1 /*
2 * arch/arm64/include/asm/arch_gicv3.h
3 *
4 * Copyright (C) 2015 ARM Ltd.
5 *
6 * This program is free software: you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
9 *
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
14 *
15 * You should have received a copy of the GNU General Public License
16 * along with this program. If not, see <http://www.gnu.org/licenses/>.
17 */
18 #ifndef __ASM_ARCH_GICV3_H
19 #define __ASM_ARCH_GICV3_H
20
21 #include <asm/sysreg.h>
22
23 #ifndef __ASSEMBLY__
24
25 #include <linux/stringify.h>
26 #include <asm/barrier.h>
27 #include <asm/cacheflush.h>
28
29 #define read_gicreg(r) read_sysreg_s(SYS_ ## r)
30 #define write_gicreg(v, r) write_sysreg_s(v, SYS_ ## r)
31
32 /*
33 * Low-level accessors
34 *
35 * These system registers are 32 bits, but we make sure that the compiler
36 * sets the GP register's most significant bits to 0 with an explicit cast.
37 */
38
gic_write_eoir(u32 irq)39 static inline void gic_write_eoir(u32 irq)
40 {
41 write_sysreg_s(irq, SYS_ICC_EOIR1_EL1);
42 isb();
43 }
44
gic_write_dir(u32 irq)45 static inline void gic_write_dir(u32 irq)
46 {
47 write_sysreg_s(irq, SYS_ICC_DIR_EL1);
48 isb();
49 }
50
gic_read_iar_common(void)51 static inline u64 gic_read_iar_common(void)
52 {
53 u64 irqstat;
54
55 irqstat = read_sysreg_s(SYS_ICC_IAR1_EL1);
56 dsb(sy);
57 return irqstat;
58 }
59
60 /*
61 * Cavium ThunderX erratum 23154
62 *
63 * The gicv3 of ThunderX requires a modified version for reading the
64 * IAR status to ensure data synchronization (access to icc_iar1_el1
65 * is not sync'ed before and after).
66 */
gic_read_iar_cavium_thunderx(void)67 static inline u64 gic_read_iar_cavium_thunderx(void)
68 {
69 u64 irqstat;
70
71 nops(8);
72 irqstat = read_sysreg_s(SYS_ICC_IAR1_EL1);
73 nops(4);
74 mb();
75
76 return irqstat;
77 }
78
gic_write_pmr(u32 val)79 static inline void gic_write_pmr(u32 val)
80 {
81 write_sysreg_s(val, SYS_ICC_PMR_EL1);
82 }
83
gic_write_ctlr(u32 val)84 static inline void gic_write_ctlr(u32 val)
85 {
86 write_sysreg_s(val, SYS_ICC_CTLR_EL1);
87 isb();
88 }
89
gic_write_grpen1(u32 val)90 static inline void gic_write_grpen1(u32 val)
91 {
92 write_sysreg_s(val, SYS_ICC_IGRPEN1_EL1);
93 isb();
94 }
95
gic_write_sgi1r(u64 val)96 static inline void gic_write_sgi1r(u64 val)
97 {
98 write_sysreg_s(val, SYS_ICC_SGI1R_EL1);
99 }
100
gic_read_sre(void)101 static inline u32 gic_read_sre(void)
102 {
103 return read_sysreg_s(SYS_ICC_SRE_EL1);
104 }
105
gic_write_sre(u32 val)106 static inline void gic_write_sre(u32 val)
107 {
108 write_sysreg_s(val, SYS_ICC_SRE_EL1);
109 isb();
110 }
111
gic_write_bpr1(u32 val)112 static inline void gic_write_bpr1(u32 val)
113 {
114 write_sysreg_s(val, SYS_ICC_BPR1_EL1);
115 }
116
117 #define gic_read_typer(c) readq_relaxed(c)
118 #define gic_write_irouter(v, c) writeq_relaxed(v, c)
119 #define gic_read_lpir(c) readq_relaxed(c)
120 #define gic_write_lpir(v, c) writeq_relaxed(v, c)
121
122 #define gic_flush_dcache_to_poc(a,l) __flush_dcache_area((a), (l))
123
124 #define gits_read_baser(c) readq_relaxed(c)
125 #define gits_write_baser(v, c) writeq_relaxed(v, c)
126
127 #define gits_read_cbaser(c) readq_relaxed(c)
128 #define gits_write_cbaser(v, c) writeq_relaxed(v, c)
129
130 #define gits_write_cwriter(v, c) writeq_relaxed(v, c)
131
132 #define gicr_read_propbaser(c) readq_relaxed(c)
133 #define gicr_write_propbaser(v, c) writeq_relaxed(v, c)
134
135 #define gicr_write_pendbaser(v, c) writeq_relaxed(v, c)
136 #define gicr_read_pendbaser(c) readq_relaxed(c)
137
138 #define gits_write_vpropbaser(v, c) writeq_relaxed(v, c)
139
140 #define gits_write_vpendbaser(v, c) writeq_relaxed(v, c)
141 #define gits_read_vpendbaser(c) readq_relaxed(c)
142
143 #endif /* __ASSEMBLY__ */
144 #endif /* __ASM_ARCH_GICV3_H */
145