1 /*
2 * Based on arch/arm/include/asm/processor.h
3 *
4 * Copyright (C) 1995-1999 Russell King
5 * Copyright (C) 2012 ARM Ltd.
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License version 2 as
9 * published by the Free Software Foundation.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 *
16 * You should have received a copy of the GNU General Public License
17 * along with this program. If not, see <http://www.gnu.org/licenses/>.
18 */
19 #ifndef __ASM_PROCESSOR_H
20 #define __ASM_PROCESSOR_H
21
22 #define TASK_SIZE_64 (UL(1) << VA_BITS)
23
24 #define KERNEL_DS UL(-1)
25 #define USER_DS (TASK_SIZE_64 - 1)
26
27 #ifndef __ASSEMBLY__
28
29 /*
30 * Default implementation of macro that returns current
31 * instruction pointer ("program counter").
32 */
33 #define current_text_addr() ({ __label__ _l; _l: &&_l;})
34
35 #ifdef __KERNEL__
36
37 #include <linux/string.h>
38
39 #include <asm/alternative.h>
40 #include <asm/cpufeature.h>
41 #include <asm/fpsimd.h>
42 #include <asm/hw_breakpoint.h>
43 #include <asm/lse.h>
44 #include <asm/pgtable-hwdef.h>
45 #include <asm/ptrace.h>
46 #include <asm/types.h>
47
48 /*
49 * TASK_SIZE - the maximum size of a user space task.
50 * TASK_UNMAPPED_BASE - the lower boundary of the mmap VM area.
51 */
52 #ifdef CONFIG_COMPAT
53 #ifdef CONFIG_ARM64_64K_PAGES
54 /*
55 * With CONFIG_ARM64_64K_PAGES enabled, the last page is occupied
56 * by the compat vectors page.
57 */
58 #define TASK_SIZE_32 UL(0x100000000)
59 #else
60 #define TASK_SIZE_32 (UL(0x100000000) - PAGE_SIZE)
61 #endif /* CONFIG_ARM64_64K_PAGES */
62 #define TASK_SIZE (test_thread_flag(TIF_32BIT) ? \
63 TASK_SIZE_32 : TASK_SIZE_64)
64 #define TASK_SIZE_OF(tsk) (test_tsk_thread_flag(tsk, TIF_32BIT) ? \
65 TASK_SIZE_32 : TASK_SIZE_64)
66 #else
67 #define TASK_SIZE TASK_SIZE_64
68 #endif /* CONFIG_COMPAT */
69
70 #define TASK_UNMAPPED_BASE (PAGE_ALIGN(TASK_SIZE / 4))
71
72 #define STACK_TOP_MAX TASK_SIZE_64
73 #ifdef CONFIG_COMPAT
74 #define AARCH32_VECTORS_BASE 0xffff0000
75 #define STACK_TOP (test_thread_flag(TIF_32BIT) ? \
76 AARCH32_VECTORS_BASE : STACK_TOP_MAX)
77 #else
78 #define STACK_TOP STACK_TOP_MAX
79 #endif /* CONFIG_COMPAT */
80
81 extern phys_addr_t arm64_dma_phys_limit;
82 #define ARCH_LOW_ADDRESS_LIMIT (arm64_dma_phys_limit - 1)
83
84 struct debug_info {
85 #ifdef CONFIG_HAVE_HW_BREAKPOINT
86 /* Have we suspended stepping by a debugger? */
87 int suspended_step;
88 /* Allow breakpoints and watchpoints to be disabled for this thread. */
89 int bps_disabled;
90 int wps_disabled;
91 /* Hardware breakpoints pinned to this task. */
92 struct perf_event *hbp_break[ARM_MAX_BRP];
93 struct perf_event *hbp_watch[ARM_MAX_WRP];
94 #endif
95 };
96
97 struct cpu_context {
98 unsigned long x19;
99 unsigned long x20;
100 unsigned long x21;
101 unsigned long x22;
102 unsigned long x23;
103 unsigned long x24;
104 unsigned long x25;
105 unsigned long x26;
106 unsigned long x27;
107 unsigned long x28;
108 unsigned long fp;
109 unsigned long sp;
110 unsigned long pc;
111 };
112
113 struct thread_struct {
114 struct cpu_context cpu_context; /* cpu context */
115 unsigned long tp_value; /* TLS register */
116 #ifdef CONFIG_COMPAT
117 unsigned long tp2_value;
118 #endif
119 struct fpsimd_state fpsimd_state;
120 unsigned long fault_address; /* fault info */
121 unsigned long fault_code; /* ESR_EL1 value */
122 struct debug_info debug; /* debugging */
123 };
124
125 #ifdef CONFIG_COMPAT
126 #define task_user_tls(t) \
127 ({ \
128 unsigned long *__tls; \
129 if (is_compat_thread(task_thread_info(t))) \
130 __tls = &(t)->thread.tp2_value; \
131 else \
132 __tls = &(t)->thread.tp_value; \
133 __tls; \
134 })
135 #else
136 #define task_user_tls(t) (&(t)->thread.tp_value)
137 #endif
138
139 /* Sync TPIDR_EL0 back to thread_struct for current */
140 void tls_preserve_current_state(void);
141
142 #define INIT_THREAD { }
143
start_thread_common(struct pt_regs * regs,unsigned long pc)144 static inline void start_thread_common(struct pt_regs *regs, unsigned long pc)
145 {
146 memset(regs, 0, sizeof(*regs));
147 forget_syscall(regs);
148 regs->pc = pc;
149 }
150
set_ssbs_bit(struct pt_regs * regs)151 static inline void set_ssbs_bit(struct pt_regs *regs)
152 {
153 regs->pstate |= PSR_SSBS_BIT;
154 }
155
set_compat_ssbs_bit(struct pt_regs * regs)156 static inline void set_compat_ssbs_bit(struct pt_regs *regs)
157 {
158 regs->pstate |= PSR_AA32_SSBS_BIT;
159 }
160
start_thread(struct pt_regs * regs,unsigned long pc,unsigned long sp)161 static inline void start_thread(struct pt_regs *regs, unsigned long pc,
162 unsigned long sp)
163 {
164 start_thread_common(regs, pc);
165 regs->pstate = PSR_MODE_EL0t;
166
167 if (arm64_get_ssbd_state() != ARM64_SSBD_FORCE_ENABLE)
168 set_ssbs_bit(regs);
169
170 regs->sp = sp;
171 }
172
173 #ifdef CONFIG_COMPAT
compat_start_thread(struct pt_regs * regs,unsigned long pc,unsigned long sp)174 static inline void compat_start_thread(struct pt_regs *regs, unsigned long pc,
175 unsigned long sp)
176 {
177 start_thread_common(regs, pc);
178 regs->pstate = COMPAT_PSR_MODE_USR;
179 if (pc & 1)
180 regs->pstate |= COMPAT_PSR_T_BIT;
181
182 #ifdef __AARCH64EB__
183 regs->pstate |= COMPAT_PSR_E_BIT;
184 #endif
185
186 if (arm64_get_ssbd_state() != ARM64_SSBD_FORCE_ENABLE)
187 set_compat_ssbs_bit(regs);
188
189 regs->compat_sp = sp;
190 }
191 #endif
192
193 /* Forward declaration, a strange C thing */
194 struct task_struct;
195
196 /* Free all resources held by a thread. */
197 extern void release_thread(struct task_struct *);
198
199 unsigned long get_wchan(struct task_struct *p);
200
cpu_relax(void)201 static inline void cpu_relax(void)
202 {
203 asm volatile("yield" ::: "memory");
204 }
205
206 /* Thread switching */
207 extern struct task_struct *cpu_switch_to(struct task_struct *prev,
208 struct task_struct *next);
209
210 #define task_pt_regs(p) \
211 ((struct pt_regs *)(THREAD_SIZE + task_stack_page(p)) - 1)
212
213 #define KSTK_EIP(tsk) ((unsigned long)task_pt_regs(tsk)->pc)
214 #define KSTK_ESP(tsk) user_stack_pointer(task_pt_regs(tsk))
215
216 /*
217 * Prefetching support
218 */
219 #define ARCH_HAS_PREFETCH
prefetch(const void * ptr)220 static inline void prefetch(const void *ptr)
221 {
222 asm volatile("prfm pldl1keep, %a0\n" : : "p" (ptr));
223 }
224
225 #define ARCH_HAS_PREFETCHW
prefetchw(const void * ptr)226 static inline void prefetchw(const void *ptr)
227 {
228 asm volatile("prfm pstl1keep, %a0\n" : : "p" (ptr));
229 }
230
231 #define ARCH_HAS_SPINLOCK_PREFETCH
spin_lock_prefetch(const void * ptr)232 static inline void spin_lock_prefetch(const void *ptr)
233 {
234 asm volatile(ARM64_LSE_ATOMIC_INSN(
235 "prfm pstl1strm, %a0",
236 "nop") : : "p" (ptr));
237 }
238
239 #define HAVE_ARCH_PICK_MMAP_LAYOUT
240
241 #endif
242
243 void cpu_enable_pan(const struct arm64_cpu_capabilities *__unused);
244 void cpu_enable_cache_maint_trap(const struct arm64_cpu_capabilities *__unused);
245
246 #endif /* __ASSEMBLY__ */
247 #endif /* __ASM_PROCESSOR_H */
248