1 /*
2 * Record and handle CPU attributes.
3 *
4 * Copyright (C) 2014 ARM Ltd.
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License version 2 as
7 * published by the Free Software Foundation.
8 *
9 * This program is distributed in the hope that it will be useful,
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 * GNU General Public License for more details.
13 *
14 * You should have received a copy of the GNU General Public License
15 * along with this program. If not, see <http://www.gnu.org/licenses/>.
16 */
17 #include <asm/arch_timer.h>
18 #include <asm/cache.h>
19 #include <asm/cpu.h>
20 #include <asm/cputype.h>
21 #include <asm/cpufeature.h>
22
23 #include <linux/bitops.h>
24 #include <linux/bug.h>
25 #include <linux/compat.h>
26 #include <linux/elf.h>
27 #include <linux/init.h>
28 #include <linux/kernel.h>
29 #include <linux/personality.h>
30 #include <linux/preempt.h>
31 #include <linux/printk.h>
32 #include <linux/seq_file.h>
33 #include <linux/sched.h>
34 #include <linux/smp.h>
35 #include <linux/delay.h>
36
37 /*
38 * In case the boot CPU is hotpluggable, we record its initial state and
39 * current state separately. Certain system registers may contain different
40 * values depending on configuration at or after reset.
41 */
42 DEFINE_PER_CPU(struct cpuinfo_arm64, cpu_data);
43 static struct cpuinfo_arm64 boot_cpu_data;
44
45 static char *icache_policy_str[] = {
46 [0 ... ICACHE_POLICY_PIPT] = "RESERVED/UNKNOWN",
47 [ICACHE_POLICY_VIPT] = "VIPT",
48 [ICACHE_POLICY_PIPT] = "PIPT",
49 [ICACHE_POLICY_VPIPT] = "VPIPT",
50 };
51
52 unsigned long __icache_flags;
53
54 static const char *const hwcap_str[] = {
55 "fp",
56 "asimd",
57 "evtstrm",
58 "aes",
59 "pmull",
60 "sha1",
61 "sha2",
62 "crc32",
63 "atomics",
64 "fphp",
65 "asimdhp",
66 "cpuid",
67 "asimdrdm",
68 "jscvt",
69 "fcma",
70 "lrcpc",
71 "dcpop",
72 "sha3",
73 "sm3",
74 "sm4",
75 "asimddp",
76 "sha512",
77 "sve",
78 "asimdfhm",
79 "dit",
80 "uscat",
81 "ilrcpc",
82 "flagm",
83 "ssbs",
84 NULL
85 };
86
87 #ifdef CONFIG_COMPAT
88 static const char *const compat_hwcap_str[] = {
89 "swp",
90 "half",
91 "thumb",
92 "26bit",
93 "fastmult",
94 "fpa",
95 "vfp",
96 "edsp",
97 "java",
98 "iwmmxt",
99 "crunch",
100 "thumbee",
101 "neon",
102 "vfpv3",
103 "vfpv3d16",
104 "tls",
105 "vfpv4",
106 "idiva",
107 "idivt",
108 "vfpd32",
109 "lpae",
110 "evtstrm",
111 NULL
112 };
113
114 static const char *const compat_hwcap2_str[] = {
115 "aes",
116 "pmull",
117 "sha1",
118 "sha2",
119 "crc32",
120 NULL
121 };
122 #endif /* CONFIG_COMPAT */
123
c_show(struct seq_file * m,void * v)124 static int c_show(struct seq_file *m, void *v)
125 {
126 int i, j;
127 bool compat = personality(current->personality) == PER_LINUX32;
128
129 for_each_online_cpu(i) {
130 struct cpuinfo_arm64 *cpuinfo = &per_cpu(cpu_data, i);
131 u32 midr = cpuinfo->reg_midr;
132
133 /*
134 * glibc reads /proc/cpuinfo to determine the number of
135 * online processors, looking for lines beginning with
136 * "processor". Give glibc what it expects.
137 */
138 seq_printf(m, "processor\t: %d\n", i);
139 if (compat)
140 seq_printf(m, "model name\t: ARMv8 Processor rev %d (%s)\n",
141 MIDR_REVISION(midr), COMPAT_ELF_PLATFORM);
142
143 seq_printf(m, "BogoMIPS\t: %lu.%02lu\n",
144 loops_per_jiffy / (500000UL/HZ),
145 loops_per_jiffy / (5000UL/HZ) % 100);
146
147 /*
148 * Dump out the common processor features in a single line.
149 * Userspace should read the hwcaps with getauxval(AT_HWCAP)
150 * rather than attempting to parse this, but there's a body of
151 * software which does already (at least for 32-bit).
152 */
153 seq_puts(m, "Features\t:");
154 if (compat) {
155 #ifdef CONFIG_COMPAT
156 for (j = 0; compat_hwcap_str[j]; j++)
157 if (compat_elf_hwcap & (1 << j))
158 seq_printf(m, " %s", compat_hwcap_str[j]);
159
160 for (j = 0; compat_hwcap2_str[j]; j++)
161 if (compat_elf_hwcap2 & (1 << j))
162 seq_printf(m, " %s", compat_hwcap2_str[j]);
163 #endif /* CONFIG_COMPAT */
164 } else {
165 for (j = 0; hwcap_str[j]; j++)
166 if (elf_hwcap & (1 << j))
167 seq_printf(m, " %s", hwcap_str[j]);
168 }
169 seq_puts(m, "\n");
170
171 seq_printf(m, "CPU implementer\t: 0x%02x\n",
172 MIDR_IMPLEMENTOR(midr));
173 seq_printf(m, "CPU architecture: 8\n");
174 seq_printf(m, "CPU variant\t: 0x%x\n", MIDR_VARIANT(midr));
175 seq_printf(m, "CPU part\t: 0x%03x\n", MIDR_PARTNUM(midr));
176 seq_printf(m, "CPU revision\t: %d\n\n", MIDR_REVISION(midr));
177 }
178
179 return 0;
180 }
181
c_start(struct seq_file * m,loff_t * pos)182 static void *c_start(struct seq_file *m, loff_t *pos)
183 {
184 return *pos < 1 ? (void *)1 : NULL;
185 }
186
c_next(struct seq_file * m,void * v,loff_t * pos)187 static void *c_next(struct seq_file *m, void *v, loff_t *pos)
188 {
189 ++*pos;
190 return NULL;
191 }
192
c_stop(struct seq_file * m,void * v)193 static void c_stop(struct seq_file *m, void *v)
194 {
195 }
196
197 const struct seq_operations cpuinfo_op = {
198 .start = c_start,
199 .next = c_next,
200 .stop = c_stop,
201 .show = c_show
202 };
203
204
205 static struct kobj_type cpuregs_kobj_type = {
206 .sysfs_ops = &kobj_sysfs_ops,
207 };
208
209 /*
210 * The ARM ARM uses the phrase "32-bit register" to describe a register
211 * whose upper 32 bits are RES0 (per C5.1.1, ARM DDI 0487A.i), however
212 * no statement is made as to whether the upper 32 bits will or will not
213 * be made use of in future, and between ARM DDI 0487A.c and ARM DDI
214 * 0487A.d CLIDR_EL1 was expanded from 32-bit to 64-bit.
215 *
216 * Thus, while both MIDR_EL1 and REVIDR_EL1 are described as 32-bit
217 * registers, we expose them both as 64 bit values to cater for possible
218 * future expansion without an ABI break.
219 */
220 #define kobj_to_cpuinfo(kobj) container_of(kobj, struct cpuinfo_arm64, kobj)
221 #define CPUREGS_ATTR_RO(_name, _field) \
222 static ssize_t _name##_show(struct kobject *kobj, \
223 struct kobj_attribute *attr, char *buf) \
224 { \
225 struct cpuinfo_arm64 *info = kobj_to_cpuinfo(kobj); \
226 \
227 if (info->reg_midr) \
228 return sprintf(buf, "0x%016x\n", info->reg_##_field); \
229 else \
230 return 0; \
231 } \
232 static struct kobj_attribute cpuregs_attr_##_name = __ATTR_RO(_name)
233
234 CPUREGS_ATTR_RO(midr_el1, midr);
235 CPUREGS_ATTR_RO(revidr_el1, revidr);
236
237 static struct attribute *cpuregs_id_attrs[] = {
238 &cpuregs_attr_midr_el1.attr,
239 &cpuregs_attr_revidr_el1.attr,
240 NULL
241 };
242
243 static const struct attribute_group cpuregs_attr_group = {
244 .attrs = cpuregs_id_attrs,
245 .name = "identification"
246 };
247
cpuid_cpu_online(unsigned int cpu)248 static int cpuid_cpu_online(unsigned int cpu)
249 {
250 int rc;
251 struct device *dev;
252 struct cpuinfo_arm64 *info = &per_cpu(cpu_data, cpu);
253
254 dev = get_cpu_device(cpu);
255 if (!dev) {
256 rc = -ENODEV;
257 goto out;
258 }
259 rc = kobject_add(&info->kobj, &dev->kobj, "regs");
260 if (rc)
261 goto out;
262 rc = sysfs_create_group(&info->kobj, &cpuregs_attr_group);
263 if (rc)
264 kobject_del(&info->kobj);
265 out:
266 return rc;
267 }
268
cpuid_cpu_offline(unsigned int cpu)269 static int cpuid_cpu_offline(unsigned int cpu)
270 {
271 struct device *dev;
272 struct cpuinfo_arm64 *info = &per_cpu(cpu_data, cpu);
273
274 dev = get_cpu_device(cpu);
275 if (!dev)
276 return -ENODEV;
277 if (info->kobj.parent) {
278 sysfs_remove_group(&info->kobj, &cpuregs_attr_group);
279 kobject_del(&info->kobj);
280 }
281
282 return 0;
283 }
284
cpuinfo_regs_init(void)285 static int __init cpuinfo_regs_init(void)
286 {
287 int cpu, ret;
288
289 for_each_possible_cpu(cpu) {
290 struct cpuinfo_arm64 *info = &per_cpu(cpu_data, cpu);
291
292 kobject_init(&info->kobj, &cpuregs_kobj_type);
293 }
294
295 ret = cpuhp_setup_state(CPUHP_AP_ONLINE_DYN, "arm64/cpuinfo:online",
296 cpuid_cpu_online, cpuid_cpu_offline);
297 if (ret < 0) {
298 pr_err("cpuinfo: failed to register hotplug callbacks.\n");
299 return ret;
300 }
301 return 0;
302 }
cpuinfo_detect_icache_policy(struct cpuinfo_arm64 * info)303 static void cpuinfo_detect_icache_policy(struct cpuinfo_arm64 *info)
304 {
305 unsigned int cpu = smp_processor_id();
306 u32 l1ip = CTR_L1IP(info->reg_ctr);
307
308 switch (l1ip) {
309 case ICACHE_POLICY_PIPT:
310 break;
311 case ICACHE_POLICY_VPIPT:
312 set_bit(ICACHEF_VPIPT, &__icache_flags);
313 break;
314 default:
315 /* Fallthrough */
316 case ICACHE_POLICY_VIPT:
317 /* Assume aliasing */
318 set_bit(ICACHEF_ALIASING, &__icache_flags);
319 }
320
321 pr_info("Detected %s I-cache on CPU%d\n", icache_policy_str[l1ip], cpu);
322 }
323
__cpuinfo_store_cpu(struct cpuinfo_arm64 * info)324 static void __cpuinfo_store_cpu(struct cpuinfo_arm64 *info)
325 {
326 info->reg_cntfrq = arch_timer_get_cntfrq();
327 info->reg_ctr = read_cpuid_cachetype();
328 info->reg_dczid = read_cpuid(DCZID_EL0);
329 info->reg_midr = read_cpuid_id();
330 info->reg_revidr = read_cpuid(REVIDR_EL1);
331
332 info->reg_id_aa64dfr0 = read_cpuid(ID_AA64DFR0_EL1);
333 info->reg_id_aa64dfr1 = read_cpuid(ID_AA64DFR1_EL1);
334 info->reg_id_aa64isar0 = read_cpuid(ID_AA64ISAR0_EL1);
335 info->reg_id_aa64isar1 = read_cpuid(ID_AA64ISAR1_EL1);
336 info->reg_id_aa64mmfr0 = read_cpuid(ID_AA64MMFR0_EL1);
337 info->reg_id_aa64mmfr1 = read_cpuid(ID_AA64MMFR1_EL1);
338 info->reg_id_aa64mmfr2 = read_cpuid(ID_AA64MMFR2_EL1);
339 info->reg_id_aa64pfr0 = read_cpuid(ID_AA64PFR0_EL1);
340 info->reg_id_aa64pfr1 = read_cpuid(ID_AA64PFR1_EL1);
341
342 /* Update the 32bit ID registers only if AArch32 is implemented */
343 if (id_aa64pfr0_32bit_el0(info->reg_id_aa64pfr0)) {
344 info->reg_id_dfr0 = read_cpuid(ID_DFR0_EL1);
345 info->reg_id_isar0 = read_cpuid(ID_ISAR0_EL1);
346 info->reg_id_isar1 = read_cpuid(ID_ISAR1_EL1);
347 info->reg_id_isar2 = read_cpuid(ID_ISAR2_EL1);
348 info->reg_id_isar3 = read_cpuid(ID_ISAR3_EL1);
349 info->reg_id_isar4 = read_cpuid(ID_ISAR4_EL1);
350 info->reg_id_isar5 = read_cpuid(ID_ISAR5_EL1);
351 info->reg_id_mmfr0 = read_cpuid(ID_MMFR0_EL1);
352 info->reg_id_mmfr1 = read_cpuid(ID_MMFR1_EL1);
353 info->reg_id_mmfr2 = read_cpuid(ID_MMFR2_EL1);
354 info->reg_id_mmfr3 = read_cpuid(ID_MMFR3_EL1);
355 info->reg_id_pfr0 = read_cpuid(ID_PFR0_EL1);
356 info->reg_id_pfr1 = read_cpuid(ID_PFR1_EL1);
357
358 info->reg_mvfr0 = read_cpuid(MVFR0_EL1);
359 info->reg_mvfr1 = read_cpuid(MVFR1_EL1);
360 info->reg_mvfr2 = read_cpuid(MVFR2_EL1);
361 }
362
363 cpuinfo_detect_icache_policy(info);
364 }
365
cpuinfo_store_cpu(void)366 void cpuinfo_store_cpu(void)
367 {
368 struct cpuinfo_arm64 *info = this_cpu_ptr(&cpu_data);
369 __cpuinfo_store_cpu(info);
370 update_cpu_features(smp_processor_id(), info, &boot_cpu_data);
371 }
372
cpuinfo_store_boot_cpu(void)373 void __init cpuinfo_store_boot_cpu(void)
374 {
375 struct cpuinfo_arm64 *info = &per_cpu(cpu_data, 0);
376 __cpuinfo_store_cpu(info);
377
378 boot_cpu_data = *info;
379 init_cpu_features(&boot_cpu_data);
380 }
381
382 device_initcall(cpuinfo_regs_init);
383