1 // SPDX-License-Identifier: GPL-2.0
2 /*
3 * linux/arch/cris/kernel/irq.c
4 *
5 * Copyright (c) 2000-2002 Axis Communications AB
6 *
7 * Authors: Bjorn Wesen (bjornw@axis.com)
8 *
9 * This file contains the interrupt vectors and some
10 * helper functions
11 *
12 */
13
14 #include <asm/irq.h>
15 #include <asm/current.h>
16 #include <linux/irq.h>
17 #include <linux/interrupt.h>
18 #include <linux/kernel.h>
19 #include <linux/init.h>
20
21 #define crisv10_mask_irq(irq_nr) (*R_VECT_MASK_CLR = 1 << (irq_nr));
22 #define crisv10_unmask_irq(irq_nr) (*R_VECT_MASK_SET = 1 << (irq_nr));
23
24 extern void kgdb_init(void);
25 extern void breakpoint(void);
26
27 /* don't use set_int_vector, it bypasses the linux interrupt handlers. it is
28 * global just so that the kernel gdb can use it.
29 */
30
31 void
set_int_vector(int n,irqvectptr addr)32 set_int_vector(int n, irqvectptr addr)
33 {
34 etrax_irv->v[n + 0x20] = (irqvectptr)addr;
35 }
36
37 /* the breakpoint vector is obviously not made just like the normal irq handlers
38 * but needs to contain _code_ to jump to addr.
39 *
40 * the BREAK n instruction jumps to IBR + n * 8
41 */
42
43 void
set_break_vector(int n,irqvectptr addr)44 set_break_vector(int n, irqvectptr addr)
45 {
46 unsigned short *jinstr = (unsigned short *)&etrax_irv->v[n*2];
47 unsigned long *jaddr = (unsigned long *)(jinstr + 1);
48
49 /* if you don't know what this does, do not touch it! */
50
51 *jinstr = 0x0d3f;
52 *jaddr = (unsigned long)addr;
53
54 /* 00000026 <clrlop+1a> 3f0d82000000 jump 0x82 */
55 }
56
57 /*
58 * This builds up the IRQ handler stubs using some ugly macros in irq.h
59 *
60 * These macros create the low-level assembly IRQ routines that do all
61 * the operations that are needed. They are also written to be fast - and to
62 * disable interrupts as little as humanly possible.
63 *
64 */
65
66 /* IRQ0 and 1 are special traps */
67 void hwbreakpoint(void);
68 void IRQ1_interrupt(void);
69 BUILD_TIMER_IRQ(2, 0x04) /* the timer interrupt is somewhat special */
70 BUILD_IRQ(3, 0x08)
71 BUILD_IRQ(4, 0x10)
72 BUILD_IRQ(5, 0x20)
73 BUILD_IRQ(6, 0x40)
74 BUILD_IRQ(7, 0x80)
75 BUILD_IRQ(8, 0x100)
76 BUILD_IRQ(9, 0x200)
77 BUILD_IRQ(10, 0x400)
78 BUILD_IRQ(11, 0x800)
79 BUILD_IRQ(12, 0x1000)
80 BUILD_IRQ(13, 0x2000)
81 void mmu_bus_fault(void); /* IRQ 14 is the bus fault interrupt */
82 void multiple_interrupt(void); /* IRQ 15 is the multiple IRQ interrupt */
83 BUILD_IRQ(16, 0x10000 | 0x20000) /* ethernet tx interrupt needs to block rx */
84 BUILD_IRQ(17, 0x20000 | 0x10000) /* ...and vice versa */
85 BUILD_IRQ(18, 0x40000)
86 BUILD_IRQ(19, 0x80000)
87 BUILD_IRQ(20, 0x100000)
88 BUILD_IRQ(21, 0x200000)
89 BUILD_IRQ(22, 0x400000)
90 BUILD_IRQ(23, 0x800000)
91 BUILD_IRQ(24, 0x1000000)
92 BUILD_IRQ(25, 0x2000000)
93 /* IRQ 26-30 are reserved */
94 BUILD_IRQ(31, 0x80000000)
95
96 /*
97 * Pointers to the low-level handlers
98 */
99
100 static void (*interrupt[NR_IRQS])(void) = {
101 NULL, NULL, IRQ2_interrupt, IRQ3_interrupt,
102 IRQ4_interrupt, IRQ5_interrupt, IRQ6_interrupt, IRQ7_interrupt,
103 IRQ8_interrupt, IRQ9_interrupt, IRQ10_interrupt, IRQ11_interrupt,
104 IRQ12_interrupt, IRQ13_interrupt, NULL, NULL,
105 IRQ16_interrupt, IRQ17_interrupt, IRQ18_interrupt, IRQ19_interrupt,
106 IRQ20_interrupt, IRQ21_interrupt, IRQ22_interrupt, IRQ23_interrupt,
107 IRQ24_interrupt, IRQ25_interrupt, NULL, NULL, NULL, NULL, NULL,
108 IRQ31_interrupt
109 };
110
enable_crisv10_irq(struct irq_data * data)111 static void enable_crisv10_irq(struct irq_data *data)
112 {
113 crisv10_unmask_irq(data->irq);
114 }
115
disable_crisv10_irq(struct irq_data * data)116 static void disable_crisv10_irq(struct irq_data *data)
117 {
118 crisv10_mask_irq(data->irq);
119 }
120
121 static struct irq_chip crisv10_irq_type = {
122 .name = "CRISv10",
123 .irq_shutdown = disable_crisv10_irq,
124 .irq_enable = enable_crisv10_irq,
125 .irq_disable = disable_crisv10_irq,
126 };
127
128 void weird_irq(void);
129 void system_call(void); /* from entry.S */
130 void do_sigtrap(void); /* from entry.S */
131 void gdb_handle_breakpoint(void); /* from entry.S */
132
133 extern void do_IRQ(int irq, struct pt_regs * regs);
134
135 /* Handle multiple IRQs */
do_multiple_IRQ(struct pt_regs * regs)136 void do_multiple_IRQ(struct pt_regs* regs)
137 {
138 int bit;
139 unsigned masked;
140 unsigned mask;
141 unsigned ethmask = 0;
142
143 /* Get interrupts to mask and handle */
144 mask = masked = *R_VECT_MASK_RD;
145
146 /* Never mask timer IRQ */
147 mask &= ~(IO_MASK(R_VECT_MASK_RD, timer0));
148
149 /*
150 * If either ethernet interrupt (rx or tx) is active then block
151 * the other one too. Unblock afterwards also.
152 */
153 if (mask &
154 (IO_STATE(R_VECT_MASK_RD, dma0, active) |
155 IO_STATE(R_VECT_MASK_RD, dma1, active))) {
156 ethmask = (IO_MASK(R_VECT_MASK_RD, dma0) |
157 IO_MASK(R_VECT_MASK_RD, dma1));
158 }
159
160 /* Block them */
161 *R_VECT_MASK_CLR = (mask | ethmask);
162
163 /* An extra irq_enter here to prevent softIRQs to run after
164 * each do_IRQ. This will decrease the interrupt latency.
165 */
166 irq_enter();
167
168 /* Handle all IRQs */
169 for (bit = 2; bit < 32; bit++) {
170 if (masked & (1 << bit)) {
171 do_IRQ(bit, regs);
172 }
173 }
174
175 /* This irq_exit() will trigger the soft IRQs. */
176 irq_exit();
177
178 /* Unblock the IRQs again */
179 *R_VECT_MASK_SET = (masked | ethmask);
180 }
181
182 /* init_IRQ() is called by start_kernel and is responsible for fixing IRQ masks and
183 setting the irq vector table.
184 */
185
init_IRQ(void)186 void __init init_IRQ(void)
187 {
188 int i;
189
190 /* clear all interrupt masks */
191 *R_IRQ_MASK0_CLR = 0xffffffff;
192 *R_IRQ_MASK1_CLR = 0xffffffff;
193 *R_IRQ_MASK2_CLR = 0xffffffff;
194 *R_VECT_MASK_CLR = 0xffffffff;
195
196 for (i = 0; i < 256; i++)
197 etrax_irv->v[i] = weird_irq;
198
199 /* Initialize IRQ handler descriptors. */
200 for(i = 2; i < NR_IRQS; i++) {
201 irq_set_chip_and_handler(i, &crisv10_irq_type,
202 handle_simple_irq);
203 set_int_vector(i, interrupt[i]);
204 }
205
206 /* the entries in the break vector contain actual code to be
207 executed by the associated break handler, rather than just a jump
208 address. therefore we need to setup a default breakpoint handler
209 for all breakpoints */
210 for (i = 0; i < 16; i++)
211 set_break_vector(i, do_sigtrap);
212
213 /* except IRQ 15 which is the multiple-IRQ handler on Etrax100 */
214 set_int_vector(15, multiple_interrupt);
215
216 /* 0 and 1 which are special breakpoint/NMI traps */
217 set_int_vector(0, hwbreakpoint);
218 set_int_vector(1, IRQ1_interrupt);
219
220 /* and irq 14 which is the mmu bus fault handler */
221 set_int_vector(14, mmu_bus_fault);
222
223 /* setup the system-call trap, which is reached by BREAK 13 */
224 set_break_vector(13, system_call);
225
226 /* setup a breakpoint handler for debugging used for both user and
227 kernel mode debugging (which is why it is not inside an ifdef
228 CONFIG_ETRAX_KGDB) */
229 set_break_vector(8, gdb_handle_breakpoint);
230
231 #ifdef CONFIG_ETRAX_KGDB
232 /* setup kgdb if its enabled, and break into the debugger */
233 kgdb_init();
234 breakpoint();
235 #endif
236 }
237