1 /* SPDX-License-Identifier: GPL-2.0 */ 2 #ifndef __ddr2_defs_asm_h 3 #define __ddr2_defs_asm_h 4 5 /* 6 * This file is autogenerated from 7 * file: ddr2.r 8 * 9 * by ../../../tools/rdesc/bin/rdes2c -asm -outfile ddr2_defs_asm.h ddr2.r 10 * Any changes here will be lost. 11 * 12 * -*- buffer-read-only: t -*- 13 */ 14 15 #ifndef REG_FIELD 16 #define REG_FIELD( scope, reg, field, value ) \ 17 REG_FIELD_X_( value, reg_##scope##_##reg##___##field##___lsb ) 18 #define REG_FIELD_X_( value, shift ) ((value) << shift) 19 #endif 20 21 #ifndef REG_STATE 22 #define REG_STATE( scope, reg, field, symbolic_value ) \ 23 REG_STATE_X_( regk_##scope##_##symbolic_value, reg_##scope##_##reg##___##field##___lsb ) 24 #define REG_STATE_X_( k, shift ) (k << shift) 25 #endif 26 27 #ifndef REG_MASK 28 #define REG_MASK( scope, reg, field ) \ 29 REG_MASK_X_( reg_##scope##_##reg##___##field##___width, reg_##scope##_##reg##___##field##___lsb ) 30 #define REG_MASK_X_( width, lsb ) (((1 << width)-1) << lsb) 31 #endif 32 33 #ifndef REG_LSB 34 #define REG_LSB( scope, reg, field ) reg_##scope##_##reg##___##field##___lsb 35 #endif 36 37 #ifndef REG_BIT 38 #define REG_BIT( scope, reg, field ) reg_##scope##_##reg##___##field##___bit 39 #endif 40 41 #ifndef REG_ADDR 42 #define REG_ADDR( scope, inst, reg ) REG_ADDR_X_(inst, reg_##scope##_##reg##_offset) 43 #define REG_ADDR_X_( inst, offs ) ((inst) + offs) 44 #endif 45 46 #ifndef REG_ADDR_VECT 47 #define REG_ADDR_VECT( scope, inst, reg, index ) \ 48 REG_ADDR_VECT_X_(inst, reg_##scope##_##reg##_offset, index, \ 49 STRIDE_##scope##_##reg ) 50 #define REG_ADDR_VECT_X_( inst, offs, index, stride ) \ 51 ((inst) + offs + (index) * stride) 52 #endif 53 54 /* Register rw_cfg, scope ddr2, type rw */ 55 #define reg_ddr2_rw_cfg___col_width___lsb 0 56 #define reg_ddr2_rw_cfg___col_width___width 4 57 #define reg_ddr2_rw_cfg___nr_banks___lsb 4 58 #define reg_ddr2_rw_cfg___nr_banks___width 1 59 #define reg_ddr2_rw_cfg___nr_banks___bit 4 60 #define reg_ddr2_rw_cfg___bw___lsb 5 61 #define reg_ddr2_rw_cfg___bw___width 1 62 #define reg_ddr2_rw_cfg___bw___bit 5 63 #define reg_ddr2_rw_cfg___nr_ref___lsb 6 64 #define reg_ddr2_rw_cfg___nr_ref___width 4 65 #define reg_ddr2_rw_cfg___ref_interval___lsb 10 66 #define reg_ddr2_rw_cfg___ref_interval___width 11 67 #define reg_ddr2_rw_cfg___odt_ctrl___lsb 21 68 #define reg_ddr2_rw_cfg___odt_ctrl___width 2 69 #define reg_ddr2_rw_cfg___odt_mem___lsb 23 70 #define reg_ddr2_rw_cfg___odt_mem___width 1 71 #define reg_ddr2_rw_cfg___odt_mem___bit 23 72 #define reg_ddr2_rw_cfg___imp_strength___lsb 24 73 #define reg_ddr2_rw_cfg___imp_strength___width 1 74 #define reg_ddr2_rw_cfg___imp_strength___bit 24 75 #define reg_ddr2_rw_cfg___auto_imp_cal___lsb 25 76 #define reg_ddr2_rw_cfg___auto_imp_cal___width 1 77 #define reg_ddr2_rw_cfg___auto_imp_cal___bit 25 78 #define reg_ddr2_rw_cfg___imp_cal_override___lsb 26 79 #define reg_ddr2_rw_cfg___imp_cal_override___width 1 80 #define reg_ddr2_rw_cfg___imp_cal_override___bit 26 81 #define reg_ddr2_rw_cfg___dll_override___lsb 27 82 #define reg_ddr2_rw_cfg___dll_override___width 1 83 #define reg_ddr2_rw_cfg___dll_override___bit 27 84 #define reg_ddr2_rw_cfg_offset 0 85 86 /* Register rw_timing, scope ddr2, type rw */ 87 #define reg_ddr2_rw_timing___wr___lsb 0 88 #define reg_ddr2_rw_timing___wr___width 3 89 #define reg_ddr2_rw_timing___rcd___lsb 3 90 #define reg_ddr2_rw_timing___rcd___width 3 91 #define reg_ddr2_rw_timing___rp___lsb 6 92 #define reg_ddr2_rw_timing___rp___width 3 93 #define reg_ddr2_rw_timing___ras___lsb 9 94 #define reg_ddr2_rw_timing___ras___width 4 95 #define reg_ddr2_rw_timing___rfc___lsb 13 96 #define reg_ddr2_rw_timing___rfc___width 7 97 #define reg_ddr2_rw_timing___rc___lsb 20 98 #define reg_ddr2_rw_timing___rc___width 5 99 #define reg_ddr2_rw_timing___rtp___lsb 25 100 #define reg_ddr2_rw_timing___rtp___width 2 101 #define reg_ddr2_rw_timing___rtw___lsb 27 102 #define reg_ddr2_rw_timing___rtw___width 3 103 #define reg_ddr2_rw_timing___wtr___lsb 30 104 #define reg_ddr2_rw_timing___wtr___width 2 105 #define reg_ddr2_rw_timing_offset 4 106 107 /* Register rw_latency, scope ddr2, type rw */ 108 #define reg_ddr2_rw_latency___cas___lsb 0 109 #define reg_ddr2_rw_latency___cas___width 3 110 #define reg_ddr2_rw_latency___additive___lsb 3 111 #define reg_ddr2_rw_latency___additive___width 3 112 #define reg_ddr2_rw_latency_offset 8 113 114 /* Register rw_phy_cfg, scope ddr2, type rw */ 115 #define reg_ddr2_rw_phy_cfg___en___lsb 0 116 #define reg_ddr2_rw_phy_cfg___en___width 1 117 #define reg_ddr2_rw_phy_cfg___en___bit 0 118 #define reg_ddr2_rw_phy_cfg_offset 12 119 120 /* Register rw_phy_ctrl, scope ddr2, type rw */ 121 #define reg_ddr2_rw_phy_ctrl___rst___lsb 0 122 #define reg_ddr2_rw_phy_ctrl___rst___width 1 123 #define reg_ddr2_rw_phy_ctrl___rst___bit 0 124 #define reg_ddr2_rw_phy_ctrl___cal_rst___lsb 1 125 #define reg_ddr2_rw_phy_ctrl___cal_rst___width 1 126 #define reg_ddr2_rw_phy_ctrl___cal_rst___bit 1 127 #define reg_ddr2_rw_phy_ctrl___cal_start___lsb 2 128 #define reg_ddr2_rw_phy_ctrl___cal_start___width 1 129 #define reg_ddr2_rw_phy_ctrl___cal_start___bit 2 130 #define reg_ddr2_rw_phy_ctrl_offset 16 131 132 /* Register rw_ctrl, scope ddr2, type rw */ 133 #define reg_ddr2_rw_ctrl___mrs_data___lsb 0 134 #define reg_ddr2_rw_ctrl___mrs_data___width 16 135 #define reg_ddr2_rw_ctrl___cmd___lsb 16 136 #define reg_ddr2_rw_ctrl___cmd___width 8 137 #define reg_ddr2_rw_ctrl_offset 20 138 139 /* Register rw_pwr_down, scope ddr2, type rw */ 140 #define reg_ddr2_rw_pwr_down___self_ref___lsb 0 141 #define reg_ddr2_rw_pwr_down___self_ref___width 2 142 #define reg_ddr2_rw_pwr_down___phy_en___lsb 2 143 #define reg_ddr2_rw_pwr_down___phy_en___width 1 144 #define reg_ddr2_rw_pwr_down___phy_en___bit 2 145 #define reg_ddr2_rw_pwr_down_offset 24 146 147 /* Register r_stat, scope ddr2, type r */ 148 #define reg_ddr2_r_stat___dll_lock___lsb 0 149 #define reg_ddr2_r_stat___dll_lock___width 1 150 #define reg_ddr2_r_stat___dll_lock___bit 0 151 #define reg_ddr2_r_stat___dll_delay_code___lsb 1 152 #define reg_ddr2_r_stat___dll_delay_code___width 7 153 #define reg_ddr2_r_stat___imp_cal_done___lsb 8 154 #define reg_ddr2_r_stat___imp_cal_done___width 1 155 #define reg_ddr2_r_stat___imp_cal_done___bit 8 156 #define reg_ddr2_r_stat___imp_cal_fault___lsb 9 157 #define reg_ddr2_r_stat___imp_cal_fault___width 1 158 #define reg_ddr2_r_stat___imp_cal_fault___bit 9 159 #define reg_ddr2_r_stat___cal_imp_pu___lsb 10 160 #define reg_ddr2_r_stat___cal_imp_pu___width 4 161 #define reg_ddr2_r_stat___cal_imp_pd___lsb 14 162 #define reg_ddr2_r_stat___cal_imp_pd___width 4 163 #define reg_ddr2_r_stat_offset 28 164 165 /* Register rw_imp_ctrl, scope ddr2, type rw */ 166 #define reg_ddr2_rw_imp_ctrl___imp_pu___lsb 0 167 #define reg_ddr2_rw_imp_ctrl___imp_pu___width 4 168 #define reg_ddr2_rw_imp_ctrl___imp_pd___lsb 4 169 #define reg_ddr2_rw_imp_ctrl___imp_pd___width 4 170 #define reg_ddr2_rw_imp_ctrl_offset 32 171 172 #define STRIDE_ddr2_rw_dll_ctrl 4 173 /* Register rw_dll_ctrl, scope ddr2, type rw */ 174 #define reg_ddr2_rw_dll_ctrl___mode___lsb 0 175 #define reg_ddr2_rw_dll_ctrl___mode___width 1 176 #define reg_ddr2_rw_dll_ctrl___mode___bit 0 177 #define reg_ddr2_rw_dll_ctrl___clk_delay___lsb 1 178 #define reg_ddr2_rw_dll_ctrl___clk_delay___width 7 179 #define reg_ddr2_rw_dll_ctrl_offset 36 180 181 #define STRIDE_ddr2_rw_dqs_dll_ctrl 4 182 /* Register rw_dqs_dll_ctrl, scope ddr2, type rw */ 183 #define reg_ddr2_rw_dqs_dll_ctrl___dqs90_delay___lsb 0 184 #define reg_ddr2_rw_dqs_dll_ctrl___dqs90_delay___width 7 185 #define reg_ddr2_rw_dqs_dll_ctrl___dqs180_delay___lsb 7 186 #define reg_ddr2_rw_dqs_dll_ctrl___dqs180_delay___width 7 187 #define reg_ddr2_rw_dqs_dll_ctrl___dqs270_delay___lsb 14 188 #define reg_ddr2_rw_dqs_dll_ctrl___dqs270_delay___width 7 189 #define reg_ddr2_rw_dqs_dll_ctrl___dqs360_delay___lsb 21 190 #define reg_ddr2_rw_dqs_dll_ctrl___dqs360_delay___width 7 191 #define reg_ddr2_rw_dqs_dll_ctrl_offset 52 192 193 194 /* Constants */ 195 #define regk_ddr2_al0 0x00000000 196 #define regk_ddr2_al1 0x00000008 197 #define regk_ddr2_al2 0x00000010 198 #define regk_ddr2_al3 0x00000018 199 #define regk_ddr2_al4 0x00000020 200 #define regk_ddr2_auto 0x00000003 201 #define regk_ddr2_bank4 0x00000000 202 #define regk_ddr2_bank8 0x00000001 203 #define regk_ddr2_bl4 0x00000002 204 #define regk_ddr2_bl8 0x00000003 205 #define regk_ddr2_bt_il 0x00000008 206 #define regk_ddr2_bt_seq 0x00000000 207 #define regk_ddr2_bw16 0x00000001 208 #define regk_ddr2_bw32 0x00000000 209 #define regk_ddr2_cas2 0x00000020 210 #define regk_ddr2_cas3 0x00000030 211 #define regk_ddr2_cas4 0x00000040 212 #define regk_ddr2_cas5 0x00000050 213 #define regk_ddr2_deselect 0x000000c0 214 #define regk_ddr2_dic_weak 0x00000002 215 #define regk_ddr2_direct 0x00000001 216 #define regk_ddr2_dis 0x00000000 217 #define regk_ddr2_dll_dis 0x00000001 218 #define regk_ddr2_dll_en 0x00000000 219 #define regk_ddr2_dll_rst 0x00000100 220 #define regk_ddr2_emrs 0x00000081 221 #define regk_ddr2_emrs2 0x00000082 222 #define regk_ddr2_emrs3 0x00000083 223 #define regk_ddr2_full 0x00000001 224 #define regk_ddr2_hi_ref_rate 0x00000080 225 #define regk_ddr2_mrs 0x00000080 226 #define regk_ddr2_no 0x00000000 227 #define regk_ddr2_nop 0x000000b8 228 #define regk_ddr2_ocd_adj 0x00000200 229 #define regk_ddr2_ocd_default 0x00000380 230 #define regk_ddr2_ocd_drive0 0x00000100 231 #define regk_ddr2_ocd_drive1 0x00000080 232 #define regk_ddr2_ocd_exit 0x00000000 233 #define regk_ddr2_odt_dis 0x00000000 234 #define regk_ddr2_offs 0x00000000 235 #define regk_ddr2_pre 0x00000090 236 #define regk_ddr2_pre_all 0x00000400 237 #define regk_ddr2_pwr_down_fast 0x00000000 238 #define regk_ddr2_pwr_down_slow 0x00001000 239 #define regk_ddr2_ref 0x00000088 240 #define regk_ddr2_rtt150 0x00000040 241 #define regk_ddr2_rtt50 0x00000044 242 #define regk_ddr2_rtt75 0x00000004 243 #define regk_ddr2_rw_cfg_default 0x00186000 244 #define regk_ddr2_rw_dll_ctrl_default 0x00000000 245 #define regk_ddr2_rw_dll_ctrl_size 0x00000004 246 #define regk_ddr2_rw_dqs_dll_ctrl_default 0x00000000 247 #define regk_ddr2_rw_dqs_dll_ctrl_size 0x00000004 248 #define regk_ddr2_rw_latency_default 0x00000000 249 #define regk_ddr2_rw_phy_cfg_default 0x00000000 250 #define regk_ddr2_rw_pwr_down_default 0x00000000 251 #define regk_ddr2_rw_timing_default 0x00000000 252 #define regk_ddr2_s1Gb 0x0000001a 253 #define regk_ddr2_s256Mb 0x0000000f 254 #define regk_ddr2_s2Gb 0x00000027 255 #define regk_ddr2_s4Gb 0x00000042 256 #define regk_ddr2_s512Mb 0x00000015 257 #define regk_ddr2_temp0_85 0x00000618 258 #define regk_ddr2_temp85_95 0x0000030c 259 #define regk_ddr2_term150 0x00000002 260 #define regk_ddr2_term50 0x00000003 261 #define regk_ddr2_term75 0x00000001 262 #define regk_ddr2_test 0x00000080 263 #define regk_ddr2_weak 0x00000000 264 #define regk_ddr2_wr2 0x00000200 265 #define regk_ddr2_wr3 0x00000400 266 #define regk_ddr2_yes 0x00000001 267 #endif /* __ddr2_defs_asm_h */ 268