1 /* SPDX-License-Identifier: GPL-2.0 */ 2 #ifndef __gio_defs_asm_h 3 #define __gio_defs_asm_h 4 5 /* 6 * This file is autogenerated from 7 * file: gio.r 8 * 9 * by ../../../tools/rdesc/bin/rdes2c -asm -outfile gio_defs_asm.h gio.r 10 * Any changes here will be lost. 11 * 12 * -*- buffer-read-only: t -*- 13 */ 14 15 #ifndef REG_FIELD 16 #define REG_FIELD( scope, reg, field, value ) \ 17 REG_FIELD_X_( value, reg_##scope##_##reg##___##field##___lsb ) 18 #define REG_FIELD_X_( value, shift ) ((value) << shift) 19 #endif 20 21 #ifndef REG_STATE 22 #define REG_STATE( scope, reg, field, symbolic_value ) \ 23 REG_STATE_X_( regk_##scope##_##symbolic_value, reg_##scope##_##reg##___##field##___lsb ) 24 #define REG_STATE_X_( k, shift ) (k << shift) 25 #endif 26 27 #ifndef REG_MASK 28 #define REG_MASK( scope, reg, field ) \ 29 REG_MASK_X_( reg_##scope##_##reg##___##field##___width, reg_##scope##_##reg##___##field##___lsb ) 30 #define REG_MASK_X_( width, lsb ) (((1 << width)-1) << lsb) 31 #endif 32 33 #ifndef REG_LSB 34 #define REG_LSB( scope, reg, field ) reg_##scope##_##reg##___##field##___lsb 35 #endif 36 37 #ifndef REG_BIT 38 #define REG_BIT( scope, reg, field ) reg_##scope##_##reg##___##field##___bit 39 #endif 40 41 #ifndef REG_ADDR 42 #define REG_ADDR( scope, inst, reg ) REG_ADDR_X_(inst, reg_##scope##_##reg##_offset) 43 #define REG_ADDR_X_( inst, offs ) ((inst) + offs) 44 #endif 45 46 #ifndef REG_ADDR_VECT 47 #define REG_ADDR_VECT( scope, inst, reg, index ) \ 48 REG_ADDR_VECT_X_(inst, reg_##scope##_##reg##_offset, index, \ 49 STRIDE_##scope##_##reg ) 50 #define REG_ADDR_VECT_X_( inst, offs, index, stride ) \ 51 ((inst) + offs + (index) * stride) 52 #endif 53 54 /* Register r_pa_din, scope gio, type r */ 55 #define reg_gio_r_pa_din___data___lsb 0 56 #define reg_gio_r_pa_din___data___width 32 57 #define reg_gio_r_pa_din_offset 0 58 59 /* Register rw_pa_dout, scope gio, type rw */ 60 #define reg_gio_rw_pa_dout___data___lsb 0 61 #define reg_gio_rw_pa_dout___data___width 32 62 #define reg_gio_rw_pa_dout_offset 4 63 64 /* Register rw_pa_oe, scope gio, type rw */ 65 #define reg_gio_rw_pa_oe___oe___lsb 0 66 #define reg_gio_rw_pa_oe___oe___width 32 67 #define reg_gio_rw_pa_oe_offset 8 68 69 /* Register rw_pa_byte0_dout, scope gio, type rw */ 70 #define reg_gio_rw_pa_byte0_dout___data___lsb 0 71 #define reg_gio_rw_pa_byte0_dout___data___width 8 72 #define reg_gio_rw_pa_byte0_dout_offset 12 73 74 /* Register rw_pa_byte0_oe, scope gio, type rw */ 75 #define reg_gio_rw_pa_byte0_oe___oe___lsb 0 76 #define reg_gio_rw_pa_byte0_oe___oe___width 8 77 #define reg_gio_rw_pa_byte0_oe_offset 16 78 79 /* Register rw_pa_byte1_dout, scope gio, type rw */ 80 #define reg_gio_rw_pa_byte1_dout___data___lsb 0 81 #define reg_gio_rw_pa_byte1_dout___data___width 8 82 #define reg_gio_rw_pa_byte1_dout_offset 20 83 84 /* Register rw_pa_byte1_oe, scope gio, type rw */ 85 #define reg_gio_rw_pa_byte1_oe___oe___lsb 0 86 #define reg_gio_rw_pa_byte1_oe___oe___width 8 87 #define reg_gio_rw_pa_byte1_oe_offset 24 88 89 /* Register rw_pa_byte2_dout, scope gio, type rw */ 90 #define reg_gio_rw_pa_byte2_dout___data___lsb 0 91 #define reg_gio_rw_pa_byte2_dout___data___width 8 92 #define reg_gio_rw_pa_byte2_dout_offset 28 93 94 /* Register rw_pa_byte2_oe, scope gio, type rw */ 95 #define reg_gio_rw_pa_byte2_oe___oe___lsb 0 96 #define reg_gio_rw_pa_byte2_oe___oe___width 8 97 #define reg_gio_rw_pa_byte2_oe_offset 32 98 99 /* Register rw_pa_byte3_dout, scope gio, type rw */ 100 #define reg_gio_rw_pa_byte3_dout___data___lsb 0 101 #define reg_gio_rw_pa_byte3_dout___data___width 8 102 #define reg_gio_rw_pa_byte3_dout_offset 36 103 104 /* Register rw_pa_byte3_oe, scope gio, type rw */ 105 #define reg_gio_rw_pa_byte3_oe___oe___lsb 0 106 #define reg_gio_rw_pa_byte3_oe___oe___width 8 107 #define reg_gio_rw_pa_byte3_oe_offset 40 108 109 /* Register r_pb_din, scope gio, type r */ 110 #define reg_gio_r_pb_din___data___lsb 0 111 #define reg_gio_r_pb_din___data___width 32 112 #define reg_gio_r_pb_din_offset 44 113 114 /* Register rw_pb_dout, scope gio, type rw */ 115 #define reg_gio_rw_pb_dout___data___lsb 0 116 #define reg_gio_rw_pb_dout___data___width 32 117 #define reg_gio_rw_pb_dout_offset 48 118 119 /* Register rw_pb_oe, scope gio, type rw */ 120 #define reg_gio_rw_pb_oe___oe___lsb 0 121 #define reg_gio_rw_pb_oe___oe___width 32 122 #define reg_gio_rw_pb_oe_offset 52 123 124 /* Register rw_pb_byte0_dout, scope gio, type rw */ 125 #define reg_gio_rw_pb_byte0_dout___data___lsb 0 126 #define reg_gio_rw_pb_byte0_dout___data___width 8 127 #define reg_gio_rw_pb_byte0_dout_offset 56 128 129 /* Register rw_pb_byte0_oe, scope gio, type rw */ 130 #define reg_gio_rw_pb_byte0_oe___oe___lsb 0 131 #define reg_gio_rw_pb_byte0_oe___oe___width 8 132 #define reg_gio_rw_pb_byte0_oe_offset 60 133 134 /* Register rw_pb_byte1_dout, scope gio, type rw */ 135 #define reg_gio_rw_pb_byte1_dout___data___lsb 0 136 #define reg_gio_rw_pb_byte1_dout___data___width 8 137 #define reg_gio_rw_pb_byte1_dout_offset 64 138 139 /* Register rw_pb_byte1_oe, scope gio, type rw */ 140 #define reg_gio_rw_pb_byte1_oe___oe___lsb 0 141 #define reg_gio_rw_pb_byte1_oe___oe___width 8 142 #define reg_gio_rw_pb_byte1_oe_offset 68 143 144 /* Register rw_pb_byte2_dout, scope gio, type rw */ 145 #define reg_gio_rw_pb_byte2_dout___data___lsb 0 146 #define reg_gio_rw_pb_byte2_dout___data___width 8 147 #define reg_gio_rw_pb_byte2_dout_offset 72 148 149 /* Register rw_pb_byte2_oe, scope gio, type rw */ 150 #define reg_gio_rw_pb_byte2_oe___oe___lsb 0 151 #define reg_gio_rw_pb_byte2_oe___oe___width 8 152 #define reg_gio_rw_pb_byte2_oe_offset 76 153 154 /* Register rw_pb_byte3_dout, scope gio, type rw */ 155 #define reg_gio_rw_pb_byte3_dout___data___lsb 0 156 #define reg_gio_rw_pb_byte3_dout___data___width 8 157 #define reg_gio_rw_pb_byte3_dout_offset 80 158 159 /* Register rw_pb_byte3_oe, scope gio, type rw */ 160 #define reg_gio_rw_pb_byte3_oe___oe___lsb 0 161 #define reg_gio_rw_pb_byte3_oe___oe___width 8 162 #define reg_gio_rw_pb_byte3_oe_offset 84 163 164 /* Register r_pc_din, scope gio, type r */ 165 #define reg_gio_r_pc_din___data___lsb 0 166 #define reg_gio_r_pc_din___data___width 16 167 #define reg_gio_r_pc_din_offset 88 168 169 /* Register rw_pc_dout, scope gio, type rw */ 170 #define reg_gio_rw_pc_dout___data___lsb 0 171 #define reg_gio_rw_pc_dout___data___width 16 172 #define reg_gio_rw_pc_dout_offset 92 173 174 /* Register rw_pc_oe, scope gio, type rw */ 175 #define reg_gio_rw_pc_oe___oe___lsb 0 176 #define reg_gio_rw_pc_oe___oe___width 16 177 #define reg_gio_rw_pc_oe_offset 96 178 179 /* Register rw_pc_byte0_dout, scope gio, type rw */ 180 #define reg_gio_rw_pc_byte0_dout___data___lsb 0 181 #define reg_gio_rw_pc_byte0_dout___data___width 8 182 #define reg_gio_rw_pc_byte0_dout_offset 100 183 184 /* Register rw_pc_byte0_oe, scope gio, type rw */ 185 #define reg_gio_rw_pc_byte0_oe___oe___lsb 0 186 #define reg_gio_rw_pc_byte0_oe___oe___width 8 187 #define reg_gio_rw_pc_byte0_oe_offset 104 188 189 /* Register rw_pc_byte1_dout, scope gio, type rw */ 190 #define reg_gio_rw_pc_byte1_dout___data___lsb 0 191 #define reg_gio_rw_pc_byte1_dout___data___width 8 192 #define reg_gio_rw_pc_byte1_dout_offset 108 193 194 /* Register rw_pc_byte1_oe, scope gio, type rw */ 195 #define reg_gio_rw_pc_byte1_oe___oe___lsb 0 196 #define reg_gio_rw_pc_byte1_oe___oe___width 8 197 #define reg_gio_rw_pc_byte1_oe_offset 112 198 199 /* Register r_pd_din, scope gio, type r */ 200 #define reg_gio_r_pd_din___data___lsb 0 201 #define reg_gio_r_pd_din___data___width 32 202 #define reg_gio_r_pd_din_offset 116 203 204 /* Register rw_intr_cfg, scope gio, type rw */ 205 #define reg_gio_rw_intr_cfg___intr0___lsb 0 206 #define reg_gio_rw_intr_cfg___intr0___width 3 207 #define reg_gio_rw_intr_cfg___intr1___lsb 3 208 #define reg_gio_rw_intr_cfg___intr1___width 3 209 #define reg_gio_rw_intr_cfg___intr2___lsb 6 210 #define reg_gio_rw_intr_cfg___intr2___width 3 211 #define reg_gio_rw_intr_cfg___intr3___lsb 9 212 #define reg_gio_rw_intr_cfg___intr3___width 3 213 #define reg_gio_rw_intr_cfg___intr4___lsb 12 214 #define reg_gio_rw_intr_cfg___intr4___width 3 215 #define reg_gio_rw_intr_cfg___intr5___lsb 15 216 #define reg_gio_rw_intr_cfg___intr5___width 3 217 #define reg_gio_rw_intr_cfg___intr6___lsb 18 218 #define reg_gio_rw_intr_cfg___intr6___width 3 219 #define reg_gio_rw_intr_cfg___intr7___lsb 21 220 #define reg_gio_rw_intr_cfg___intr7___width 3 221 #define reg_gio_rw_intr_cfg_offset 120 222 223 /* Register rw_intr_pins, scope gio, type rw */ 224 #define reg_gio_rw_intr_pins___intr0___lsb 0 225 #define reg_gio_rw_intr_pins___intr0___width 4 226 #define reg_gio_rw_intr_pins___intr1___lsb 4 227 #define reg_gio_rw_intr_pins___intr1___width 4 228 #define reg_gio_rw_intr_pins___intr2___lsb 8 229 #define reg_gio_rw_intr_pins___intr2___width 4 230 #define reg_gio_rw_intr_pins___intr3___lsb 12 231 #define reg_gio_rw_intr_pins___intr3___width 4 232 #define reg_gio_rw_intr_pins___intr4___lsb 16 233 #define reg_gio_rw_intr_pins___intr4___width 4 234 #define reg_gio_rw_intr_pins___intr5___lsb 20 235 #define reg_gio_rw_intr_pins___intr5___width 4 236 #define reg_gio_rw_intr_pins___intr6___lsb 24 237 #define reg_gio_rw_intr_pins___intr6___width 4 238 #define reg_gio_rw_intr_pins___intr7___lsb 28 239 #define reg_gio_rw_intr_pins___intr7___width 4 240 #define reg_gio_rw_intr_pins_offset 124 241 242 /* Register rw_intr_mask, scope gio, type rw */ 243 #define reg_gio_rw_intr_mask___intr0___lsb 0 244 #define reg_gio_rw_intr_mask___intr0___width 1 245 #define reg_gio_rw_intr_mask___intr0___bit 0 246 #define reg_gio_rw_intr_mask___intr1___lsb 1 247 #define reg_gio_rw_intr_mask___intr1___width 1 248 #define reg_gio_rw_intr_mask___intr1___bit 1 249 #define reg_gio_rw_intr_mask___intr2___lsb 2 250 #define reg_gio_rw_intr_mask___intr2___width 1 251 #define reg_gio_rw_intr_mask___intr2___bit 2 252 #define reg_gio_rw_intr_mask___intr3___lsb 3 253 #define reg_gio_rw_intr_mask___intr3___width 1 254 #define reg_gio_rw_intr_mask___intr3___bit 3 255 #define reg_gio_rw_intr_mask___intr4___lsb 4 256 #define reg_gio_rw_intr_mask___intr4___width 1 257 #define reg_gio_rw_intr_mask___intr4___bit 4 258 #define reg_gio_rw_intr_mask___intr5___lsb 5 259 #define reg_gio_rw_intr_mask___intr5___width 1 260 #define reg_gio_rw_intr_mask___intr5___bit 5 261 #define reg_gio_rw_intr_mask___intr6___lsb 6 262 #define reg_gio_rw_intr_mask___intr6___width 1 263 #define reg_gio_rw_intr_mask___intr6___bit 6 264 #define reg_gio_rw_intr_mask___intr7___lsb 7 265 #define reg_gio_rw_intr_mask___intr7___width 1 266 #define reg_gio_rw_intr_mask___intr7___bit 7 267 #define reg_gio_rw_intr_mask___i2c0_done___lsb 8 268 #define reg_gio_rw_intr_mask___i2c0_done___width 1 269 #define reg_gio_rw_intr_mask___i2c0_done___bit 8 270 #define reg_gio_rw_intr_mask___i2c1_done___lsb 9 271 #define reg_gio_rw_intr_mask___i2c1_done___width 1 272 #define reg_gio_rw_intr_mask___i2c1_done___bit 9 273 #define reg_gio_rw_intr_mask_offset 128 274 275 /* Register rw_ack_intr, scope gio, type rw */ 276 #define reg_gio_rw_ack_intr___intr0___lsb 0 277 #define reg_gio_rw_ack_intr___intr0___width 1 278 #define reg_gio_rw_ack_intr___intr0___bit 0 279 #define reg_gio_rw_ack_intr___intr1___lsb 1 280 #define reg_gio_rw_ack_intr___intr1___width 1 281 #define reg_gio_rw_ack_intr___intr1___bit 1 282 #define reg_gio_rw_ack_intr___intr2___lsb 2 283 #define reg_gio_rw_ack_intr___intr2___width 1 284 #define reg_gio_rw_ack_intr___intr2___bit 2 285 #define reg_gio_rw_ack_intr___intr3___lsb 3 286 #define reg_gio_rw_ack_intr___intr3___width 1 287 #define reg_gio_rw_ack_intr___intr3___bit 3 288 #define reg_gio_rw_ack_intr___intr4___lsb 4 289 #define reg_gio_rw_ack_intr___intr4___width 1 290 #define reg_gio_rw_ack_intr___intr4___bit 4 291 #define reg_gio_rw_ack_intr___intr5___lsb 5 292 #define reg_gio_rw_ack_intr___intr5___width 1 293 #define reg_gio_rw_ack_intr___intr5___bit 5 294 #define reg_gio_rw_ack_intr___intr6___lsb 6 295 #define reg_gio_rw_ack_intr___intr6___width 1 296 #define reg_gio_rw_ack_intr___intr6___bit 6 297 #define reg_gio_rw_ack_intr___intr7___lsb 7 298 #define reg_gio_rw_ack_intr___intr7___width 1 299 #define reg_gio_rw_ack_intr___intr7___bit 7 300 #define reg_gio_rw_ack_intr___i2c0_done___lsb 8 301 #define reg_gio_rw_ack_intr___i2c0_done___width 1 302 #define reg_gio_rw_ack_intr___i2c0_done___bit 8 303 #define reg_gio_rw_ack_intr___i2c1_done___lsb 9 304 #define reg_gio_rw_ack_intr___i2c1_done___width 1 305 #define reg_gio_rw_ack_intr___i2c1_done___bit 9 306 #define reg_gio_rw_ack_intr_offset 132 307 308 /* Register r_intr, scope gio, type r */ 309 #define reg_gio_r_intr___intr0___lsb 0 310 #define reg_gio_r_intr___intr0___width 1 311 #define reg_gio_r_intr___intr0___bit 0 312 #define reg_gio_r_intr___intr1___lsb 1 313 #define reg_gio_r_intr___intr1___width 1 314 #define reg_gio_r_intr___intr1___bit 1 315 #define reg_gio_r_intr___intr2___lsb 2 316 #define reg_gio_r_intr___intr2___width 1 317 #define reg_gio_r_intr___intr2___bit 2 318 #define reg_gio_r_intr___intr3___lsb 3 319 #define reg_gio_r_intr___intr3___width 1 320 #define reg_gio_r_intr___intr3___bit 3 321 #define reg_gio_r_intr___intr4___lsb 4 322 #define reg_gio_r_intr___intr4___width 1 323 #define reg_gio_r_intr___intr4___bit 4 324 #define reg_gio_r_intr___intr5___lsb 5 325 #define reg_gio_r_intr___intr5___width 1 326 #define reg_gio_r_intr___intr5___bit 5 327 #define reg_gio_r_intr___intr6___lsb 6 328 #define reg_gio_r_intr___intr6___width 1 329 #define reg_gio_r_intr___intr6___bit 6 330 #define reg_gio_r_intr___intr7___lsb 7 331 #define reg_gio_r_intr___intr7___width 1 332 #define reg_gio_r_intr___intr7___bit 7 333 #define reg_gio_r_intr___i2c0_done___lsb 8 334 #define reg_gio_r_intr___i2c0_done___width 1 335 #define reg_gio_r_intr___i2c0_done___bit 8 336 #define reg_gio_r_intr___i2c1_done___lsb 9 337 #define reg_gio_r_intr___i2c1_done___width 1 338 #define reg_gio_r_intr___i2c1_done___bit 9 339 #define reg_gio_r_intr_offset 136 340 341 /* Register r_masked_intr, scope gio, type r */ 342 #define reg_gio_r_masked_intr___intr0___lsb 0 343 #define reg_gio_r_masked_intr___intr0___width 1 344 #define reg_gio_r_masked_intr___intr0___bit 0 345 #define reg_gio_r_masked_intr___intr1___lsb 1 346 #define reg_gio_r_masked_intr___intr1___width 1 347 #define reg_gio_r_masked_intr___intr1___bit 1 348 #define reg_gio_r_masked_intr___intr2___lsb 2 349 #define reg_gio_r_masked_intr___intr2___width 1 350 #define reg_gio_r_masked_intr___intr2___bit 2 351 #define reg_gio_r_masked_intr___intr3___lsb 3 352 #define reg_gio_r_masked_intr___intr3___width 1 353 #define reg_gio_r_masked_intr___intr3___bit 3 354 #define reg_gio_r_masked_intr___intr4___lsb 4 355 #define reg_gio_r_masked_intr___intr4___width 1 356 #define reg_gio_r_masked_intr___intr4___bit 4 357 #define reg_gio_r_masked_intr___intr5___lsb 5 358 #define reg_gio_r_masked_intr___intr5___width 1 359 #define reg_gio_r_masked_intr___intr5___bit 5 360 #define reg_gio_r_masked_intr___intr6___lsb 6 361 #define reg_gio_r_masked_intr___intr6___width 1 362 #define reg_gio_r_masked_intr___intr6___bit 6 363 #define reg_gio_r_masked_intr___intr7___lsb 7 364 #define reg_gio_r_masked_intr___intr7___width 1 365 #define reg_gio_r_masked_intr___intr7___bit 7 366 #define reg_gio_r_masked_intr___i2c0_done___lsb 8 367 #define reg_gio_r_masked_intr___i2c0_done___width 1 368 #define reg_gio_r_masked_intr___i2c0_done___bit 8 369 #define reg_gio_r_masked_intr___i2c1_done___lsb 9 370 #define reg_gio_r_masked_intr___i2c1_done___width 1 371 #define reg_gio_r_masked_intr___i2c1_done___bit 9 372 #define reg_gio_r_masked_intr_offset 140 373 374 /* Register rw_i2c0_start, scope gio, type rw */ 375 #define reg_gio_rw_i2c0_start___run___lsb 0 376 #define reg_gio_rw_i2c0_start___run___width 1 377 #define reg_gio_rw_i2c0_start___run___bit 0 378 #define reg_gio_rw_i2c0_start_offset 144 379 380 /* Register rw_i2c0_cfg, scope gio, type rw */ 381 #define reg_gio_rw_i2c0_cfg___en___lsb 0 382 #define reg_gio_rw_i2c0_cfg___en___width 1 383 #define reg_gio_rw_i2c0_cfg___en___bit 0 384 #define reg_gio_rw_i2c0_cfg___bit_order___lsb 1 385 #define reg_gio_rw_i2c0_cfg___bit_order___width 1 386 #define reg_gio_rw_i2c0_cfg___bit_order___bit 1 387 #define reg_gio_rw_i2c0_cfg___scl_io___lsb 2 388 #define reg_gio_rw_i2c0_cfg___scl_io___width 1 389 #define reg_gio_rw_i2c0_cfg___scl_io___bit 2 390 #define reg_gio_rw_i2c0_cfg___scl_inv___lsb 3 391 #define reg_gio_rw_i2c0_cfg___scl_inv___width 1 392 #define reg_gio_rw_i2c0_cfg___scl_inv___bit 3 393 #define reg_gio_rw_i2c0_cfg___sda_io___lsb 4 394 #define reg_gio_rw_i2c0_cfg___sda_io___width 1 395 #define reg_gio_rw_i2c0_cfg___sda_io___bit 4 396 #define reg_gio_rw_i2c0_cfg___sda_idle___lsb 5 397 #define reg_gio_rw_i2c0_cfg___sda_idle___width 1 398 #define reg_gio_rw_i2c0_cfg___sda_idle___bit 5 399 #define reg_gio_rw_i2c0_cfg_offset 148 400 401 /* Register rw_i2c0_ctrl, scope gio, type rw */ 402 #define reg_gio_rw_i2c0_ctrl___trf_bits___lsb 0 403 #define reg_gio_rw_i2c0_ctrl___trf_bits___width 6 404 #define reg_gio_rw_i2c0_ctrl___switch_dir___lsb 6 405 #define reg_gio_rw_i2c0_ctrl___switch_dir___width 6 406 #define reg_gio_rw_i2c0_ctrl___extra_start___lsb 12 407 #define reg_gio_rw_i2c0_ctrl___extra_start___width 3 408 #define reg_gio_rw_i2c0_ctrl___early_end___lsb 15 409 #define reg_gio_rw_i2c0_ctrl___early_end___width 1 410 #define reg_gio_rw_i2c0_ctrl___early_end___bit 15 411 #define reg_gio_rw_i2c0_ctrl___start_stop___lsb 16 412 #define reg_gio_rw_i2c0_ctrl___start_stop___width 1 413 #define reg_gio_rw_i2c0_ctrl___start_stop___bit 16 414 #define reg_gio_rw_i2c0_ctrl___ack_dir0___lsb 17 415 #define reg_gio_rw_i2c0_ctrl___ack_dir0___width 1 416 #define reg_gio_rw_i2c0_ctrl___ack_dir0___bit 17 417 #define reg_gio_rw_i2c0_ctrl___ack_dir1___lsb 18 418 #define reg_gio_rw_i2c0_ctrl___ack_dir1___width 1 419 #define reg_gio_rw_i2c0_ctrl___ack_dir1___bit 18 420 #define reg_gio_rw_i2c0_ctrl___ack_dir2___lsb 19 421 #define reg_gio_rw_i2c0_ctrl___ack_dir2___width 1 422 #define reg_gio_rw_i2c0_ctrl___ack_dir2___bit 19 423 #define reg_gio_rw_i2c0_ctrl___ack_dir3___lsb 20 424 #define reg_gio_rw_i2c0_ctrl___ack_dir3___width 1 425 #define reg_gio_rw_i2c0_ctrl___ack_dir3___bit 20 426 #define reg_gio_rw_i2c0_ctrl___ack_dir4___lsb 21 427 #define reg_gio_rw_i2c0_ctrl___ack_dir4___width 1 428 #define reg_gio_rw_i2c0_ctrl___ack_dir4___bit 21 429 #define reg_gio_rw_i2c0_ctrl___ack_dir5___lsb 22 430 #define reg_gio_rw_i2c0_ctrl___ack_dir5___width 1 431 #define reg_gio_rw_i2c0_ctrl___ack_dir5___bit 22 432 #define reg_gio_rw_i2c0_ctrl___ack_bit___lsb 23 433 #define reg_gio_rw_i2c0_ctrl___ack_bit___width 1 434 #define reg_gio_rw_i2c0_ctrl___ack_bit___bit 23 435 #define reg_gio_rw_i2c0_ctrl___start_bit___lsb 24 436 #define reg_gio_rw_i2c0_ctrl___start_bit___width 1 437 #define reg_gio_rw_i2c0_ctrl___start_bit___bit 24 438 #define reg_gio_rw_i2c0_ctrl___freq___lsb 25 439 #define reg_gio_rw_i2c0_ctrl___freq___width 2 440 #define reg_gio_rw_i2c0_ctrl_offset 152 441 442 /* Register rw_i2c0_data, scope gio, type rw */ 443 #define reg_gio_rw_i2c0_data___data0___lsb 0 444 #define reg_gio_rw_i2c0_data___data0___width 8 445 #define reg_gio_rw_i2c0_data___data1___lsb 8 446 #define reg_gio_rw_i2c0_data___data1___width 8 447 #define reg_gio_rw_i2c0_data___data2___lsb 16 448 #define reg_gio_rw_i2c0_data___data2___width 8 449 #define reg_gio_rw_i2c0_data___data3___lsb 24 450 #define reg_gio_rw_i2c0_data___data3___width 8 451 #define reg_gio_rw_i2c0_data_offset 156 452 453 /* Register rw_i2c0_data2, scope gio, type rw */ 454 #define reg_gio_rw_i2c0_data2___data4___lsb 0 455 #define reg_gio_rw_i2c0_data2___data4___width 8 456 #define reg_gio_rw_i2c0_data2___data5___lsb 8 457 #define reg_gio_rw_i2c0_data2___data5___width 8 458 #define reg_gio_rw_i2c0_data2___start_val___lsb 16 459 #define reg_gio_rw_i2c0_data2___start_val___width 6 460 #define reg_gio_rw_i2c0_data2___ack_val___lsb 22 461 #define reg_gio_rw_i2c0_data2___ack_val___width 6 462 #define reg_gio_rw_i2c0_data2_offset 160 463 464 /* Register rw_i2c1_start, scope gio, type rw */ 465 #define reg_gio_rw_i2c1_start___run___lsb 0 466 #define reg_gio_rw_i2c1_start___run___width 1 467 #define reg_gio_rw_i2c1_start___run___bit 0 468 #define reg_gio_rw_i2c1_start_offset 164 469 470 /* Register rw_i2c1_cfg, scope gio, type rw */ 471 #define reg_gio_rw_i2c1_cfg___en___lsb 0 472 #define reg_gio_rw_i2c1_cfg___en___width 1 473 #define reg_gio_rw_i2c1_cfg___en___bit 0 474 #define reg_gio_rw_i2c1_cfg___bit_order___lsb 1 475 #define reg_gio_rw_i2c1_cfg___bit_order___width 1 476 #define reg_gio_rw_i2c1_cfg___bit_order___bit 1 477 #define reg_gio_rw_i2c1_cfg___scl_io___lsb 2 478 #define reg_gio_rw_i2c1_cfg___scl_io___width 1 479 #define reg_gio_rw_i2c1_cfg___scl_io___bit 2 480 #define reg_gio_rw_i2c1_cfg___scl_inv___lsb 3 481 #define reg_gio_rw_i2c1_cfg___scl_inv___width 1 482 #define reg_gio_rw_i2c1_cfg___scl_inv___bit 3 483 #define reg_gio_rw_i2c1_cfg___sda0_io___lsb 4 484 #define reg_gio_rw_i2c1_cfg___sda0_io___width 1 485 #define reg_gio_rw_i2c1_cfg___sda0_io___bit 4 486 #define reg_gio_rw_i2c1_cfg___sda0_idle___lsb 5 487 #define reg_gio_rw_i2c1_cfg___sda0_idle___width 1 488 #define reg_gio_rw_i2c1_cfg___sda0_idle___bit 5 489 #define reg_gio_rw_i2c1_cfg___sda1_io___lsb 6 490 #define reg_gio_rw_i2c1_cfg___sda1_io___width 1 491 #define reg_gio_rw_i2c1_cfg___sda1_io___bit 6 492 #define reg_gio_rw_i2c1_cfg___sda1_idle___lsb 7 493 #define reg_gio_rw_i2c1_cfg___sda1_idle___width 1 494 #define reg_gio_rw_i2c1_cfg___sda1_idle___bit 7 495 #define reg_gio_rw_i2c1_cfg___sda2_io___lsb 8 496 #define reg_gio_rw_i2c1_cfg___sda2_io___width 1 497 #define reg_gio_rw_i2c1_cfg___sda2_io___bit 8 498 #define reg_gio_rw_i2c1_cfg___sda2_idle___lsb 9 499 #define reg_gio_rw_i2c1_cfg___sda2_idle___width 1 500 #define reg_gio_rw_i2c1_cfg___sda2_idle___bit 9 501 #define reg_gio_rw_i2c1_cfg___sda3_io___lsb 10 502 #define reg_gio_rw_i2c1_cfg___sda3_io___width 1 503 #define reg_gio_rw_i2c1_cfg___sda3_io___bit 10 504 #define reg_gio_rw_i2c1_cfg___sda3_idle___lsb 11 505 #define reg_gio_rw_i2c1_cfg___sda3_idle___width 1 506 #define reg_gio_rw_i2c1_cfg___sda3_idle___bit 11 507 #define reg_gio_rw_i2c1_cfg___sda_sel___lsb 12 508 #define reg_gio_rw_i2c1_cfg___sda_sel___width 2 509 #define reg_gio_rw_i2c1_cfg___sen_idle___lsb 14 510 #define reg_gio_rw_i2c1_cfg___sen_idle___width 1 511 #define reg_gio_rw_i2c1_cfg___sen_idle___bit 14 512 #define reg_gio_rw_i2c1_cfg___sen_inv___lsb 15 513 #define reg_gio_rw_i2c1_cfg___sen_inv___width 1 514 #define reg_gio_rw_i2c1_cfg___sen_inv___bit 15 515 #define reg_gio_rw_i2c1_cfg___sen_sel___lsb 16 516 #define reg_gio_rw_i2c1_cfg___sen_sel___width 2 517 #define reg_gio_rw_i2c1_cfg_offset 168 518 519 /* Register rw_i2c1_ctrl, scope gio, type rw */ 520 #define reg_gio_rw_i2c1_ctrl___trf_bits___lsb 0 521 #define reg_gio_rw_i2c1_ctrl___trf_bits___width 6 522 #define reg_gio_rw_i2c1_ctrl___switch_dir___lsb 6 523 #define reg_gio_rw_i2c1_ctrl___switch_dir___width 6 524 #define reg_gio_rw_i2c1_ctrl___extra_start___lsb 12 525 #define reg_gio_rw_i2c1_ctrl___extra_start___width 3 526 #define reg_gio_rw_i2c1_ctrl___early_end___lsb 15 527 #define reg_gio_rw_i2c1_ctrl___early_end___width 1 528 #define reg_gio_rw_i2c1_ctrl___early_end___bit 15 529 #define reg_gio_rw_i2c1_ctrl___start_stop___lsb 16 530 #define reg_gio_rw_i2c1_ctrl___start_stop___width 1 531 #define reg_gio_rw_i2c1_ctrl___start_stop___bit 16 532 #define reg_gio_rw_i2c1_ctrl___ack_dir0___lsb 17 533 #define reg_gio_rw_i2c1_ctrl___ack_dir0___width 1 534 #define reg_gio_rw_i2c1_ctrl___ack_dir0___bit 17 535 #define reg_gio_rw_i2c1_ctrl___ack_dir1___lsb 18 536 #define reg_gio_rw_i2c1_ctrl___ack_dir1___width 1 537 #define reg_gio_rw_i2c1_ctrl___ack_dir1___bit 18 538 #define reg_gio_rw_i2c1_ctrl___ack_dir2___lsb 19 539 #define reg_gio_rw_i2c1_ctrl___ack_dir2___width 1 540 #define reg_gio_rw_i2c1_ctrl___ack_dir2___bit 19 541 #define reg_gio_rw_i2c1_ctrl___ack_dir3___lsb 20 542 #define reg_gio_rw_i2c1_ctrl___ack_dir3___width 1 543 #define reg_gio_rw_i2c1_ctrl___ack_dir3___bit 20 544 #define reg_gio_rw_i2c1_ctrl___ack_dir4___lsb 21 545 #define reg_gio_rw_i2c1_ctrl___ack_dir4___width 1 546 #define reg_gio_rw_i2c1_ctrl___ack_dir4___bit 21 547 #define reg_gio_rw_i2c1_ctrl___ack_dir5___lsb 22 548 #define reg_gio_rw_i2c1_ctrl___ack_dir5___width 1 549 #define reg_gio_rw_i2c1_ctrl___ack_dir5___bit 22 550 #define reg_gio_rw_i2c1_ctrl___ack_bit___lsb 23 551 #define reg_gio_rw_i2c1_ctrl___ack_bit___width 1 552 #define reg_gio_rw_i2c1_ctrl___ack_bit___bit 23 553 #define reg_gio_rw_i2c1_ctrl___start_bit___lsb 24 554 #define reg_gio_rw_i2c1_ctrl___start_bit___width 1 555 #define reg_gio_rw_i2c1_ctrl___start_bit___bit 24 556 #define reg_gio_rw_i2c1_ctrl___freq___lsb 25 557 #define reg_gio_rw_i2c1_ctrl___freq___width 2 558 #define reg_gio_rw_i2c1_ctrl_offset 172 559 560 /* Register rw_i2c1_data, scope gio, type rw */ 561 #define reg_gio_rw_i2c1_data___data0___lsb 0 562 #define reg_gio_rw_i2c1_data___data0___width 8 563 #define reg_gio_rw_i2c1_data___data1___lsb 8 564 #define reg_gio_rw_i2c1_data___data1___width 8 565 #define reg_gio_rw_i2c1_data___data2___lsb 16 566 #define reg_gio_rw_i2c1_data___data2___width 8 567 #define reg_gio_rw_i2c1_data___data3___lsb 24 568 #define reg_gio_rw_i2c1_data___data3___width 8 569 #define reg_gio_rw_i2c1_data_offset 176 570 571 /* Register rw_i2c1_data2, scope gio, type rw */ 572 #define reg_gio_rw_i2c1_data2___data4___lsb 0 573 #define reg_gio_rw_i2c1_data2___data4___width 8 574 #define reg_gio_rw_i2c1_data2___data5___lsb 8 575 #define reg_gio_rw_i2c1_data2___data5___width 8 576 #define reg_gio_rw_i2c1_data2___start_val___lsb 16 577 #define reg_gio_rw_i2c1_data2___start_val___width 6 578 #define reg_gio_rw_i2c1_data2___ack_val___lsb 22 579 #define reg_gio_rw_i2c1_data2___ack_val___width 6 580 #define reg_gio_rw_i2c1_data2_offset 180 581 582 /* Register r_ppwm_stat, scope gio, type r */ 583 #define reg_gio_r_ppwm_stat___freq___lsb 0 584 #define reg_gio_r_ppwm_stat___freq___width 2 585 #define reg_gio_r_ppwm_stat_offset 184 586 587 /* Register rw_ppwm_data, scope gio, type rw */ 588 #define reg_gio_rw_ppwm_data___data___lsb 0 589 #define reg_gio_rw_ppwm_data___data___width 8 590 #define reg_gio_rw_ppwm_data_offset 188 591 592 /* Register rw_pwm0_ctrl, scope gio, type rw */ 593 #define reg_gio_rw_pwm0_ctrl___mode___lsb 0 594 #define reg_gio_rw_pwm0_ctrl___mode___width 2 595 #define reg_gio_rw_pwm0_ctrl___ccd_override___lsb 2 596 #define reg_gio_rw_pwm0_ctrl___ccd_override___width 1 597 #define reg_gio_rw_pwm0_ctrl___ccd_override___bit 2 598 #define reg_gio_rw_pwm0_ctrl___ccd_val___lsb 3 599 #define reg_gio_rw_pwm0_ctrl___ccd_val___width 1 600 #define reg_gio_rw_pwm0_ctrl___ccd_val___bit 3 601 #define reg_gio_rw_pwm0_ctrl_offset 192 602 603 /* Register rw_pwm0_var, scope gio, type rw */ 604 #define reg_gio_rw_pwm0_var___lo___lsb 0 605 #define reg_gio_rw_pwm0_var___lo___width 13 606 #define reg_gio_rw_pwm0_var___hi___lsb 13 607 #define reg_gio_rw_pwm0_var___hi___width 13 608 #define reg_gio_rw_pwm0_var_offset 196 609 610 /* Register rw_pwm0_data, scope gio, type rw */ 611 #define reg_gio_rw_pwm0_data___data___lsb 0 612 #define reg_gio_rw_pwm0_data___data___width 8 613 #define reg_gio_rw_pwm0_data_offset 200 614 615 /* Register rw_pwm1_ctrl, scope gio, type rw */ 616 #define reg_gio_rw_pwm1_ctrl___mode___lsb 0 617 #define reg_gio_rw_pwm1_ctrl___mode___width 2 618 #define reg_gio_rw_pwm1_ctrl___ccd_override___lsb 2 619 #define reg_gio_rw_pwm1_ctrl___ccd_override___width 1 620 #define reg_gio_rw_pwm1_ctrl___ccd_override___bit 2 621 #define reg_gio_rw_pwm1_ctrl___ccd_val___lsb 3 622 #define reg_gio_rw_pwm1_ctrl___ccd_val___width 1 623 #define reg_gio_rw_pwm1_ctrl___ccd_val___bit 3 624 #define reg_gio_rw_pwm1_ctrl_offset 204 625 626 /* Register rw_pwm1_var, scope gio, type rw */ 627 #define reg_gio_rw_pwm1_var___lo___lsb 0 628 #define reg_gio_rw_pwm1_var___lo___width 13 629 #define reg_gio_rw_pwm1_var___hi___lsb 13 630 #define reg_gio_rw_pwm1_var___hi___width 13 631 #define reg_gio_rw_pwm1_var_offset 208 632 633 /* Register rw_pwm1_data, scope gio, type rw */ 634 #define reg_gio_rw_pwm1_data___data___lsb 0 635 #define reg_gio_rw_pwm1_data___data___width 8 636 #define reg_gio_rw_pwm1_data_offset 212 637 638 /* Register rw_pwm2_ctrl, scope gio, type rw */ 639 #define reg_gio_rw_pwm2_ctrl___mode___lsb 0 640 #define reg_gio_rw_pwm2_ctrl___mode___width 2 641 #define reg_gio_rw_pwm2_ctrl___ccd_override___lsb 2 642 #define reg_gio_rw_pwm2_ctrl___ccd_override___width 1 643 #define reg_gio_rw_pwm2_ctrl___ccd_override___bit 2 644 #define reg_gio_rw_pwm2_ctrl___ccd_val___lsb 3 645 #define reg_gio_rw_pwm2_ctrl___ccd_val___width 1 646 #define reg_gio_rw_pwm2_ctrl___ccd_val___bit 3 647 #define reg_gio_rw_pwm2_ctrl_offset 216 648 649 /* Register rw_pwm2_var, scope gio, type rw */ 650 #define reg_gio_rw_pwm2_var___lo___lsb 0 651 #define reg_gio_rw_pwm2_var___lo___width 13 652 #define reg_gio_rw_pwm2_var___hi___lsb 13 653 #define reg_gio_rw_pwm2_var___hi___width 13 654 #define reg_gio_rw_pwm2_var_offset 220 655 656 /* Register rw_pwm2_data, scope gio, type rw */ 657 #define reg_gio_rw_pwm2_data___data___lsb 0 658 #define reg_gio_rw_pwm2_data___data___width 8 659 #define reg_gio_rw_pwm2_data_offset 224 660 661 /* Register rw_pwm_in_cfg, scope gio, type rw */ 662 #define reg_gio_rw_pwm_in_cfg___pin___lsb 0 663 #define reg_gio_rw_pwm_in_cfg___pin___width 3 664 #define reg_gio_rw_pwm_in_cfg_offset 228 665 666 /* Register r_pwm_in_lo, scope gio, type r */ 667 #define reg_gio_r_pwm_in_lo___data___lsb 0 668 #define reg_gio_r_pwm_in_lo___data___width 32 669 #define reg_gio_r_pwm_in_lo_offset 232 670 671 /* Register r_pwm_in_hi, scope gio, type r */ 672 #define reg_gio_r_pwm_in_hi___data___lsb 0 673 #define reg_gio_r_pwm_in_hi___data___width 32 674 #define reg_gio_r_pwm_in_hi_offset 236 675 676 /* Register r_pwm_in_cnt, scope gio, type r */ 677 #define reg_gio_r_pwm_in_cnt___data___lsb 0 678 #define reg_gio_r_pwm_in_cnt___data___width 32 679 #define reg_gio_r_pwm_in_cnt_offset 240 680 681 682 /* Constants */ 683 #define regk_gio_anyedge 0x00000007 684 #define regk_gio_f100k 0x00000000 685 #define regk_gio_f1562 0x00000000 686 #define regk_gio_f195 0x00000003 687 #define regk_gio_f1m 0x00000002 688 #define regk_gio_f390 0x00000002 689 #define regk_gio_f400k 0x00000001 690 #define regk_gio_f5m 0x00000003 691 #define regk_gio_f781 0x00000001 692 #define regk_gio_hi 0x00000001 693 #define regk_gio_in 0x00000000 694 #define regk_gio_intr_pa0 0x00000000 695 #define regk_gio_intr_pa1 0x00000000 696 #define regk_gio_intr_pa10 0x00000001 697 #define regk_gio_intr_pa11 0x00000001 698 #define regk_gio_intr_pa12 0x00000001 699 #define regk_gio_intr_pa13 0x00000001 700 #define regk_gio_intr_pa14 0x00000001 701 #define regk_gio_intr_pa15 0x00000001 702 #define regk_gio_intr_pa16 0x00000002 703 #define regk_gio_intr_pa17 0x00000002 704 #define regk_gio_intr_pa18 0x00000002 705 #define regk_gio_intr_pa19 0x00000002 706 #define regk_gio_intr_pa2 0x00000000 707 #define regk_gio_intr_pa20 0x00000002 708 #define regk_gio_intr_pa21 0x00000002 709 #define regk_gio_intr_pa22 0x00000002 710 #define regk_gio_intr_pa23 0x00000002 711 #define regk_gio_intr_pa24 0x00000003 712 #define regk_gio_intr_pa25 0x00000003 713 #define regk_gio_intr_pa26 0x00000003 714 #define regk_gio_intr_pa27 0x00000003 715 #define regk_gio_intr_pa28 0x00000003 716 #define regk_gio_intr_pa29 0x00000003 717 #define regk_gio_intr_pa3 0x00000000 718 #define regk_gio_intr_pa30 0x00000003 719 #define regk_gio_intr_pa31 0x00000003 720 #define regk_gio_intr_pa4 0x00000000 721 #define regk_gio_intr_pa5 0x00000000 722 #define regk_gio_intr_pa6 0x00000000 723 #define regk_gio_intr_pa7 0x00000000 724 #define regk_gio_intr_pa8 0x00000001 725 #define regk_gio_intr_pa9 0x00000001 726 #define regk_gio_intr_pb0 0x00000004 727 #define regk_gio_intr_pb1 0x00000004 728 #define regk_gio_intr_pb10 0x00000005 729 #define regk_gio_intr_pb11 0x00000005 730 #define regk_gio_intr_pb12 0x00000005 731 #define regk_gio_intr_pb13 0x00000005 732 #define regk_gio_intr_pb14 0x00000005 733 #define regk_gio_intr_pb15 0x00000005 734 #define regk_gio_intr_pb16 0x00000006 735 #define regk_gio_intr_pb17 0x00000006 736 #define regk_gio_intr_pb18 0x00000006 737 #define regk_gio_intr_pb19 0x00000006 738 #define regk_gio_intr_pb2 0x00000004 739 #define regk_gio_intr_pb20 0x00000006 740 #define regk_gio_intr_pb21 0x00000006 741 #define regk_gio_intr_pb22 0x00000006 742 #define regk_gio_intr_pb23 0x00000006 743 #define regk_gio_intr_pb24 0x00000007 744 #define regk_gio_intr_pb25 0x00000007 745 #define regk_gio_intr_pb26 0x00000007 746 #define regk_gio_intr_pb27 0x00000007 747 #define regk_gio_intr_pb28 0x00000007 748 #define regk_gio_intr_pb29 0x00000007 749 #define regk_gio_intr_pb3 0x00000004 750 #define regk_gio_intr_pb30 0x00000007 751 #define regk_gio_intr_pb31 0x00000007 752 #define regk_gio_intr_pb4 0x00000004 753 #define regk_gio_intr_pb5 0x00000004 754 #define regk_gio_intr_pb6 0x00000004 755 #define regk_gio_intr_pb7 0x00000004 756 #define regk_gio_intr_pb8 0x00000005 757 #define regk_gio_intr_pb9 0x00000005 758 #define regk_gio_intr_pc0 0x00000008 759 #define regk_gio_intr_pc1 0x00000008 760 #define regk_gio_intr_pc10 0x00000009 761 #define regk_gio_intr_pc11 0x00000009 762 #define regk_gio_intr_pc12 0x00000009 763 #define regk_gio_intr_pc13 0x00000009 764 #define regk_gio_intr_pc14 0x00000009 765 #define regk_gio_intr_pc15 0x00000009 766 #define regk_gio_intr_pc2 0x00000008 767 #define regk_gio_intr_pc3 0x00000008 768 #define regk_gio_intr_pc4 0x00000008 769 #define regk_gio_intr_pc5 0x00000008 770 #define regk_gio_intr_pc6 0x00000008 771 #define regk_gio_intr_pc7 0x00000008 772 #define regk_gio_intr_pc8 0x00000009 773 #define regk_gio_intr_pc9 0x00000009 774 #define regk_gio_intr_pd0 0x0000000c 775 #define regk_gio_intr_pd1 0x0000000c 776 #define regk_gio_intr_pd10 0x0000000d 777 #define regk_gio_intr_pd11 0x0000000d 778 #define regk_gio_intr_pd12 0x0000000d 779 #define regk_gio_intr_pd13 0x0000000d 780 #define regk_gio_intr_pd14 0x0000000d 781 #define regk_gio_intr_pd15 0x0000000d 782 #define regk_gio_intr_pd16 0x0000000e 783 #define regk_gio_intr_pd17 0x0000000e 784 #define regk_gio_intr_pd18 0x0000000e 785 #define regk_gio_intr_pd19 0x0000000e 786 #define regk_gio_intr_pd2 0x0000000c 787 #define regk_gio_intr_pd20 0x0000000e 788 #define regk_gio_intr_pd21 0x0000000e 789 #define regk_gio_intr_pd22 0x0000000e 790 #define regk_gio_intr_pd23 0x0000000e 791 #define regk_gio_intr_pd24 0x0000000f 792 #define regk_gio_intr_pd25 0x0000000f 793 #define regk_gio_intr_pd26 0x0000000f 794 #define regk_gio_intr_pd27 0x0000000f 795 #define regk_gio_intr_pd28 0x0000000f 796 #define regk_gio_intr_pd29 0x0000000f 797 #define regk_gio_intr_pd3 0x0000000c 798 #define regk_gio_intr_pd30 0x0000000f 799 #define regk_gio_intr_pd31 0x0000000f 800 #define regk_gio_intr_pd4 0x0000000c 801 #define regk_gio_intr_pd5 0x0000000c 802 #define regk_gio_intr_pd6 0x0000000c 803 #define regk_gio_intr_pd7 0x0000000c 804 #define regk_gio_intr_pd8 0x0000000d 805 #define regk_gio_intr_pd9 0x0000000d 806 #define regk_gio_lo 0x00000002 807 #define regk_gio_lsb 0x00000000 808 #define regk_gio_msb 0x00000001 809 #define regk_gio_negedge 0x00000006 810 #define regk_gio_no 0x00000000 811 #define regk_gio_no_switch 0x0000003f 812 #define regk_gio_none 0x00000007 813 #define regk_gio_off 0x00000000 814 #define regk_gio_opendrain 0x00000000 815 #define regk_gio_out 0x00000001 816 #define regk_gio_posedge 0x00000005 817 #define regk_gio_pwm_hfp 0x00000002 818 #define regk_gio_pwm_pa0 0x00000001 819 #define regk_gio_pwm_pa19 0x00000004 820 #define regk_gio_pwm_pa6 0x00000002 821 #define regk_gio_pwm_pa7 0x00000003 822 #define regk_gio_pwm_pb26 0x00000005 823 #define regk_gio_pwm_pd23 0x00000006 824 #define regk_gio_pwm_pd31 0x00000007 825 #define regk_gio_pwm_std 0x00000001 826 #define regk_gio_pwm_var 0x00000003 827 #define regk_gio_rw_i2c0_cfg_default 0x00000020 828 #define regk_gio_rw_i2c0_ctrl_default 0x00010000 829 #define regk_gio_rw_i2c0_start_default 0x00000000 830 #define regk_gio_rw_i2c1_cfg_default 0x00000aa0 831 #define regk_gio_rw_i2c1_ctrl_default 0x00010000 832 #define regk_gio_rw_i2c1_start_default 0x00000000 833 #define regk_gio_rw_intr_cfg_default 0x00000000 834 #define regk_gio_rw_intr_mask_default 0x00000000 835 #define regk_gio_rw_pa_oe_default 0x00000000 836 #define regk_gio_rw_pb_oe_default 0x00000000 837 #define regk_gio_rw_pc_oe_default 0x00000000 838 #define regk_gio_rw_ppwm_data_default 0x00000000 839 #define regk_gio_rw_pwm0_ctrl_default 0x00000000 840 #define regk_gio_rw_pwm1_ctrl_default 0x00000000 841 #define regk_gio_rw_pwm2_ctrl_default 0x00000000 842 #define regk_gio_rw_pwm_in_cfg_default 0x00000000 843 #define regk_gio_sda0 0x00000000 844 #define regk_gio_sda1 0x00000001 845 #define regk_gio_sda2 0x00000002 846 #define regk_gio_sda3 0x00000003 847 #define regk_gio_sen 0x00000000 848 #define regk_gio_set 0x00000003 849 #define regk_gio_yes 0x00000001 850 #endif /* __gio_defs_asm_h */ 851