1 /* SPDX-License-Identifier: GPL-2.0 */ 2 #ifndef __gio_defs_asm_h 3 #define __gio_defs_asm_h 4 5 /* 6 * This file is autogenerated from 7 * file: ../../inst/gio/rtl/gio_regs.r 8 * id: gio_regs.r,v 1.5 2005/02/04 09:43:21 perz Exp 9 * last modfied: Mon Apr 11 16:07:47 2005 10 * 11 * by /n/asic/design/tools/rdesc/src/rdes2c -asm --outfile asm/gio_defs_asm.h ../../inst/gio/rtl/gio_regs.r 12 * id: $Id: gio_defs_asm.h,v 1.1 2007/02/13 11:55:30 starvik Exp $ 13 * Any changes here will be lost. 14 * 15 * -*- buffer-read-only: t -*- 16 */ 17 18 #ifndef REG_FIELD 19 #define REG_FIELD( scope, reg, field, value ) \ 20 REG_FIELD_X_( value, reg_##scope##_##reg##___##field##___lsb ) 21 #define REG_FIELD_X_( value, shift ) ((value) << shift) 22 #endif 23 24 #ifndef REG_STATE 25 #define REG_STATE( scope, reg, field, symbolic_value ) \ 26 REG_STATE_X_( regk_##scope##_##symbolic_value, reg_##scope##_##reg##___##field##___lsb ) 27 #define REG_STATE_X_( k, shift ) (k << shift) 28 #endif 29 30 #ifndef REG_MASK 31 #define REG_MASK( scope, reg, field ) \ 32 REG_MASK_X_( reg_##scope##_##reg##___##field##___width, reg_##scope##_##reg##___##field##___lsb ) 33 #define REG_MASK_X_( width, lsb ) (((1 << width)-1) << lsb) 34 #endif 35 36 #ifndef REG_LSB 37 #define REG_LSB( scope, reg, field ) reg_##scope##_##reg##___##field##___lsb 38 #endif 39 40 #ifndef REG_BIT 41 #define REG_BIT( scope, reg, field ) reg_##scope##_##reg##___##field##___bit 42 #endif 43 44 #ifndef REG_ADDR 45 #define REG_ADDR( scope, inst, reg ) REG_ADDR_X_(inst, reg_##scope##_##reg##_offset) 46 #define REG_ADDR_X_( inst, offs ) ((inst) + offs) 47 #endif 48 49 #ifndef REG_ADDR_VECT 50 #define REG_ADDR_VECT( scope, inst, reg, index ) \ 51 REG_ADDR_VECT_X_(inst, reg_##scope##_##reg##_offset, index, \ 52 STRIDE_##scope##_##reg ) 53 #define REG_ADDR_VECT_X_( inst, offs, index, stride ) \ 54 ((inst) + offs + (index) * stride) 55 #endif 56 57 /* Register rw_pa_dout, scope gio, type rw */ 58 #define reg_gio_rw_pa_dout___data___lsb 0 59 #define reg_gio_rw_pa_dout___data___width 8 60 #define reg_gio_rw_pa_dout_offset 0 61 62 /* Register r_pa_din, scope gio, type r */ 63 #define reg_gio_r_pa_din___data___lsb 0 64 #define reg_gio_r_pa_din___data___width 8 65 #define reg_gio_r_pa_din_offset 4 66 67 /* Register rw_pa_oe, scope gio, type rw */ 68 #define reg_gio_rw_pa_oe___oe___lsb 0 69 #define reg_gio_rw_pa_oe___oe___width 8 70 #define reg_gio_rw_pa_oe_offset 8 71 72 /* Register rw_intr_cfg, scope gio, type rw */ 73 #define reg_gio_rw_intr_cfg___pa0___lsb 0 74 #define reg_gio_rw_intr_cfg___pa0___width 3 75 #define reg_gio_rw_intr_cfg___pa1___lsb 3 76 #define reg_gio_rw_intr_cfg___pa1___width 3 77 #define reg_gio_rw_intr_cfg___pa2___lsb 6 78 #define reg_gio_rw_intr_cfg___pa2___width 3 79 #define reg_gio_rw_intr_cfg___pa3___lsb 9 80 #define reg_gio_rw_intr_cfg___pa3___width 3 81 #define reg_gio_rw_intr_cfg___pa4___lsb 12 82 #define reg_gio_rw_intr_cfg___pa4___width 3 83 #define reg_gio_rw_intr_cfg___pa5___lsb 15 84 #define reg_gio_rw_intr_cfg___pa5___width 3 85 #define reg_gio_rw_intr_cfg___pa6___lsb 18 86 #define reg_gio_rw_intr_cfg___pa6___width 3 87 #define reg_gio_rw_intr_cfg___pa7___lsb 21 88 #define reg_gio_rw_intr_cfg___pa7___width 3 89 #define reg_gio_rw_intr_cfg_offset 12 90 91 /* Register rw_intr_mask, scope gio, type rw */ 92 #define reg_gio_rw_intr_mask___pa0___lsb 0 93 #define reg_gio_rw_intr_mask___pa0___width 1 94 #define reg_gio_rw_intr_mask___pa0___bit 0 95 #define reg_gio_rw_intr_mask___pa1___lsb 1 96 #define reg_gio_rw_intr_mask___pa1___width 1 97 #define reg_gio_rw_intr_mask___pa1___bit 1 98 #define reg_gio_rw_intr_mask___pa2___lsb 2 99 #define reg_gio_rw_intr_mask___pa2___width 1 100 #define reg_gio_rw_intr_mask___pa2___bit 2 101 #define reg_gio_rw_intr_mask___pa3___lsb 3 102 #define reg_gio_rw_intr_mask___pa3___width 1 103 #define reg_gio_rw_intr_mask___pa3___bit 3 104 #define reg_gio_rw_intr_mask___pa4___lsb 4 105 #define reg_gio_rw_intr_mask___pa4___width 1 106 #define reg_gio_rw_intr_mask___pa4___bit 4 107 #define reg_gio_rw_intr_mask___pa5___lsb 5 108 #define reg_gio_rw_intr_mask___pa5___width 1 109 #define reg_gio_rw_intr_mask___pa5___bit 5 110 #define reg_gio_rw_intr_mask___pa6___lsb 6 111 #define reg_gio_rw_intr_mask___pa6___width 1 112 #define reg_gio_rw_intr_mask___pa6___bit 6 113 #define reg_gio_rw_intr_mask___pa7___lsb 7 114 #define reg_gio_rw_intr_mask___pa7___width 1 115 #define reg_gio_rw_intr_mask___pa7___bit 7 116 #define reg_gio_rw_intr_mask_offset 16 117 118 /* Register rw_ack_intr, scope gio, type rw */ 119 #define reg_gio_rw_ack_intr___pa0___lsb 0 120 #define reg_gio_rw_ack_intr___pa0___width 1 121 #define reg_gio_rw_ack_intr___pa0___bit 0 122 #define reg_gio_rw_ack_intr___pa1___lsb 1 123 #define reg_gio_rw_ack_intr___pa1___width 1 124 #define reg_gio_rw_ack_intr___pa1___bit 1 125 #define reg_gio_rw_ack_intr___pa2___lsb 2 126 #define reg_gio_rw_ack_intr___pa2___width 1 127 #define reg_gio_rw_ack_intr___pa2___bit 2 128 #define reg_gio_rw_ack_intr___pa3___lsb 3 129 #define reg_gio_rw_ack_intr___pa3___width 1 130 #define reg_gio_rw_ack_intr___pa3___bit 3 131 #define reg_gio_rw_ack_intr___pa4___lsb 4 132 #define reg_gio_rw_ack_intr___pa4___width 1 133 #define reg_gio_rw_ack_intr___pa4___bit 4 134 #define reg_gio_rw_ack_intr___pa5___lsb 5 135 #define reg_gio_rw_ack_intr___pa5___width 1 136 #define reg_gio_rw_ack_intr___pa5___bit 5 137 #define reg_gio_rw_ack_intr___pa6___lsb 6 138 #define reg_gio_rw_ack_intr___pa6___width 1 139 #define reg_gio_rw_ack_intr___pa6___bit 6 140 #define reg_gio_rw_ack_intr___pa7___lsb 7 141 #define reg_gio_rw_ack_intr___pa7___width 1 142 #define reg_gio_rw_ack_intr___pa7___bit 7 143 #define reg_gio_rw_ack_intr_offset 20 144 145 /* Register r_intr, scope gio, type r */ 146 #define reg_gio_r_intr___pa0___lsb 0 147 #define reg_gio_r_intr___pa0___width 1 148 #define reg_gio_r_intr___pa0___bit 0 149 #define reg_gio_r_intr___pa1___lsb 1 150 #define reg_gio_r_intr___pa1___width 1 151 #define reg_gio_r_intr___pa1___bit 1 152 #define reg_gio_r_intr___pa2___lsb 2 153 #define reg_gio_r_intr___pa2___width 1 154 #define reg_gio_r_intr___pa2___bit 2 155 #define reg_gio_r_intr___pa3___lsb 3 156 #define reg_gio_r_intr___pa3___width 1 157 #define reg_gio_r_intr___pa3___bit 3 158 #define reg_gio_r_intr___pa4___lsb 4 159 #define reg_gio_r_intr___pa4___width 1 160 #define reg_gio_r_intr___pa4___bit 4 161 #define reg_gio_r_intr___pa5___lsb 5 162 #define reg_gio_r_intr___pa5___width 1 163 #define reg_gio_r_intr___pa5___bit 5 164 #define reg_gio_r_intr___pa6___lsb 6 165 #define reg_gio_r_intr___pa6___width 1 166 #define reg_gio_r_intr___pa6___bit 6 167 #define reg_gio_r_intr___pa7___lsb 7 168 #define reg_gio_r_intr___pa7___width 1 169 #define reg_gio_r_intr___pa7___bit 7 170 #define reg_gio_r_intr_offset 24 171 172 /* Register r_masked_intr, scope gio, type r */ 173 #define reg_gio_r_masked_intr___pa0___lsb 0 174 #define reg_gio_r_masked_intr___pa0___width 1 175 #define reg_gio_r_masked_intr___pa0___bit 0 176 #define reg_gio_r_masked_intr___pa1___lsb 1 177 #define reg_gio_r_masked_intr___pa1___width 1 178 #define reg_gio_r_masked_intr___pa1___bit 1 179 #define reg_gio_r_masked_intr___pa2___lsb 2 180 #define reg_gio_r_masked_intr___pa2___width 1 181 #define reg_gio_r_masked_intr___pa2___bit 2 182 #define reg_gio_r_masked_intr___pa3___lsb 3 183 #define reg_gio_r_masked_intr___pa3___width 1 184 #define reg_gio_r_masked_intr___pa3___bit 3 185 #define reg_gio_r_masked_intr___pa4___lsb 4 186 #define reg_gio_r_masked_intr___pa4___width 1 187 #define reg_gio_r_masked_intr___pa4___bit 4 188 #define reg_gio_r_masked_intr___pa5___lsb 5 189 #define reg_gio_r_masked_intr___pa5___width 1 190 #define reg_gio_r_masked_intr___pa5___bit 5 191 #define reg_gio_r_masked_intr___pa6___lsb 6 192 #define reg_gio_r_masked_intr___pa6___width 1 193 #define reg_gio_r_masked_intr___pa6___bit 6 194 #define reg_gio_r_masked_intr___pa7___lsb 7 195 #define reg_gio_r_masked_intr___pa7___width 1 196 #define reg_gio_r_masked_intr___pa7___bit 7 197 #define reg_gio_r_masked_intr_offset 28 198 199 /* Register rw_pb_dout, scope gio, type rw */ 200 #define reg_gio_rw_pb_dout___data___lsb 0 201 #define reg_gio_rw_pb_dout___data___width 18 202 #define reg_gio_rw_pb_dout_offset 32 203 204 /* Register r_pb_din, scope gio, type r */ 205 #define reg_gio_r_pb_din___data___lsb 0 206 #define reg_gio_r_pb_din___data___width 18 207 #define reg_gio_r_pb_din_offset 36 208 209 /* Register rw_pb_oe, scope gio, type rw */ 210 #define reg_gio_rw_pb_oe___oe___lsb 0 211 #define reg_gio_rw_pb_oe___oe___width 18 212 #define reg_gio_rw_pb_oe_offset 40 213 214 /* Register rw_pc_dout, scope gio, type rw */ 215 #define reg_gio_rw_pc_dout___data___lsb 0 216 #define reg_gio_rw_pc_dout___data___width 18 217 #define reg_gio_rw_pc_dout_offset 48 218 219 /* Register r_pc_din, scope gio, type r */ 220 #define reg_gio_r_pc_din___data___lsb 0 221 #define reg_gio_r_pc_din___data___width 18 222 #define reg_gio_r_pc_din_offset 52 223 224 /* Register rw_pc_oe, scope gio, type rw */ 225 #define reg_gio_rw_pc_oe___oe___lsb 0 226 #define reg_gio_rw_pc_oe___oe___width 18 227 #define reg_gio_rw_pc_oe_offset 56 228 229 /* Register rw_pd_dout, scope gio, type rw */ 230 #define reg_gio_rw_pd_dout___data___lsb 0 231 #define reg_gio_rw_pd_dout___data___width 18 232 #define reg_gio_rw_pd_dout_offset 64 233 234 /* Register r_pd_din, scope gio, type r */ 235 #define reg_gio_r_pd_din___data___lsb 0 236 #define reg_gio_r_pd_din___data___width 18 237 #define reg_gio_r_pd_din_offset 68 238 239 /* Register rw_pd_oe, scope gio, type rw */ 240 #define reg_gio_rw_pd_oe___oe___lsb 0 241 #define reg_gio_rw_pd_oe___oe___width 18 242 #define reg_gio_rw_pd_oe_offset 72 243 244 /* Register rw_pe_dout, scope gio, type rw */ 245 #define reg_gio_rw_pe_dout___data___lsb 0 246 #define reg_gio_rw_pe_dout___data___width 18 247 #define reg_gio_rw_pe_dout_offset 80 248 249 /* Register r_pe_din, scope gio, type r */ 250 #define reg_gio_r_pe_din___data___lsb 0 251 #define reg_gio_r_pe_din___data___width 18 252 #define reg_gio_r_pe_din_offset 84 253 254 /* Register rw_pe_oe, scope gio, type rw */ 255 #define reg_gio_rw_pe_oe___oe___lsb 0 256 #define reg_gio_rw_pe_oe___oe___width 18 257 #define reg_gio_rw_pe_oe_offset 88 258 259 260 /* Constants */ 261 #define regk_gio_anyedge 0x00000007 262 #define regk_gio_hi 0x00000001 263 #define regk_gio_lo 0x00000002 264 #define regk_gio_negedge 0x00000006 265 #define regk_gio_no 0x00000000 266 #define regk_gio_off 0x00000000 267 #define regk_gio_posedge 0x00000005 268 #define regk_gio_rw_intr_cfg_default 0x00000000 269 #define regk_gio_rw_intr_mask_default 0x00000000 270 #define regk_gio_rw_pa_oe_default 0x00000000 271 #define regk_gio_rw_pb_oe_default 0x00000000 272 #define regk_gio_rw_pc_oe_default 0x00000000 273 #define regk_gio_rw_pd_oe_default 0x00000000 274 #define regk_gio_rw_pe_oe_default 0x00000000 275 #define regk_gio_set 0x00000003 276 #define regk_gio_yes 0x00000001 277 #endif /* __gio_defs_asm_h */ 278