1 /* SPDX-License-Identifier: GPL-2.0 */ 2 #ifndef __gio_defs_h 3 #define __gio_defs_h 4 5 /* 6 * This file is autogenerated from 7 * file: ../../inst/gio/rtl/gio_regs.r 8 * id: gio_regs.r,v 1.5 2005/02/04 09:43:21 perz Exp 9 * last modfied: Mon Apr 11 16:07:47 2005 10 * 11 * by /n/asic/design/tools/rdesc/src/rdes2c --outfile gio_defs.h ../../inst/gio/rtl/gio_regs.r 12 * id: $Id: gio_defs.h,v 1.1 2007/02/13 11:55:30 starvik Exp $ 13 * Any changes here will be lost. 14 * 15 * -*- buffer-read-only: t -*- 16 */ 17 /* Main access macros */ 18 #ifndef REG_RD 19 #define REG_RD( scope, inst, reg ) \ 20 REG_READ( reg_##scope##_##reg, \ 21 (inst) + REG_RD_ADDR_##scope##_##reg ) 22 #endif 23 24 #ifndef REG_WR 25 #define REG_WR( scope, inst, reg, val ) \ 26 REG_WRITE( reg_##scope##_##reg, \ 27 (inst) + REG_WR_ADDR_##scope##_##reg, (val) ) 28 #endif 29 30 #ifndef REG_RD_VECT 31 #define REG_RD_VECT( scope, inst, reg, index ) \ 32 REG_READ( reg_##scope##_##reg, \ 33 (inst) + REG_RD_ADDR_##scope##_##reg + \ 34 (index) * STRIDE_##scope##_##reg ) 35 #endif 36 37 #ifndef REG_WR_VECT 38 #define REG_WR_VECT( scope, inst, reg, index, val ) \ 39 REG_WRITE( reg_##scope##_##reg, \ 40 (inst) + REG_WR_ADDR_##scope##_##reg + \ 41 (index) * STRIDE_##scope##_##reg, (val) ) 42 #endif 43 44 #ifndef REG_RD_INT 45 #define REG_RD_INT( scope, inst, reg ) \ 46 REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg ) 47 #endif 48 49 #ifndef REG_WR_INT 50 #define REG_WR_INT( scope, inst, reg, val ) \ 51 REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg, (val) ) 52 #endif 53 54 #ifndef REG_RD_INT_VECT 55 #define REG_RD_INT_VECT( scope, inst, reg, index ) \ 56 REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg + \ 57 (index) * STRIDE_##scope##_##reg ) 58 #endif 59 60 #ifndef REG_WR_INT_VECT 61 #define REG_WR_INT_VECT( scope, inst, reg, index, val ) \ 62 REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg + \ 63 (index) * STRIDE_##scope##_##reg, (val) ) 64 #endif 65 66 #ifndef REG_TYPE_CONV 67 #define REG_TYPE_CONV( type, orgtype, val ) \ 68 ( { union { orgtype o; type n; } r; r.o = val; r.n; } ) 69 #endif 70 71 #ifndef reg_page_size 72 #define reg_page_size 8192 73 #endif 74 75 #ifndef REG_ADDR 76 #define REG_ADDR( scope, inst, reg ) \ 77 ( (inst) + REG_RD_ADDR_##scope##_##reg ) 78 #endif 79 80 #ifndef REG_ADDR_VECT 81 #define REG_ADDR_VECT( scope, inst, reg, index ) \ 82 ( (inst) + REG_RD_ADDR_##scope##_##reg + \ 83 (index) * STRIDE_##scope##_##reg ) 84 #endif 85 86 /* C-code for register scope gio */ 87 88 /* Register rw_pa_dout, scope gio, type rw */ 89 typedef struct { 90 unsigned int data : 8; 91 unsigned int dummy1 : 24; 92 } reg_gio_rw_pa_dout; 93 #define REG_RD_ADDR_gio_rw_pa_dout 0 94 #define REG_WR_ADDR_gio_rw_pa_dout 0 95 96 /* Register r_pa_din, scope gio, type r */ 97 typedef struct { 98 unsigned int data : 8; 99 unsigned int dummy1 : 24; 100 } reg_gio_r_pa_din; 101 #define REG_RD_ADDR_gio_r_pa_din 4 102 103 /* Register rw_pa_oe, scope gio, type rw */ 104 typedef struct { 105 unsigned int oe : 8; 106 unsigned int dummy1 : 24; 107 } reg_gio_rw_pa_oe; 108 #define REG_RD_ADDR_gio_rw_pa_oe 8 109 #define REG_WR_ADDR_gio_rw_pa_oe 8 110 111 /* Register rw_intr_cfg, scope gio, type rw */ 112 typedef struct { 113 unsigned int pa0 : 3; 114 unsigned int pa1 : 3; 115 unsigned int pa2 : 3; 116 unsigned int pa3 : 3; 117 unsigned int pa4 : 3; 118 unsigned int pa5 : 3; 119 unsigned int pa6 : 3; 120 unsigned int pa7 : 3; 121 unsigned int dummy1 : 8; 122 } reg_gio_rw_intr_cfg; 123 #define REG_RD_ADDR_gio_rw_intr_cfg 12 124 #define REG_WR_ADDR_gio_rw_intr_cfg 12 125 126 /* Register rw_intr_mask, scope gio, type rw */ 127 typedef struct { 128 unsigned int pa0 : 1; 129 unsigned int pa1 : 1; 130 unsigned int pa2 : 1; 131 unsigned int pa3 : 1; 132 unsigned int pa4 : 1; 133 unsigned int pa5 : 1; 134 unsigned int pa6 : 1; 135 unsigned int pa7 : 1; 136 unsigned int dummy1 : 24; 137 } reg_gio_rw_intr_mask; 138 #define REG_RD_ADDR_gio_rw_intr_mask 16 139 #define REG_WR_ADDR_gio_rw_intr_mask 16 140 141 /* Register rw_ack_intr, scope gio, type rw */ 142 typedef struct { 143 unsigned int pa0 : 1; 144 unsigned int pa1 : 1; 145 unsigned int pa2 : 1; 146 unsigned int pa3 : 1; 147 unsigned int pa4 : 1; 148 unsigned int pa5 : 1; 149 unsigned int pa6 : 1; 150 unsigned int pa7 : 1; 151 unsigned int dummy1 : 24; 152 } reg_gio_rw_ack_intr; 153 #define REG_RD_ADDR_gio_rw_ack_intr 20 154 #define REG_WR_ADDR_gio_rw_ack_intr 20 155 156 /* Register r_intr, scope gio, type r */ 157 typedef struct { 158 unsigned int pa0 : 1; 159 unsigned int pa1 : 1; 160 unsigned int pa2 : 1; 161 unsigned int pa3 : 1; 162 unsigned int pa4 : 1; 163 unsigned int pa5 : 1; 164 unsigned int pa6 : 1; 165 unsigned int pa7 : 1; 166 unsigned int dummy1 : 24; 167 } reg_gio_r_intr; 168 #define REG_RD_ADDR_gio_r_intr 24 169 170 /* Register r_masked_intr, scope gio, type r */ 171 typedef struct { 172 unsigned int pa0 : 1; 173 unsigned int pa1 : 1; 174 unsigned int pa2 : 1; 175 unsigned int pa3 : 1; 176 unsigned int pa4 : 1; 177 unsigned int pa5 : 1; 178 unsigned int pa6 : 1; 179 unsigned int pa7 : 1; 180 unsigned int dummy1 : 24; 181 } reg_gio_r_masked_intr; 182 #define REG_RD_ADDR_gio_r_masked_intr 28 183 184 /* Register rw_pb_dout, scope gio, type rw */ 185 typedef struct { 186 unsigned int data : 18; 187 unsigned int dummy1 : 14; 188 } reg_gio_rw_pb_dout; 189 #define REG_RD_ADDR_gio_rw_pb_dout 32 190 #define REG_WR_ADDR_gio_rw_pb_dout 32 191 192 /* Register r_pb_din, scope gio, type r */ 193 typedef struct { 194 unsigned int data : 18; 195 unsigned int dummy1 : 14; 196 } reg_gio_r_pb_din; 197 #define REG_RD_ADDR_gio_r_pb_din 36 198 199 /* Register rw_pb_oe, scope gio, type rw */ 200 typedef struct { 201 unsigned int oe : 18; 202 unsigned int dummy1 : 14; 203 } reg_gio_rw_pb_oe; 204 #define REG_RD_ADDR_gio_rw_pb_oe 40 205 #define REG_WR_ADDR_gio_rw_pb_oe 40 206 207 /* Register rw_pc_dout, scope gio, type rw */ 208 typedef struct { 209 unsigned int data : 18; 210 unsigned int dummy1 : 14; 211 } reg_gio_rw_pc_dout; 212 #define REG_RD_ADDR_gio_rw_pc_dout 48 213 #define REG_WR_ADDR_gio_rw_pc_dout 48 214 215 /* Register r_pc_din, scope gio, type r */ 216 typedef struct { 217 unsigned int data : 18; 218 unsigned int dummy1 : 14; 219 } reg_gio_r_pc_din; 220 #define REG_RD_ADDR_gio_r_pc_din 52 221 222 /* Register rw_pc_oe, scope gio, type rw */ 223 typedef struct { 224 unsigned int oe : 18; 225 unsigned int dummy1 : 14; 226 } reg_gio_rw_pc_oe; 227 #define REG_RD_ADDR_gio_rw_pc_oe 56 228 #define REG_WR_ADDR_gio_rw_pc_oe 56 229 230 /* Register rw_pd_dout, scope gio, type rw */ 231 typedef struct { 232 unsigned int data : 18; 233 unsigned int dummy1 : 14; 234 } reg_gio_rw_pd_dout; 235 #define REG_RD_ADDR_gio_rw_pd_dout 64 236 #define REG_WR_ADDR_gio_rw_pd_dout 64 237 238 /* Register r_pd_din, scope gio, type r */ 239 typedef struct { 240 unsigned int data : 18; 241 unsigned int dummy1 : 14; 242 } reg_gio_r_pd_din; 243 #define REG_RD_ADDR_gio_r_pd_din 68 244 245 /* Register rw_pd_oe, scope gio, type rw */ 246 typedef struct { 247 unsigned int oe : 18; 248 unsigned int dummy1 : 14; 249 } reg_gio_rw_pd_oe; 250 #define REG_RD_ADDR_gio_rw_pd_oe 72 251 #define REG_WR_ADDR_gio_rw_pd_oe 72 252 253 /* Register rw_pe_dout, scope gio, type rw */ 254 typedef struct { 255 unsigned int data : 18; 256 unsigned int dummy1 : 14; 257 } reg_gio_rw_pe_dout; 258 #define REG_RD_ADDR_gio_rw_pe_dout 80 259 #define REG_WR_ADDR_gio_rw_pe_dout 80 260 261 /* Register r_pe_din, scope gio, type r */ 262 typedef struct { 263 unsigned int data : 18; 264 unsigned int dummy1 : 14; 265 } reg_gio_r_pe_din; 266 #define REG_RD_ADDR_gio_r_pe_din 84 267 268 /* Register rw_pe_oe, scope gio, type rw */ 269 typedef struct { 270 unsigned int oe : 18; 271 unsigned int dummy1 : 14; 272 } reg_gio_rw_pe_oe; 273 #define REG_RD_ADDR_gio_rw_pe_oe 88 274 #define REG_WR_ADDR_gio_rw_pe_oe 88 275 276 277 /* Constants */ 278 enum { 279 regk_gio_anyedge = 0x00000007, 280 regk_gio_hi = 0x00000001, 281 regk_gio_lo = 0x00000002, 282 regk_gio_negedge = 0x00000006, 283 regk_gio_no = 0x00000000, 284 regk_gio_off = 0x00000000, 285 regk_gio_posedge = 0x00000005, 286 regk_gio_rw_intr_cfg_default = 0x00000000, 287 regk_gio_rw_intr_mask_default = 0x00000000, 288 regk_gio_rw_pa_oe_default = 0x00000000, 289 regk_gio_rw_pb_oe_default = 0x00000000, 290 regk_gio_rw_pc_oe_default = 0x00000000, 291 regk_gio_rw_pd_oe_default = 0x00000000, 292 regk_gio_rw_pe_oe_default = 0x00000000, 293 regk_gio_set = 0x00000003, 294 regk_gio_yes = 0x00000001 295 }; 296 #endif /* __gio_defs_h */ 297