1 /* bitops.h: bit operations for the Fujitsu FR-V CPUs
2 *
3 * For an explanation of how atomic ops work in this arch, see:
4 * Documentation/frv/atomic-ops.txt
5 *
6 * Copyright (C) 2004 Red Hat, Inc. All Rights Reserved.
7 * Written by David Howells (dhowells@redhat.com)
8 *
9 * This program is free software; you can redistribute it and/or
10 * modify it under the terms of the GNU General Public License
11 * as published by the Free Software Foundation; either version
12 * 2 of the License, or (at your option) any later version.
13 */
14 #ifndef _ASM_BITOPS_H
15 #define _ASM_BITOPS_H
16
17 #include <linux/compiler.h>
18 #include <asm/byteorder.h>
19
20 #ifdef __KERNEL__
21
22 #ifndef _LINUX_BITOPS_H
23 #error only <linux/bitops.h> can be included directly
24 #endif
25
26 #include <asm-generic/bitops/ffz.h>
27
28 #include <asm/atomic.h>
29
test_and_clear_bit(unsigned long nr,volatile void * addr)30 static inline int test_and_clear_bit(unsigned long nr, volatile void *addr)
31 {
32 unsigned int *ptr = (void *)addr;
33 unsigned int mask = 1UL << (nr & 31);
34 ptr += nr >> 5;
35 return (__atomic32_fetch_and(~mask, ptr) & mask) != 0;
36 }
37
test_and_set_bit(unsigned long nr,volatile void * addr)38 static inline int test_and_set_bit(unsigned long nr, volatile void *addr)
39 {
40 unsigned int *ptr = (void *)addr;
41 unsigned int mask = 1UL << (nr & 31);
42 ptr += nr >> 5;
43 return (__atomic32_fetch_or(mask, ptr) & mask) != 0;
44 }
45
test_and_change_bit(unsigned long nr,volatile void * addr)46 static inline int test_and_change_bit(unsigned long nr, volatile void *addr)
47 {
48 unsigned int *ptr = (void *)addr;
49 unsigned int mask = 1UL << (nr & 31);
50 ptr += nr >> 5;
51 return (__atomic32_fetch_xor(mask, ptr) & mask) != 0;
52 }
53
clear_bit(unsigned long nr,volatile void * addr)54 static inline void clear_bit(unsigned long nr, volatile void *addr)
55 {
56 test_and_clear_bit(nr, addr);
57 }
58
set_bit(unsigned long nr,volatile void * addr)59 static inline void set_bit(unsigned long nr, volatile void *addr)
60 {
61 test_and_set_bit(nr, addr);
62 }
63
change_bit(unsigned long nr,volatile void * addr)64 static inline void change_bit(unsigned long nr, volatile void *addr)
65 {
66 test_and_change_bit(nr, addr);
67 }
68
__clear_bit(unsigned long nr,volatile void * addr)69 static inline void __clear_bit(unsigned long nr, volatile void *addr)
70 {
71 volatile unsigned long *a = addr;
72 int mask;
73
74 a += nr >> 5;
75 mask = 1 << (nr & 31);
76 *a &= ~mask;
77 }
78
__set_bit(unsigned long nr,volatile void * addr)79 static inline void __set_bit(unsigned long nr, volatile void *addr)
80 {
81 volatile unsigned long *a = addr;
82 int mask;
83
84 a += nr >> 5;
85 mask = 1 << (nr & 31);
86 *a |= mask;
87 }
88
__change_bit(unsigned long nr,volatile void * addr)89 static inline void __change_bit(unsigned long nr, volatile void *addr)
90 {
91 volatile unsigned long *a = addr;
92 int mask;
93
94 a += nr >> 5;
95 mask = 1 << (nr & 31);
96 *a ^= mask;
97 }
98
__test_and_clear_bit(unsigned long nr,volatile void * addr)99 static inline int __test_and_clear_bit(unsigned long nr, volatile void *addr)
100 {
101 volatile unsigned long *a = addr;
102 int mask, retval;
103
104 a += nr >> 5;
105 mask = 1 << (nr & 31);
106 retval = (mask & *a) != 0;
107 *a &= ~mask;
108 return retval;
109 }
110
__test_and_set_bit(unsigned long nr,volatile void * addr)111 static inline int __test_and_set_bit(unsigned long nr, volatile void *addr)
112 {
113 volatile unsigned long *a = addr;
114 int mask, retval;
115
116 a += nr >> 5;
117 mask = 1 << (nr & 31);
118 retval = (mask & *a) != 0;
119 *a |= mask;
120 return retval;
121 }
122
__test_and_change_bit(unsigned long nr,volatile void * addr)123 static inline int __test_and_change_bit(unsigned long nr, volatile void *addr)
124 {
125 volatile unsigned long *a = addr;
126 int mask, retval;
127
128 a += nr >> 5;
129 mask = 1 << (nr & 31);
130 retval = (mask & *a) != 0;
131 *a ^= mask;
132 return retval;
133 }
134
135 /*
136 * This routine doesn't need to be atomic.
137 */
138 static inline int
__constant_test_bit(unsigned long nr,const volatile void * addr)139 __constant_test_bit(unsigned long nr, const volatile void *addr)
140 {
141 return ((1UL << (nr & 31)) & (((const volatile unsigned int *) addr)[nr >> 5])) != 0;
142 }
143
__test_bit(unsigned long nr,const volatile void * addr)144 static inline int __test_bit(unsigned long nr, const volatile void *addr)
145 {
146 int * a = (int *) addr;
147 int mask;
148
149 a += nr >> 5;
150 mask = 1 << (nr & 0x1f);
151 return ((mask & *a) != 0);
152 }
153
154 #define test_bit(nr,addr) \
155 (__builtin_constant_p(nr) ? \
156 __constant_test_bit((nr),(addr)) : \
157 __test_bit((nr),(addr)))
158
159 #include <asm-generic/bitops/find.h>
160
161 /**
162 * fls - find last bit set
163 * @x: the word to search
164 *
165 * This is defined the same way as ffs:
166 * - return 32..1 to indicate bit 31..0 most significant bit set
167 * - return 0 to indicate no bits set
168 */
169 #define fls(x) \
170 ({ \
171 int bit; \
172 \
173 asm(" subcc %1,gr0,gr0,icc0 \n" \
174 " ckne icc0,cc4 \n" \
175 " cscan.p %1,gr0,%0 ,cc4,#1 \n" \
176 " csub %0,%0,%0 ,cc4,#0 \n" \
177 " csub %2,%0,%0 ,cc4,#1 \n" \
178 : "=&r"(bit) \
179 : "r"(x), "r"(32) \
180 : "icc0", "cc4" \
181 ); \
182 \
183 bit; \
184 })
185
186 /**
187 * fls64 - find last bit set in a 64-bit value
188 * @n: the value to search
189 *
190 * This is defined the same way as ffs:
191 * - return 64..1 to indicate bit 63..0 most significant bit set
192 * - return 0 to indicate no bits set
193 */
194 static inline __attribute__((const))
fls64(u64 n)195 int fls64(u64 n)
196 {
197 union {
198 u64 ll;
199 struct { u32 h, l; };
200 } _;
201 int bit, x, y;
202
203 _.ll = n;
204
205 asm(" subcc.p %3,gr0,gr0,icc0 \n"
206 " subcc %4,gr0,gr0,icc1 \n"
207 " ckne icc0,cc4 \n"
208 " ckne icc1,cc5 \n"
209 " norcr cc4,cc5,cc6 \n"
210 " csub.p %0,%0,%0 ,cc6,1 \n"
211 " orcr cc5,cc4,cc4 \n"
212 " andcr cc4,cc5,cc4 \n"
213 " cscan.p %3,gr0,%0 ,cc4,0 \n"
214 " setlos #64,%1 \n"
215 " cscan.p %4,gr0,%0 ,cc4,1 \n"
216 " setlos #32,%2 \n"
217 " csub.p %1,%0,%0 ,cc4,0 \n"
218 " csub %2,%0,%0 ,cc4,1 \n"
219 : "=&r"(bit), "=r"(x), "=r"(y)
220 : "0r"(_.h), "r"(_.l)
221 : "icc0", "icc1", "cc4", "cc5", "cc6"
222 );
223 return bit;
224
225 }
226
227 /**
228 * ffs - find first bit set
229 * @x: the word to search
230 *
231 * - return 32..1 to indicate bit 31..0 most least significant bit set
232 * - return 0 to indicate no bits set
233 */
234 static inline __attribute__((const))
ffs(int x)235 int ffs(int x)
236 {
237 /* Note: (x & -x) gives us a mask that is the least significant
238 * (rightmost) 1-bit of the value in x.
239 */
240 return fls(x & -x);
241 }
242
243 /**
244 * __ffs - find first bit set
245 * @x: the word to search
246 *
247 * - return 31..0 to indicate bit 31..0 most least significant bit set
248 * - if no bits are set in x, the result is undefined
249 */
250 static inline __attribute__((const))
__ffs(unsigned long x)251 int __ffs(unsigned long x)
252 {
253 int bit;
254 asm("scan %1,gr0,%0" : "=r"(bit) : "r"(x & -x));
255 return 31 - bit;
256 }
257
258 /**
259 * __fls - find last (most-significant) set bit in a long word
260 * @word: the word to search
261 *
262 * Undefined if no set bit exists, so code should check against 0 first.
263 */
__fls(unsigned long word)264 static inline unsigned long __fls(unsigned long word)
265 {
266 unsigned long bit;
267 asm("scan %1,gr0,%0" : "=r"(bit) : "r"(word));
268 return bit;
269 }
270
271 /*
272 * special slimline version of fls() for calculating ilog2_u32()
273 * - note: no protection against n == 0
274 */
275 #define ARCH_HAS_ILOG2_U32
276 static inline __attribute__((const))
__ilog2_u32(u32 n)277 int __ilog2_u32(u32 n)
278 {
279 int bit;
280 asm("scan %1,gr0,%0" : "=r"(bit) : "r"(n));
281 return 31 - bit;
282 }
283
284 /*
285 * special slimline version of fls64() for calculating ilog2_u64()
286 * - note: no protection against n == 0
287 */
288 #define ARCH_HAS_ILOG2_U64
289 static inline __attribute__((const))
__ilog2_u64(u64 n)290 int __ilog2_u64(u64 n)
291 {
292 union {
293 u64 ll;
294 struct { u32 h, l; };
295 } _;
296 int bit, x, y;
297
298 _.ll = n;
299
300 asm(" subcc %3,gr0,gr0,icc0 \n"
301 " ckeq icc0,cc4 \n"
302 " cscan.p %3,gr0,%0 ,cc4,0 \n"
303 " setlos #63,%1 \n"
304 " cscan.p %4,gr0,%0 ,cc4,1 \n"
305 " setlos #31,%2 \n"
306 " csub.p %1,%0,%0 ,cc4,0 \n"
307 " csub %2,%0,%0 ,cc4,1 \n"
308 : "=&r"(bit), "=r"(x), "=r"(y)
309 : "0r"(_.h), "r"(_.l)
310 : "icc0", "cc4"
311 );
312 return bit;
313 }
314
315 #include <asm-generic/bitops/sched.h>
316 #include <asm-generic/bitops/hweight.h>
317 #include <asm-generic/bitops/lock.h>
318
319 #include <asm-generic/bitops/le.h>
320
321 #include <asm-generic/bitops/ext2-atomic-setbit.h>
322
323 #endif /* __KERNEL__ */
324
325 #endif /* _ASM_BITOPS_H */
326