1 /*
2 * This file is subject to the terms and conditions of the GNU General Public
3 * License. See the file "COPYING" in the main directory of this archive
4 * for more details.
5 *
6 * Copyright (C) 1994 - 1999, 2000 by Ralf Baechle and others.
7 * Copyright (C) 2005, 2006 by Ralf Baechle (ralf@linux-mips.org)
8 * Copyright (C) 1999, 2000 Silicon Graphics, Inc.
9 * Copyright (C) 2004 Thiemo Seufer
10 * Copyright (C) 2013 Imagination Technologies Ltd.
11 */
12 #include <linux/errno.h>
13 #include <linux/sched.h>
14 #include <linux/sched/debug.h>
15 #include <linux/sched/task.h>
16 #include <linux/sched/task_stack.h>
17 #include <linux/tick.h>
18 #include <linux/kernel.h>
19 #include <linux/mm.h>
20 #include <linux/stddef.h>
21 #include <linux/unistd.h>
22 #include <linux/export.h>
23 #include <linux/ptrace.h>
24 #include <linux/mman.h>
25 #include <linux/personality.h>
26 #include <linux/sys.h>
27 #include <linux/init.h>
28 #include <linux/completion.h>
29 #include <linux/kallsyms.h>
30 #include <linux/random.h>
31 #include <linux/prctl.h>
32 #include <linux/nmi.h>
33
34 #include <asm/abi.h>
35 #include <asm/asm.h>
36 #include <asm/bootinfo.h>
37 #include <asm/cpu.h>
38 #include <asm/dsemul.h>
39 #include <asm/dsp.h>
40 #include <asm/fpu.h>
41 #include <asm/irq.h>
42 #include <asm/mips-cps.h>
43 #include <asm/msa.h>
44 #include <asm/pgtable.h>
45 #include <asm/mipsregs.h>
46 #include <asm/processor.h>
47 #include <asm/reg.h>
48 #include <linux/uaccess.h>
49 #include <asm/io.h>
50 #include <asm/elf.h>
51 #include <asm/isadep.h>
52 #include <asm/inst.h>
53 #include <asm/stacktrace.h>
54 #include <asm/irq_regs.h>
55
56 #ifdef CONFIG_HOTPLUG_CPU
arch_cpu_idle_dead(void)57 void arch_cpu_idle_dead(void)
58 {
59 play_dead();
60 }
61 #endif
62
63 asmlinkage void ret_from_fork(void);
64 asmlinkage void ret_from_kernel_thread(void);
65
start_thread(struct pt_regs * regs,unsigned long pc,unsigned long sp)66 void start_thread(struct pt_regs * regs, unsigned long pc, unsigned long sp)
67 {
68 unsigned long status;
69
70 /* New thread loses kernel privileges. */
71 status = regs->cp0_status & ~(ST0_CU0|ST0_CU1|ST0_FR|KU_MASK);
72 status |= KU_USER;
73 regs->cp0_status = status;
74 lose_fpu(0);
75 clear_thread_flag(TIF_MSA_CTX_LIVE);
76 clear_used_math();
77 atomic_set(¤t->thread.bd_emu_frame, BD_EMUFRAME_NONE);
78 init_dsp();
79 regs->cp0_epc = pc;
80 regs->regs[29] = sp;
81 }
82
exit_thread(struct task_struct * tsk)83 void exit_thread(struct task_struct *tsk)
84 {
85 /*
86 * User threads may have allocated a delay slot emulation frame.
87 * If so, clean up that allocation.
88 */
89 if (!(current->flags & PF_KTHREAD))
90 dsemul_thread_cleanup(tsk);
91 }
92
arch_dup_task_struct(struct task_struct * dst,struct task_struct * src)93 int arch_dup_task_struct(struct task_struct *dst, struct task_struct *src)
94 {
95 /*
96 * Save any process state which is live in hardware registers to the
97 * parent context prior to duplication. This prevents the new child
98 * state becoming stale if the parent is preempted before copy_thread()
99 * gets a chance to save the parent's live hardware registers to the
100 * child context.
101 */
102 preempt_disable();
103
104 if (is_msa_enabled())
105 save_msa(current);
106 else if (is_fpu_owner())
107 _save_fp(current);
108
109 save_dsp(current);
110
111 preempt_enable();
112
113 *dst = *src;
114 return 0;
115 }
116
117 /*
118 * Copy architecture-specific thread state
119 */
copy_thread_tls(unsigned long clone_flags,unsigned long usp,unsigned long kthread_arg,struct task_struct * p,unsigned long tls)120 int copy_thread_tls(unsigned long clone_flags, unsigned long usp,
121 unsigned long kthread_arg, struct task_struct *p, unsigned long tls)
122 {
123 struct thread_info *ti = task_thread_info(p);
124 struct pt_regs *childregs, *regs = current_pt_regs();
125 unsigned long childksp;
126
127 childksp = (unsigned long)task_stack_page(p) + THREAD_SIZE - 32;
128
129 /* set up new TSS. */
130 childregs = (struct pt_regs *) childksp - 1;
131 /* Put the stack after the struct pt_regs. */
132 childksp = (unsigned long) childregs;
133 p->thread.cp0_status = read_c0_status() & ~(ST0_CU2|ST0_CU1);
134 if (unlikely(p->flags & PF_KTHREAD)) {
135 /* kernel thread */
136 unsigned long status = p->thread.cp0_status;
137 memset(childregs, 0, sizeof(struct pt_regs));
138 ti->addr_limit = KERNEL_DS;
139 p->thread.reg16 = usp; /* fn */
140 p->thread.reg17 = kthread_arg;
141 p->thread.reg29 = childksp;
142 p->thread.reg31 = (unsigned long) ret_from_kernel_thread;
143 #if defined(CONFIG_CPU_R3000) || defined(CONFIG_CPU_TX39XX)
144 status = (status & ~(ST0_KUP | ST0_IEP | ST0_IEC)) |
145 ((status & (ST0_KUC | ST0_IEC)) << 2);
146 #else
147 status |= ST0_EXL;
148 #endif
149 childregs->cp0_status = status;
150 return 0;
151 }
152
153 /* user thread */
154 *childregs = *regs;
155 childregs->regs[7] = 0; /* Clear error flag */
156 childregs->regs[2] = 0; /* Child gets zero as return value */
157 if (usp)
158 childregs->regs[29] = usp;
159 ti->addr_limit = USER_DS;
160
161 p->thread.reg29 = (unsigned long) childregs;
162 p->thread.reg31 = (unsigned long) ret_from_fork;
163
164 /*
165 * New tasks lose permission to use the fpu. This accelerates context
166 * switching for most programs since they don't use the fpu.
167 */
168 childregs->cp0_status &= ~(ST0_CU2|ST0_CU1);
169
170 clear_tsk_thread_flag(p, TIF_USEDFPU);
171 clear_tsk_thread_flag(p, TIF_USEDMSA);
172 clear_tsk_thread_flag(p, TIF_MSA_CTX_LIVE);
173
174 #ifdef CONFIG_MIPS_MT_FPAFF
175 clear_tsk_thread_flag(p, TIF_FPUBOUND);
176 #endif /* CONFIG_MIPS_MT_FPAFF */
177
178 atomic_set(&p->thread.bd_emu_frame, BD_EMUFRAME_NONE);
179
180 if (clone_flags & CLONE_SETTLS)
181 ti->tp_value = tls;
182
183 return 0;
184 }
185
186 #ifdef CONFIG_CC_STACKPROTECTOR
187 #include <linux/stackprotector.h>
188 unsigned long __stack_chk_guard __read_mostly;
189 EXPORT_SYMBOL(__stack_chk_guard);
190 #endif
191
192 struct mips_frame_info {
193 void *func;
194 unsigned long func_size;
195 int frame_size;
196 int pc_offset;
197 };
198
199 #define J_TARGET(pc,target) \
200 (((unsigned long)(pc) & 0xf0000000) | ((target) << 2))
201
is_ra_save_ins(union mips_instruction * ip,int * poff)202 static inline int is_ra_save_ins(union mips_instruction *ip, int *poff)
203 {
204 #ifdef CONFIG_CPU_MICROMIPS
205 /*
206 * swsp ra,offset
207 * swm16 reglist,offset(sp)
208 * swm32 reglist,offset(sp)
209 * sw32 ra,offset(sp)
210 * jradiussp - NOT SUPPORTED
211 *
212 * microMIPS is way more fun...
213 */
214 if (mm_insn_16bit(ip->word >> 16)) {
215 switch (ip->mm16_r5_format.opcode) {
216 case mm_swsp16_op:
217 if (ip->mm16_r5_format.rt != 31)
218 return 0;
219
220 *poff = ip->mm16_r5_format.imm;
221 *poff = (*poff << 2) / sizeof(ulong);
222 return 1;
223
224 case mm_pool16c_op:
225 switch (ip->mm16_m_format.func) {
226 case mm_swm16_op:
227 *poff = ip->mm16_m_format.imm;
228 *poff += 1 + ip->mm16_m_format.rlist;
229 *poff = (*poff << 2) / sizeof(ulong);
230 return 1;
231
232 default:
233 return 0;
234 }
235
236 default:
237 return 0;
238 }
239 }
240
241 switch (ip->i_format.opcode) {
242 case mm_sw32_op:
243 if (ip->i_format.rs != 29)
244 return 0;
245 if (ip->i_format.rt != 31)
246 return 0;
247
248 *poff = ip->i_format.simmediate / sizeof(ulong);
249 return 1;
250
251 case mm_pool32b_op:
252 switch (ip->mm_m_format.func) {
253 case mm_swm32_func:
254 if (ip->mm_m_format.rd < 0x10)
255 return 0;
256 if (ip->mm_m_format.base != 29)
257 return 0;
258
259 *poff = ip->mm_m_format.simmediate;
260 *poff += (ip->mm_m_format.rd & 0xf) * sizeof(u32);
261 *poff /= sizeof(ulong);
262 return 1;
263 default:
264 return 0;
265 }
266
267 default:
268 return 0;
269 }
270 #else
271 /* sw / sd $ra, offset($sp) */
272 if ((ip->i_format.opcode == sw_op || ip->i_format.opcode == sd_op) &&
273 ip->i_format.rs == 29 && ip->i_format.rt == 31) {
274 *poff = ip->i_format.simmediate / sizeof(ulong);
275 return 1;
276 }
277
278 return 0;
279 #endif
280 }
281
is_jump_ins(union mips_instruction * ip)282 static inline int is_jump_ins(union mips_instruction *ip)
283 {
284 #ifdef CONFIG_CPU_MICROMIPS
285 /*
286 * jr16,jrc,jalr16,jalr16
287 * jal
288 * jalr/jr,jalr.hb/jr.hb,jalrs,jalrs.hb
289 * jraddiusp - NOT SUPPORTED
290 *
291 * microMIPS is kind of more fun...
292 */
293 if (mm_insn_16bit(ip->word >> 16)) {
294 if ((ip->mm16_r5_format.opcode == mm_pool16c_op &&
295 (ip->mm16_r5_format.rt & mm_jr16_op) == mm_jr16_op))
296 return 1;
297 return 0;
298 }
299
300 if (ip->j_format.opcode == mm_j32_op)
301 return 1;
302 if (ip->j_format.opcode == mm_jal32_op)
303 return 1;
304 if (ip->r_format.opcode != mm_pool32a_op ||
305 ip->r_format.func != mm_pool32axf_op)
306 return 0;
307 return ((ip->u_format.uimmediate >> 6) & mm_jalr_op) == mm_jalr_op;
308 #else
309 if (ip->j_format.opcode == j_op)
310 return 1;
311 if (ip->j_format.opcode == jal_op)
312 return 1;
313 if (ip->r_format.opcode != spec_op)
314 return 0;
315 return ip->r_format.func == jalr_op || ip->r_format.func == jr_op;
316 #endif
317 }
318
is_sp_move_ins(union mips_instruction * ip,int * frame_size)319 static inline int is_sp_move_ins(union mips_instruction *ip, int *frame_size)
320 {
321 #ifdef CONFIG_CPU_MICROMIPS
322 unsigned short tmp;
323
324 /*
325 * addiusp -imm
326 * addius5 sp,-imm
327 * addiu32 sp,sp,-imm
328 * jradiussp - NOT SUPPORTED
329 *
330 * microMIPS is not more fun...
331 */
332 if (mm_insn_16bit(ip->word >> 16)) {
333 if (ip->mm16_r3_format.opcode == mm_pool16d_op &&
334 ip->mm16_r3_format.simmediate & mm_addiusp_func) {
335 tmp = ip->mm_b0_format.simmediate >> 1;
336 tmp = ((tmp & 0x1ff) ^ 0x100) - 0x100;
337 if ((tmp + 2) < 4) /* 0x0,0x1,0x1fe,0x1ff are special */
338 tmp ^= 0x100;
339 *frame_size = -(signed short)(tmp << 2);
340 return 1;
341 }
342 if (ip->mm16_r5_format.opcode == mm_pool16d_op &&
343 ip->mm16_r5_format.rt == 29) {
344 tmp = ip->mm16_r5_format.imm >> 1;
345 *frame_size = -(signed short)(tmp & 0xf);
346 return 1;
347 }
348 return 0;
349 }
350
351 if (ip->mm_i_format.opcode == mm_addiu32_op &&
352 ip->mm_i_format.rt == 29 && ip->mm_i_format.rs == 29) {
353 *frame_size = -ip->i_format.simmediate;
354 return 1;
355 }
356 #else
357 /* addiu/daddiu sp,sp,-imm */
358 if (ip->i_format.rs != 29 || ip->i_format.rt != 29)
359 return 0;
360
361 if (ip->i_format.opcode == addiu_op ||
362 ip->i_format.opcode == daddiu_op) {
363 *frame_size = -ip->i_format.simmediate;
364 return 1;
365 }
366 #endif
367 return 0;
368 }
369
get_frame_info(struct mips_frame_info * info)370 static int get_frame_info(struct mips_frame_info *info)
371 {
372 bool is_mmips = IS_ENABLED(CONFIG_CPU_MICROMIPS);
373 union mips_instruction insn, *ip;
374 const unsigned int max_insns = 128;
375 unsigned int last_insn_size = 0;
376 unsigned int i;
377 bool saw_jump = false;
378
379 info->pc_offset = -1;
380 info->frame_size = 0;
381
382 ip = (void *)msk_isa16_mode((ulong)info->func);
383 if (!ip)
384 goto err;
385
386 for (i = 0; i < max_insns; i++) {
387 ip = (void *)ip + last_insn_size;
388
389 if (is_mmips && mm_insn_16bit(ip->halfword[0])) {
390 insn.word = ip->halfword[0] << 16;
391 last_insn_size = 2;
392 } else if (is_mmips) {
393 insn.word = ip->halfword[0] << 16 | ip->halfword[1];
394 last_insn_size = 4;
395 } else {
396 insn.word = ip->word;
397 last_insn_size = 4;
398 }
399
400 if (!info->frame_size) {
401 is_sp_move_ins(&insn, &info->frame_size);
402 continue;
403 } else if (!saw_jump && is_jump_ins(ip)) {
404 /*
405 * If we see a jump instruction, we are finished
406 * with the frame save.
407 *
408 * Some functions can have a shortcut return at
409 * the beginning of the function, so don't start
410 * looking for jump instruction until we see the
411 * frame setup.
412 *
413 * The RA save instruction can get put into the
414 * delay slot of the jump instruction, so look
415 * at the next instruction, too.
416 */
417 saw_jump = true;
418 continue;
419 }
420 if (info->pc_offset == -1 &&
421 is_ra_save_ins(&insn, &info->pc_offset))
422 break;
423 if (saw_jump)
424 break;
425 }
426 if (info->frame_size && info->pc_offset >= 0) /* nested */
427 return 0;
428 if (info->pc_offset < 0) /* leaf */
429 return 1;
430 /* prologue seems bogus... */
431 err:
432 return -1;
433 }
434
435 static struct mips_frame_info schedule_mfi __read_mostly;
436
437 #ifdef CONFIG_KALLSYMS
get___schedule_addr(void)438 static unsigned long get___schedule_addr(void)
439 {
440 return kallsyms_lookup_name("__schedule");
441 }
442 #else
get___schedule_addr(void)443 static unsigned long get___schedule_addr(void)
444 {
445 union mips_instruction *ip = (void *)schedule;
446 int max_insns = 8;
447 int i;
448
449 for (i = 0; i < max_insns; i++, ip++) {
450 if (ip->j_format.opcode == j_op)
451 return J_TARGET(ip, ip->j_format.target);
452 }
453 return 0;
454 }
455 #endif
456
frame_info_init(void)457 static int __init frame_info_init(void)
458 {
459 unsigned long size = 0;
460 #ifdef CONFIG_KALLSYMS
461 unsigned long ofs;
462 #endif
463 unsigned long addr;
464
465 addr = get___schedule_addr();
466 if (!addr)
467 addr = (unsigned long)schedule;
468
469 #ifdef CONFIG_KALLSYMS
470 kallsyms_lookup_size_offset(addr, &size, &ofs);
471 #endif
472 schedule_mfi.func = (void *)addr;
473 schedule_mfi.func_size = size;
474
475 get_frame_info(&schedule_mfi);
476
477 /*
478 * Without schedule() frame info, result given by
479 * thread_saved_pc() and get_wchan() are not reliable.
480 */
481 if (schedule_mfi.pc_offset < 0)
482 printk("Can't analyze schedule() prologue at %p\n", schedule);
483
484 return 0;
485 }
486
487 arch_initcall(frame_info_init);
488
489 /*
490 * Return saved PC of a blocked thread.
491 */
thread_saved_pc(struct task_struct * tsk)492 unsigned long thread_saved_pc(struct task_struct *tsk)
493 {
494 struct thread_struct *t = &tsk->thread;
495
496 /* New born processes are a special case */
497 if (t->reg31 == (unsigned long) ret_from_fork)
498 return t->reg31;
499 if (schedule_mfi.pc_offset < 0)
500 return 0;
501 return ((unsigned long *)t->reg29)[schedule_mfi.pc_offset];
502 }
503
504
505 #ifdef CONFIG_KALLSYMS
506 /* generic stack unwinding function */
unwind_stack_by_address(unsigned long stack_page,unsigned long * sp,unsigned long pc,unsigned long * ra)507 unsigned long notrace unwind_stack_by_address(unsigned long stack_page,
508 unsigned long *sp,
509 unsigned long pc,
510 unsigned long *ra)
511 {
512 unsigned long low, high, irq_stack_high;
513 struct mips_frame_info info;
514 unsigned long size, ofs;
515 struct pt_regs *regs;
516 int leaf;
517
518 if (!stack_page)
519 return 0;
520
521 /*
522 * IRQ stacks start at IRQ_STACK_START
523 * task stacks at THREAD_SIZE - 32
524 */
525 low = stack_page;
526 if (!preemptible() && on_irq_stack(raw_smp_processor_id(), *sp)) {
527 high = stack_page + IRQ_STACK_START;
528 irq_stack_high = high;
529 } else {
530 high = stack_page + THREAD_SIZE - 32;
531 irq_stack_high = 0;
532 }
533
534 /*
535 * If we reached the top of the interrupt stack, start unwinding
536 * the interrupted task stack.
537 */
538 if (unlikely(*sp == irq_stack_high)) {
539 unsigned long task_sp = *(unsigned long *)*sp;
540
541 /*
542 * Check that the pointer saved in the IRQ stack head points to
543 * something within the stack of the current task
544 */
545 if (!object_is_on_stack((void *)task_sp))
546 return 0;
547
548 /*
549 * Follow pointer to tasks kernel stack frame where interrupted
550 * state was saved.
551 */
552 regs = (struct pt_regs *)task_sp;
553 pc = regs->cp0_epc;
554 if (!user_mode(regs) && __kernel_text_address(pc)) {
555 *sp = regs->regs[29];
556 *ra = regs->regs[31];
557 return pc;
558 }
559 return 0;
560 }
561 if (!kallsyms_lookup_size_offset(pc, &size, &ofs))
562 return 0;
563 /*
564 * Return ra if an exception occurred at the first instruction
565 */
566 if (unlikely(ofs == 0)) {
567 pc = *ra;
568 *ra = 0;
569 return pc;
570 }
571
572 info.func = (void *)(pc - ofs);
573 info.func_size = ofs; /* analyze from start to ofs */
574 leaf = get_frame_info(&info);
575 if (leaf < 0)
576 return 0;
577
578 if (*sp < low || *sp + info.frame_size > high)
579 return 0;
580
581 if (leaf)
582 /*
583 * For some extreme cases, get_frame_info() can
584 * consider wrongly a nested function as a leaf
585 * one. In that cases avoid to return always the
586 * same value.
587 */
588 pc = pc != *ra ? *ra : 0;
589 else
590 pc = ((unsigned long *)(*sp))[info.pc_offset];
591
592 *sp += info.frame_size;
593 *ra = 0;
594 return __kernel_text_address(pc) ? pc : 0;
595 }
596 EXPORT_SYMBOL(unwind_stack_by_address);
597
598 /* used by show_backtrace() */
unwind_stack(struct task_struct * task,unsigned long * sp,unsigned long pc,unsigned long * ra)599 unsigned long unwind_stack(struct task_struct *task, unsigned long *sp,
600 unsigned long pc, unsigned long *ra)
601 {
602 unsigned long stack_page = 0;
603 int cpu;
604
605 for_each_possible_cpu(cpu) {
606 if (on_irq_stack(cpu, *sp)) {
607 stack_page = (unsigned long)irq_stack[cpu];
608 break;
609 }
610 }
611
612 if (!stack_page)
613 stack_page = (unsigned long)task_stack_page(task);
614
615 return unwind_stack_by_address(stack_page, sp, pc, ra);
616 }
617 #endif
618
619 /*
620 * get_wchan - a maintenance nightmare^W^Wpain in the ass ...
621 */
get_wchan(struct task_struct * task)622 unsigned long get_wchan(struct task_struct *task)
623 {
624 unsigned long pc = 0;
625 #ifdef CONFIG_KALLSYMS
626 unsigned long sp;
627 unsigned long ra = 0;
628 #endif
629
630 if (!task || task == current || task->state == TASK_RUNNING)
631 goto out;
632 if (!task_stack_page(task))
633 goto out;
634
635 pc = thread_saved_pc(task);
636
637 #ifdef CONFIG_KALLSYMS
638 sp = task->thread.reg29 + schedule_mfi.frame_size;
639
640 while (in_sched_functions(pc))
641 pc = unwind_stack(task, &sp, pc, &ra);
642 #endif
643
644 out:
645 return pc;
646 }
647
mips_stack_top(void)648 unsigned long mips_stack_top(void)
649 {
650 unsigned long top = TASK_SIZE & PAGE_MASK;
651
652 /* One page for branch delay slot "emulation" */
653 top -= PAGE_SIZE;
654
655 /* Space for the VDSO, data page & GIC user page */
656 top -= PAGE_ALIGN(current->thread.abi->vdso->size);
657 top -= PAGE_SIZE;
658 top -= mips_gic_present() ? PAGE_SIZE : 0;
659
660 /* Space for cache colour alignment */
661 if (cpu_has_dc_aliases)
662 top -= shm_align_mask + 1;
663
664 /* Space to randomize the VDSO base */
665 if (current->flags & PF_RANDOMIZE)
666 top -= VDSO_RANDOMIZE_SIZE;
667
668 return top;
669 }
670
671 /*
672 * Don't forget that the stack pointer must be aligned on a 8 bytes
673 * boundary for 32-bits ABI and 16 bytes for 64-bits ABI.
674 */
arch_align_stack(unsigned long sp)675 unsigned long arch_align_stack(unsigned long sp)
676 {
677 if (!(current->personality & ADDR_NO_RANDOMIZE) && randomize_va_space)
678 sp -= get_random_int() & ~PAGE_MASK;
679
680 return sp & ALMASK;
681 }
682
683 static DEFINE_PER_CPU(call_single_data_t, backtrace_csd);
684 static struct cpumask backtrace_csd_busy;
685
handle_backtrace(void * info)686 static void handle_backtrace(void *info)
687 {
688 nmi_cpu_backtrace(get_irq_regs());
689 cpumask_clear_cpu(smp_processor_id(), &backtrace_csd_busy);
690 }
691
raise_backtrace(cpumask_t * mask)692 static void raise_backtrace(cpumask_t *mask)
693 {
694 call_single_data_t *csd;
695 int cpu;
696
697 for_each_cpu(cpu, mask) {
698 /*
699 * If we previously sent an IPI to the target CPU & it hasn't
700 * cleared its bit in the busy cpumask then it didn't handle
701 * our previous IPI & it's not safe for us to reuse the
702 * call_single_data_t.
703 */
704 if (cpumask_test_and_set_cpu(cpu, &backtrace_csd_busy)) {
705 pr_warn("Unable to send backtrace IPI to CPU%u - perhaps it hung?\n",
706 cpu);
707 continue;
708 }
709
710 csd = &per_cpu(backtrace_csd, cpu);
711 csd->func = handle_backtrace;
712 smp_call_function_single_async(cpu, csd);
713 }
714 }
715
arch_trigger_cpumask_backtrace(const cpumask_t * mask,bool exclude_self)716 void arch_trigger_cpumask_backtrace(const cpumask_t *mask, bool exclude_self)
717 {
718 nmi_trigger_cpumask_backtrace(mask, exclude_self, raise_backtrace);
719 }
720
mips_get_process_fp_mode(struct task_struct * task)721 int mips_get_process_fp_mode(struct task_struct *task)
722 {
723 int value = 0;
724
725 if (!test_tsk_thread_flag(task, TIF_32BIT_FPREGS))
726 value |= PR_FP_MODE_FR;
727 if (test_tsk_thread_flag(task, TIF_HYBRID_FPREGS))
728 value |= PR_FP_MODE_FRE;
729
730 return value;
731 }
732
prepare_for_fp_mode_switch(void * info)733 static void prepare_for_fp_mode_switch(void *info)
734 {
735 struct mm_struct *mm = info;
736
737 if (current->mm == mm)
738 lose_fpu(1);
739 }
740
mips_set_process_fp_mode(struct task_struct * task,unsigned int value)741 int mips_set_process_fp_mode(struct task_struct *task, unsigned int value)
742 {
743 const unsigned int known_bits = PR_FP_MODE_FR | PR_FP_MODE_FRE;
744 struct task_struct *t;
745 int max_users;
746
747 /* If nothing to change, return right away, successfully. */
748 if (value == mips_get_process_fp_mode(task))
749 return 0;
750
751 /* Only accept a mode change if 64-bit FP enabled for o32. */
752 if (!IS_ENABLED(CONFIG_MIPS_O32_FP64_SUPPORT))
753 return -EOPNOTSUPP;
754
755 /* And only for o32 tasks. */
756 if (IS_ENABLED(CONFIG_64BIT) && !test_thread_flag(TIF_32BIT_REGS))
757 return -EOPNOTSUPP;
758
759 /* Check the value is valid */
760 if (value & ~known_bits)
761 return -EOPNOTSUPP;
762
763 /* Setting FRE without FR is not supported. */
764 if ((value & (PR_FP_MODE_FR | PR_FP_MODE_FRE)) == PR_FP_MODE_FRE)
765 return -EOPNOTSUPP;
766
767 /* Avoid inadvertently triggering emulation */
768 if ((value & PR_FP_MODE_FR) && raw_cpu_has_fpu &&
769 !(raw_current_cpu_data.fpu_id & MIPS_FPIR_F64))
770 return -EOPNOTSUPP;
771 if ((value & PR_FP_MODE_FRE) && raw_cpu_has_fpu && !cpu_has_fre)
772 return -EOPNOTSUPP;
773
774 /* FR = 0 not supported in MIPS R6 */
775 if (!(value & PR_FP_MODE_FR) && raw_cpu_has_fpu && cpu_has_mips_r6)
776 return -EOPNOTSUPP;
777
778 /* Proceed with the mode switch */
779 preempt_disable();
780
781 /* Save FP & vector context, then disable FPU & MSA */
782 if (task->signal == current->signal)
783 lose_fpu(1);
784
785 /* Prevent any threads from obtaining live FP context */
786 atomic_set(&task->mm->context.fp_mode_switching, 1);
787 smp_mb__after_atomic();
788
789 /*
790 * If there are multiple online CPUs then force any which are running
791 * threads in this process to lose their FPU context, which they can't
792 * regain until fp_mode_switching is cleared later.
793 */
794 if (num_online_cpus() > 1) {
795 /* No need to send an IPI for the local CPU */
796 max_users = (task->mm == current->mm) ? 1 : 0;
797
798 if (atomic_read(¤t->mm->mm_users) > max_users)
799 smp_call_function(prepare_for_fp_mode_switch,
800 (void *)current->mm, 1);
801 }
802
803 /*
804 * There are now no threads of the process with live FP context, so it
805 * is safe to proceed with the FP mode switch.
806 */
807 for_each_thread(task, t) {
808 /* Update desired FP register width */
809 if (value & PR_FP_MODE_FR) {
810 clear_tsk_thread_flag(t, TIF_32BIT_FPREGS);
811 } else {
812 set_tsk_thread_flag(t, TIF_32BIT_FPREGS);
813 clear_tsk_thread_flag(t, TIF_MSA_CTX_LIVE);
814 }
815
816 /* Update desired FP single layout */
817 if (value & PR_FP_MODE_FRE)
818 set_tsk_thread_flag(t, TIF_HYBRID_FPREGS);
819 else
820 clear_tsk_thread_flag(t, TIF_HYBRID_FPREGS);
821 }
822
823 /* Allow threads to use FP again */
824 atomic_set(&task->mm->context.fp_mode_switching, 0);
825 preempt_enable();
826
827 return 0;
828 }
829
830 #if defined(CONFIG_32BIT) || defined(CONFIG_MIPS32_O32)
mips_dump_regs32(u32 * uregs,const struct pt_regs * regs)831 void mips_dump_regs32(u32 *uregs, const struct pt_regs *regs)
832 {
833 unsigned int i;
834
835 for (i = MIPS32_EF_R1; i <= MIPS32_EF_R31; i++) {
836 /* k0/k1 are copied as zero. */
837 if (i == MIPS32_EF_R26 || i == MIPS32_EF_R27)
838 uregs[i] = 0;
839 else
840 uregs[i] = regs->regs[i - MIPS32_EF_R0];
841 }
842
843 uregs[MIPS32_EF_LO] = regs->lo;
844 uregs[MIPS32_EF_HI] = regs->hi;
845 uregs[MIPS32_EF_CP0_EPC] = regs->cp0_epc;
846 uregs[MIPS32_EF_CP0_BADVADDR] = regs->cp0_badvaddr;
847 uregs[MIPS32_EF_CP0_STATUS] = regs->cp0_status;
848 uregs[MIPS32_EF_CP0_CAUSE] = regs->cp0_cause;
849 }
850 #endif /* CONFIG_32BIT || CONFIG_MIPS32_O32 */
851
852 #ifdef CONFIG_64BIT
mips_dump_regs64(u64 * uregs,const struct pt_regs * regs)853 void mips_dump_regs64(u64 *uregs, const struct pt_regs *regs)
854 {
855 unsigned int i;
856
857 for (i = MIPS64_EF_R1; i <= MIPS64_EF_R31; i++) {
858 /* k0/k1 are copied as zero. */
859 if (i == MIPS64_EF_R26 || i == MIPS64_EF_R27)
860 uregs[i] = 0;
861 else
862 uregs[i] = regs->regs[i - MIPS64_EF_R0];
863 }
864
865 uregs[MIPS64_EF_LO] = regs->lo;
866 uregs[MIPS64_EF_HI] = regs->hi;
867 uregs[MIPS64_EF_CP0_EPC] = regs->cp0_epc;
868 uregs[MIPS64_EF_CP0_BADVADDR] = regs->cp0_badvaddr;
869 uregs[MIPS64_EF_CP0_STATUS] = regs->cp0_status;
870 uregs[MIPS64_EF_CP0_CAUSE] = regs->cp0_cause;
871 }
872 #endif /* CONFIG_64BIT */
873