1 /* ASB2303-specific timer specifications 2 * 3 * Copyright (C) 2007, 2010 Red Hat, Inc. All Rights Reserved. 4 * Written by David Howells (dhowells@redhat.com) 5 * 6 * This program is free software; you can redistribute it and/or 7 * modify it under the terms of the GNU General Public Licence 8 * as published by the Free Software Foundation; either version 9 * 2 of the Licence, or (at your option) any later version. 10 */ 11 #ifndef _ASM_UNIT_TIMEX_H 12 #define _ASM_UNIT_TIMEX_H 13 14 #include <asm/timer-regs.h> 15 #include <unit/clock.h> 16 #include <asm/param.h> 17 18 /* 19 * jiffies counter specifications 20 */ 21 22 #define TMJCBR_MAX 0xffff 23 #define TMJCIRQ TM1IRQ 24 #define TMJCICR TM1ICR 25 26 #ifndef __ASSEMBLY__ 27 28 #define MN10300_SRC_IOCLK MN10300_IOCLK 29 30 #ifndef HZ 31 # error HZ undeclared. 32 #endif /* !HZ */ 33 /* use as little prescaling as possible to avoid losing accuracy */ 34 #if (MN10300_SRC_IOCLK + HZ / 2) / HZ - 1 <= TMJCBR_MAX 35 # define IOCLK_PRESCALE 1 36 # define JC_TIMER_CLKSRC TM0MD_SRC_IOCLK 37 # define TSC_TIMER_CLKSRC TM4MD_SRC_IOCLK 38 #elif (MN10300_SRC_IOCLK / 8 + HZ / 2) / HZ - 1 <= TMJCBR_MAX 39 # define IOCLK_PRESCALE 8 40 # define JC_TIMER_CLKSRC TM0MD_SRC_IOCLK_8 41 # define TSC_TIMER_CLKSRC TM4MD_SRC_IOCLK_8 42 #elif (MN10300_SRC_IOCLK / 32 + HZ / 2) / HZ - 1 <= TMJCBR_MAX 43 # define IOCLK_PRESCALE 32 44 # define JC_TIMER_CLKSRC TM0MD_SRC_IOCLK_32 45 # define TSC_TIMER_CLKSRC TM4MD_SRC_IOCLK_32 46 #else 47 # error You lose. 48 #endif 49 50 #define MN10300_JCCLK (MN10300_SRC_IOCLK / IOCLK_PRESCALE) 51 #define MN10300_TSCCLK (MN10300_SRC_IOCLK / IOCLK_PRESCALE) 52 53 #define MN10300_JC_PER_HZ ((MN10300_JCCLK + HZ / 2) / HZ) 54 #define MN10300_TSC_PER_HZ ((MN10300_TSCCLK + HZ / 2) / HZ) 55 stop_jiffies_counter(void)56static inline void stop_jiffies_counter(void) 57 { 58 u16 tmp; 59 TM01MD = JC_TIMER_CLKSRC | TM1MD_SRC_TM0CASCADE << 8; 60 tmp = TM01MD; 61 } 62 reload_jiffies_counter(u32 cnt)63static inline void reload_jiffies_counter(u32 cnt) 64 { 65 u32 tmp; 66 67 TM01BR = cnt; 68 tmp = TM01BR; 69 70 TM01MD = JC_TIMER_CLKSRC | \ 71 TM1MD_SRC_TM0CASCADE << 8 | \ 72 TM0MD_INIT_COUNTER | \ 73 TM1MD_INIT_COUNTER << 8; 74 75 76 TM01MD = JC_TIMER_CLKSRC | \ 77 TM1MD_SRC_TM0CASCADE << 8 | \ 78 TM0MD_COUNT_ENABLE | \ 79 TM1MD_COUNT_ENABLE << 8; 80 81 tmp = TM01MD; 82 } 83 84 #endif /* !__ASSEMBLY__ */ 85 86 87 /* 88 * timestamp counter specifications 89 */ 90 91 #define TMTSCBR_MAX 0xffffffff 92 #define TMTSCBC TM45BC 93 94 #ifndef __ASSEMBLY__ 95 startup_timestamp_counter(void)96static inline void startup_timestamp_counter(void) 97 { 98 u32 t32; 99 100 /* set up timer 4 & 5 cascaded as a 32-bit counter to count real time 101 * - count down from 4Gig-1 to 0 and wrap at IOCLK rate 102 */ 103 TM45BR = TMTSCBR_MAX; 104 t32 = TM45BR; 105 106 TM4MD = TSC_TIMER_CLKSRC; 107 TM4MD |= TM4MD_INIT_COUNTER; 108 TM4MD &= ~TM4MD_INIT_COUNTER; 109 TM4ICR = 0; 110 t32 = TM4ICR; 111 112 TM5MD = TM5MD_SRC_TM4CASCADE; 113 TM5MD |= TM5MD_INIT_COUNTER; 114 TM5MD &= ~TM5MD_INIT_COUNTER; 115 TM5ICR = 0; 116 t32 = TM5ICR; 117 118 TM5MD |= TM5MD_COUNT_ENABLE; 119 TM4MD |= TM4MD_COUNT_ENABLE; 120 t32 = TM5MD; 121 t32 = TM4MD; 122 } 123 shutdown_timestamp_counter(void)124static inline void shutdown_timestamp_counter(void) 125 { 126 u8 t8; 127 TM4MD = 0; 128 TM5MD = 0; 129 t8 = TM4MD; 130 t8 = TM5MD; 131 } 132 133 /* 134 * we use a cascaded pair of 16-bit down-counting timers to count I/O 135 * clock cycles for the purposes of time keeping 136 */ 137 typedef unsigned long cycles_t; 138 read_timestamp_counter(void)139static inline cycles_t read_timestamp_counter(void) 140 { 141 return (cycles_t)~TMTSCBC; 142 } 143 144 #endif /* !__ASSEMBLY__ */ 145 146 #endif /* _ASM_UNIT_TIMEX_H */ 147