1/* 2 * SBC8641D Device Tree Source 3 * 4 * Copyright 2008 Wind River Systems Inc. 5 * 6 * Paul Gortmaker (see MAINTAINERS for contact information) 7 * 8 * Based largely on the mpc8641_hpcn.dts by Freescale Semiconductor Inc. 9 * 10 * This program is free software; you can redistribute it and/or modify it 11 * under the terms of the GNU General Public License as published by the 12 * Free Software Foundation; either version 2 of the License, or (at your 13 * option) any later version. 14 */ 15 16/include/ "mpc8641si-pre.dtsi" 17 18/ { 19 model = "SBC8641D"; 20 compatible = "wind,sbc8641"; 21 22 memory { 23 device_type = "memory"; 24 reg = <0x00000000 0x20000000>; // 512M at 0x0 25 }; 26 27 lbc: localbus@f8005000 { 28 reg = <0xf8005000 0x1000>; 29 30 ranges = <0 0 0xff000000 0x01000000 // 16MB Boot flash 31 1 0 0xf0000000 0x00010000 // 64KB EEPROM 32 2 0 0xf1000000 0x00100000 // EPLD (1MB) 33 3 0 0xe0000000 0x04000000 // 64MB LB SDRAM (CS3) 34 4 0 0xe4000000 0x04000000 // 64MB LB SDRAM (CS4) 35 6 0 0xf4000000 0x00100000 // LCD display (1MB) 36 7 0 0xe8000000 0x04000000>; // 64MB OneNAND 37 38 flash@0,0 { 39 compatible = "cfi-flash"; 40 reg = <0 0 0x01000000>; 41 bank-width = <2>; 42 device-width = <2>; 43 #address-cells = <1>; 44 #size-cells = <1>; 45 partition@0 { 46 label = "dtb"; 47 reg = <0x00000000 0x00100000>; 48 read-only; 49 }; 50 partition@300000 { 51 label = "kernel"; 52 reg = <0x00100000 0x00400000>; 53 read-only; 54 }; 55 partition@400000 { 56 label = "fs"; 57 reg = <0x00500000 0x00a00000>; 58 }; 59 partition@700000 { 60 label = "firmware"; 61 reg = <0x00f00000 0x00100000>; 62 read-only; 63 }; 64 }; 65 66 epld@2,0 { 67 compatible = "wrs,epld-localbus"; 68 #address-cells = <2>; 69 #size-cells = <1>; 70 reg = <2 0 0x100000>; 71 ranges = <0 0 5 0 1 // User switches 72 1 0 5 1 1 // Board ID/Rev 73 3 0 5 3 1>; // LEDs 74 }; 75 }; 76 77 soc: soc@f8000000 { 78 ranges = <0x00000000 0xf8000000 0x00100000>; 79 80 enet0: ethernet@24000 { 81 tbi-handle = <&tbi0>; 82 phy-handle = <&phy0>; 83 phy-connection-type = "rgmii-id"; 84 }; 85 86 mdio@24520 { 87 phy0: ethernet-phy@1f { 88 reg = <0x1f>; 89 }; 90 phy1: ethernet-phy@0 { 91 reg = <0>; 92 }; 93 phy2: ethernet-phy@1 { 94 reg = <1>; 95 }; 96 phy3: ethernet-phy@2 { 97 reg = <2>; 98 }; 99 tbi0: tbi-phy@11 { 100 reg = <0x11>; 101 device_type = "tbi-phy"; 102 }; 103 }; 104 105 enet1: ethernet@25000 { 106 tbi-handle = <&tbi1>; 107 phy-handle = <&phy1>; 108 phy-connection-type = "rgmii-id"; 109 }; 110 111 mdio@25520 { 112 tbi1: tbi-phy@11 { 113 reg = <0x11>; 114 device_type = "tbi-phy"; 115 }; 116 }; 117 118 enet2: ethernet@26000 { 119 tbi-handle = <&tbi2>; 120 phy-handle = <&phy2>; 121 phy-connection-type = "rgmii-id"; 122 }; 123 124 mdio@26520 { 125 tbi2: tbi-phy@11 { 126 reg = <0x11>; 127 device_type = "tbi-phy"; 128 }; 129 }; 130 131 enet3: ethernet@27000 { 132 tbi-handle = <&tbi3>; 133 phy-handle = <&phy3>; 134 phy-connection-type = "rgmii-id"; 135 }; 136 137 mdio@27520 { 138 tbi3: tbi-phy@11 { 139 reg = <0x11>; 140 device_type = "tbi-phy"; 141 }; 142 }; 143 }; 144 145 pci0: pcie@f8008000 { 146 reg = <0xf8008000 0x1000>; 147 ranges = <0x02000000 0x0 0x80000000 0x80000000 0x0 0x20000000 148 0x01000000 0x0 0x00000000 0xe2000000 0x0 0x00100000>; 149 interrupt-map-mask = <0xff00 0 0 7>; 150 151 pcie@0 { 152 ranges = <0x02000000 0x0 0x80000000 153 0x02000000 0x0 0x80000000 154 0x0 0x20000000 155 156 0x01000000 0x0 0x00000000 157 0x01000000 0x0 0x00000000 158 0x0 0x00100000>; 159 }; 160 161 }; 162 163 pci1: pcie@f8009000 { 164 reg = <0xf8009000 0x1000>; 165 ranges = <0x02000000 0x0 0xa0000000 0xa0000000 0x0 0x20000000 166 0x01000000 0x0 0x00000000 0xe3000000 0x0 0x00100000>; 167 168 pcie@0 { 169 ranges = <0x02000000 0x0 0xa0000000 170 0x02000000 0x0 0xa0000000 171 0x0 0x20000000 172 173 0x01000000 0x0 0x00000000 174 0x01000000 0x0 0x00000000 175 0x0 0x00100000>; 176 }; 177 }; 178}; 179 180/include/ "mpc8641si-post.dtsi" 181