1/* 2 * Boot code and exception vectors for Book3E processors 3 * 4 * Copyright (C) 2007 Ben. Herrenschmidt (benh@kernel.crashing.org), IBM Corp. 5 * 6 * This program is free software; you can redistribute it and/or 7 * modify it under the terms of the GNU General Public License 8 * as published by the Free Software Foundation; either version 9 * 2 of the License, or (at your option) any later version. 10 */ 11 12#include <linux/threads.h> 13#include <asm/reg.h> 14#include <asm/page.h> 15#include <asm/ppc_asm.h> 16#include <asm/asm-offsets.h> 17#include <asm/cputable.h> 18#include <asm/setup.h> 19#include <asm/thread_info.h> 20#include <asm/reg_a2.h> 21#include <asm/exception-64e.h> 22#include <asm/bug.h> 23#include <asm/irqflags.h> 24#include <asm/ptrace.h> 25#include <asm/ppc-opcode.h> 26#include <asm/mmu.h> 27#include <asm/hw_irq.h> 28#include <asm/kvm_asm.h> 29#include <asm/kvm_booke_hv_asm.h> 30 31/* XXX This will ultimately add space for a special exception save 32 * structure used to save things like SRR0/SRR1, SPRGs, MAS, etc... 33 * when taking special interrupts. For now we don't support that, 34 * special interrupts from within a non-standard level will probably 35 * blow you up 36 */ 37#define SPECIAL_EXC_SRR0 0 38#define SPECIAL_EXC_SRR1 1 39#define SPECIAL_EXC_SPRG_GEN 2 40#define SPECIAL_EXC_SPRG_TLB 3 41#define SPECIAL_EXC_MAS0 4 42#define SPECIAL_EXC_MAS1 5 43#define SPECIAL_EXC_MAS2 6 44#define SPECIAL_EXC_MAS3 7 45#define SPECIAL_EXC_MAS6 8 46#define SPECIAL_EXC_MAS7 9 47#define SPECIAL_EXC_MAS5 10 /* E.HV only */ 48#define SPECIAL_EXC_MAS8 11 /* E.HV only */ 49#define SPECIAL_EXC_IRQHAPPENED 12 50#define SPECIAL_EXC_DEAR 13 51#define SPECIAL_EXC_ESR 14 52#define SPECIAL_EXC_SOFTE 15 53#define SPECIAL_EXC_CSRR0 16 54#define SPECIAL_EXC_CSRR1 17 55/* must be even to keep 16-byte stack alignment */ 56#define SPECIAL_EXC_END 18 57 58#define SPECIAL_EXC_FRAME_SIZE (INT_FRAME_SIZE + SPECIAL_EXC_END * 8) 59#define SPECIAL_EXC_FRAME_OFFS (INT_FRAME_SIZE - 288) 60 61#define SPECIAL_EXC_STORE(reg, name) \ 62 std reg, (SPECIAL_EXC_##name * 8 + SPECIAL_EXC_FRAME_OFFS)(r1) 63 64#define SPECIAL_EXC_LOAD(reg, name) \ 65 ld reg, (SPECIAL_EXC_##name * 8 + SPECIAL_EXC_FRAME_OFFS)(r1) 66 67special_reg_save: 68 lbz r9,PACAIRQHAPPENED(r13) 69 RECONCILE_IRQ_STATE(r3,r4) 70 71 /* 72 * We only need (or have stack space) to save this stuff if 73 * we interrupted the kernel. 74 */ 75 ld r3,_MSR(r1) 76 andi. r3,r3,MSR_PR 77 bnelr 78 79 /* Copy info into temporary exception thread info */ 80 ld r11,PACAKSAVE(r13) 81 CURRENT_THREAD_INFO(r11, r11) 82 CURRENT_THREAD_INFO(r12, r1) 83 ld r10,TI_FLAGS(r11) 84 std r10,TI_FLAGS(r12) 85 ld r10,TI_PREEMPT(r11) 86 std r10,TI_PREEMPT(r12) 87 ld r10,TI_TASK(r11) 88 std r10,TI_TASK(r12) 89 90 /* 91 * Advance to the next TLB exception frame for handler 92 * types that don't do it automatically. 93 */ 94 LOAD_REG_ADDR(r11,extlb_level_exc) 95 lwz r12,0(r11) 96 mfspr r10,SPRN_SPRG_TLB_EXFRAME 97 add r10,r10,r12 98 mtspr SPRN_SPRG_TLB_EXFRAME,r10 99 100 /* 101 * Save registers needed to allow nesting of certain exceptions 102 * (such as TLB misses) inside special exception levels 103 */ 104 mfspr r10,SPRN_SRR0 105 SPECIAL_EXC_STORE(r10,SRR0) 106 mfspr r10,SPRN_SRR1 107 SPECIAL_EXC_STORE(r10,SRR1) 108 mfspr r10,SPRN_SPRG_GEN_SCRATCH 109 SPECIAL_EXC_STORE(r10,SPRG_GEN) 110 mfspr r10,SPRN_SPRG_TLB_SCRATCH 111 SPECIAL_EXC_STORE(r10,SPRG_TLB) 112 mfspr r10,SPRN_MAS0 113 SPECIAL_EXC_STORE(r10,MAS0) 114 mfspr r10,SPRN_MAS1 115 SPECIAL_EXC_STORE(r10,MAS1) 116 mfspr r10,SPRN_MAS2 117 SPECIAL_EXC_STORE(r10,MAS2) 118 mfspr r10,SPRN_MAS3 119 SPECIAL_EXC_STORE(r10,MAS3) 120 mfspr r10,SPRN_MAS6 121 SPECIAL_EXC_STORE(r10,MAS6) 122 mfspr r10,SPRN_MAS7 123 SPECIAL_EXC_STORE(r10,MAS7) 124BEGIN_FTR_SECTION 125 mfspr r10,SPRN_MAS5 126 SPECIAL_EXC_STORE(r10,MAS5) 127 mfspr r10,SPRN_MAS8 128 SPECIAL_EXC_STORE(r10,MAS8) 129 130 /* MAS5/8 could have inappropriate values if we interrupted KVM code */ 131 li r10,0 132 mtspr SPRN_MAS5,r10 133 mtspr SPRN_MAS8,r10 134END_FTR_SECTION_IFSET(CPU_FTR_EMB_HV) 135 SPECIAL_EXC_STORE(r9,IRQHAPPENED) 136 137 mfspr r10,SPRN_DEAR 138 SPECIAL_EXC_STORE(r10,DEAR) 139 mfspr r10,SPRN_ESR 140 SPECIAL_EXC_STORE(r10,ESR) 141 142 lbz r10,PACASOFTIRQEN(r13) 143 SPECIAL_EXC_STORE(r10,SOFTE) 144 ld r10,_NIP(r1) 145 SPECIAL_EXC_STORE(r10,CSRR0) 146 ld r10,_MSR(r1) 147 SPECIAL_EXC_STORE(r10,CSRR1) 148 149 blr 150 151ret_from_level_except: 152 ld r3,_MSR(r1) 153 andi. r3,r3,MSR_PR 154 beq 1f 155 b ret_from_except 1561: 157 158 LOAD_REG_ADDR(r11,extlb_level_exc) 159 lwz r12,0(r11) 160 mfspr r10,SPRN_SPRG_TLB_EXFRAME 161 sub r10,r10,r12 162 mtspr SPRN_SPRG_TLB_EXFRAME,r10 163 164 /* 165 * It's possible that the special level exception interrupted a 166 * TLB miss handler, and inserted the same entry that the 167 * interrupted handler was about to insert. On CPUs without TLB 168 * write conditional, this can result in a duplicate TLB entry. 169 * Wipe all non-bolted entries to be safe. 170 * 171 * Note that this doesn't protect against any TLB misses 172 * we may take accessing the stack from here to the end of 173 * the special level exception. It's not clear how we can 174 * reasonably protect against that, but only CPUs with 175 * neither TLB write conditional nor bolted kernel memory 176 * are affected. Do any such CPUs even exist? 177 */ 178 PPC_TLBILX_ALL(0,R0) 179 180 REST_NVGPRS(r1) 181 182 SPECIAL_EXC_LOAD(r10,SRR0) 183 mtspr SPRN_SRR0,r10 184 SPECIAL_EXC_LOAD(r10,SRR1) 185 mtspr SPRN_SRR1,r10 186 SPECIAL_EXC_LOAD(r10,SPRG_GEN) 187 mtspr SPRN_SPRG_GEN_SCRATCH,r10 188 SPECIAL_EXC_LOAD(r10,SPRG_TLB) 189 mtspr SPRN_SPRG_TLB_SCRATCH,r10 190 SPECIAL_EXC_LOAD(r10,MAS0) 191 mtspr SPRN_MAS0,r10 192 SPECIAL_EXC_LOAD(r10,MAS1) 193 mtspr SPRN_MAS1,r10 194 SPECIAL_EXC_LOAD(r10,MAS2) 195 mtspr SPRN_MAS2,r10 196 SPECIAL_EXC_LOAD(r10,MAS3) 197 mtspr SPRN_MAS3,r10 198 SPECIAL_EXC_LOAD(r10,MAS6) 199 mtspr SPRN_MAS6,r10 200 SPECIAL_EXC_LOAD(r10,MAS7) 201 mtspr SPRN_MAS7,r10 202BEGIN_FTR_SECTION 203 SPECIAL_EXC_LOAD(r10,MAS5) 204 mtspr SPRN_MAS5,r10 205 SPECIAL_EXC_LOAD(r10,MAS8) 206 mtspr SPRN_MAS8,r10 207END_FTR_SECTION_IFSET(CPU_FTR_EMB_HV) 208 209 lbz r6,PACASOFTIRQEN(r13) 210 ld r5,SOFTE(r1) 211 212 /* Interrupts had better not already be enabled... */ 213 twnei r6,0 214 215 cmpwi cr0,r5,0 216 beq 1f 217 218 TRACE_ENABLE_INTS 219 stb r5,PACASOFTIRQEN(r13) 2201: 221 /* 222 * Restore PACAIRQHAPPENED rather than setting it based on 223 * the return MSR[EE], since we could have interrupted 224 * __check_irq_replay() or other inconsistent transitory 225 * states that must remain that way. 226 */ 227 SPECIAL_EXC_LOAD(r10,IRQHAPPENED) 228 stb r10,PACAIRQHAPPENED(r13) 229 230 SPECIAL_EXC_LOAD(r10,DEAR) 231 mtspr SPRN_DEAR,r10 232 SPECIAL_EXC_LOAD(r10,ESR) 233 mtspr SPRN_ESR,r10 234 235 stdcx. r0,0,r1 /* to clear the reservation */ 236 237 REST_4GPRS(2, r1) 238 REST_4GPRS(6, r1) 239 240 ld r10,_CTR(r1) 241 ld r11,_XER(r1) 242 mtctr r10 243 mtxer r11 244 245 blr 246 247.macro ret_from_level srr0 srr1 paca_ex scratch 248 bl ret_from_level_except 249 250 ld r10,_LINK(r1) 251 ld r11,_CCR(r1) 252 ld r0,GPR13(r1) 253 mtlr r10 254 mtcr r11 255 256 ld r10,GPR10(r1) 257 ld r11,GPR11(r1) 258 ld r12,GPR12(r1) 259 mtspr \scratch,r0 260 261 std r10,\paca_ex+EX_R10(r13); 262 std r11,\paca_ex+EX_R11(r13); 263 ld r10,_NIP(r1) 264 ld r11,_MSR(r1) 265 ld r0,GPR0(r1) 266 ld r1,GPR1(r1) 267 mtspr \srr0,r10 268 mtspr \srr1,r11 269 ld r10,\paca_ex+EX_R10(r13) 270 ld r11,\paca_ex+EX_R11(r13) 271 mfspr r13,\scratch 272.endm 273 274ret_from_crit_except: 275 ret_from_level SPRN_CSRR0 SPRN_CSRR1 PACA_EXCRIT SPRN_SPRG_CRIT_SCRATCH 276 rfci 277 278ret_from_mc_except: 279 ret_from_level SPRN_MCSRR0 SPRN_MCSRR1 PACA_EXMC SPRN_SPRG_MC_SCRATCH 280 rfmci 281 282/* Exception prolog code for all exceptions */ 283#define EXCEPTION_PROLOG(n, intnum, type, addition) \ 284 mtspr SPRN_SPRG_##type##_SCRATCH,r13; /* get spare registers */ \ 285 mfspr r13,SPRN_SPRG_PACA; /* get PACA */ \ 286 std r10,PACA_EX##type+EX_R10(r13); \ 287 std r11,PACA_EX##type+EX_R11(r13); \ 288 mfcr r10; /* save CR */ \ 289 mfspr r11,SPRN_##type##_SRR1;/* what are we coming from */ \ 290 DO_KVM intnum,SPRN_##type##_SRR1; /* KVM hook */ \ 291 stw r10,PACA_EX##type+EX_CR(r13); /* save old CR in the PACA */ \ 292 addition; /* additional code for that exc. */ \ 293 std r1,PACA_EX##type+EX_R1(r13); /* save old r1 in the PACA */ \ 294 type##_SET_KSTACK; /* get special stack if necessary */\ 295 andi. r10,r11,MSR_PR; /* save stack pointer */ \ 296 beq 1f; /* branch around if supervisor */ \ 297 ld r1,PACAKSAVE(r13); /* get kernel stack coming from usr */\ 2981: type##_BTB_FLUSH \ 299 cmpdi cr1,r1,0; /* check if SP makes sense */ \ 300 bge- cr1,exc_##n##_bad_stack;/* bad stack (TODO: out of line) */ \ 301 mfspr r10,SPRN_##type##_SRR0; /* read SRR0 before touching stack */ 302 303/* Exception type-specific macros */ 304#define GEN_SET_KSTACK \ 305 subi r1,r1,INT_FRAME_SIZE; /* alloc frame on kernel stack */ 306#define SPRN_GEN_SRR0 SPRN_SRR0 307#define SPRN_GEN_SRR1 SPRN_SRR1 308 309#define GDBELL_SET_KSTACK GEN_SET_KSTACK 310#define SPRN_GDBELL_SRR0 SPRN_GSRR0 311#define SPRN_GDBELL_SRR1 SPRN_GSRR1 312 313#define CRIT_SET_KSTACK \ 314 ld r1,PACA_CRIT_STACK(r13); \ 315 subi r1,r1,SPECIAL_EXC_FRAME_SIZE 316#define SPRN_CRIT_SRR0 SPRN_CSRR0 317#define SPRN_CRIT_SRR1 SPRN_CSRR1 318 319#define DBG_SET_KSTACK \ 320 ld r1,PACA_DBG_STACK(r13); \ 321 subi r1,r1,SPECIAL_EXC_FRAME_SIZE 322#define SPRN_DBG_SRR0 SPRN_DSRR0 323#define SPRN_DBG_SRR1 SPRN_DSRR1 324 325#define MC_SET_KSTACK \ 326 ld r1,PACA_MC_STACK(r13); \ 327 subi r1,r1,SPECIAL_EXC_FRAME_SIZE 328#define SPRN_MC_SRR0 SPRN_MCSRR0 329#define SPRN_MC_SRR1 SPRN_MCSRR1 330 331#ifdef CONFIG_PPC_FSL_BOOK3E 332#define GEN_BTB_FLUSH \ 333 START_BTB_FLUSH_SECTION \ 334 beq 1f; \ 335 BTB_FLUSH(r10) \ 336 1: \ 337 END_BTB_FLUSH_SECTION 338 339#define CRIT_BTB_FLUSH \ 340 START_BTB_FLUSH_SECTION \ 341 BTB_FLUSH(r10) \ 342 END_BTB_FLUSH_SECTION 343 344#define DBG_BTB_FLUSH CRIT_BTB_FLUSH 345#define MC_BTB_FLUSH CRIT_BTB_FLUSH 346#define GDBELL_BTB_FLUSH GEN_BTB_FLUSH 347#else 348#define GEN_BTB_FLUSH 349#define CRIT_BTB_FLUSH 350#define DBG_BTB_FLUSH 351#define MC_BTB_FLUSH 352#define GDBELL_BTB_FLUSH 353#endif 354 355#define NORMAL_EXCEPTION_PROLOG(n, intnum, addition) \ 356 EXCEPTION_PROLOG(n, intnum, GEN, addition##_GEN(n)) 357 358#define CRIT_EXCEPTION_PROLOG(n, intnum, addition) \ 359 EXCEPTION_PROLOG(n, intnum, CRIT, addition##_CRIT(n)) 360 361#define DBG_EXCEPTION_PROLOG(n, intnum, addition) \ 362 EXCEPTION_PROLOG(n, intnum, DBG, addition##_DBG(n)) 363 364#define MC_EXCEPTION_PROLOG(n, intnum, addition) \ 365 EXCEPTION_PROLOG(n, intnum, MC, addition##_MC(n)) 366 367#define GDBELL_EXCEPTION_PROLOG(n, intnum, addition) \ 368 EXCEPTION_PROLOG(n, intnum, GDBELL, addition##_GDBELL(n)) 369 370/* Variants of the "addition" argument for the prolog 371 */ 372#define PROLOG_ADDITION_NONE_GEN(n) 373#define PROLOG_ADDITION_NONE_GDBELL(n) 374#define PROLOG_ADDITION_NONE_CRIT(n) 375#define PROLOG_ADDITION_NONE_DBG(n) 376#define PROLOG_ADDITION_NONE_MC(n) 377 378#define PROLOG_ADDITION_MASKABLE_GEN(n) \ 379 lbz r10,PACASOFTIRQEN(r13); /* are irqs soft-disabled ? */ \ 380 cmpwi cr0,r10,0; /* yes -> go out of line */ \ 381 beq masked_interrupt_book3e_##n 382 383#define PROLOG_ADDITION_2REGS_GEN(n) \ 384 std r14,PACA_EXGEN+EX_R14(r13); \ 385 std r15,PACA_EXGEN+EX_R15(r13) 386 387#define PROLOG_ADDITION_1REG_GEN(n) \ 388 std r14,PACA_EXGEN+EX_R14(r13); 389 390#define PROLOG_ADDITION_2REGS_CRIT(n) \ 391 std r14,PACA_EXCRIT+EX_R14(r13); \ 392 std r15,PACA_EXCRIT+EX_R15(r13) 393 394#define PROLOG_ADDITION_2REGS_DBG(n) \ 395 std r14,PACA_EXDBG+EX_R14(r13); \ 396 std r15,PACA_EXDBG+EX_R15(r13) 397 398#define PROLOG_ADDITION_2REGS_MC(n) \ 399 std r14,PACA_EXMC+EX_R14(r13); \ 400 std r15,PACA_EXMC+EX_R15(r13) 401 402 403/* Core exception code for all exceptions except TLB misses. */ 404#define EXCEPTION_COMMON_LVL(n, scratch, excf) \ 405exc_##n##_common: \ 406 std r0,GPR0(r1); /* save r0 in stackframe */ \ 407 std r2,GPR2(r1); /* save r2 in stackframe */ \ 408 SAVE_4GPRS(3, r1); /* save r3 - r6 in stackframe */ \ 409 SAVE_2GPRS(7, r1); /* save r7, r8 in stackframe */ \ 410 std r9,GPR9(r1); /* save r9 in stackframe */ \ 411 std r10,_NIP(r1); /* save SRR0 to stackframe */ \ 412 std r11,_MSR(r1); /* save SRR1 to stackframe */ \ 413 beq 2f; /* if from kernel mode */ \ 414 ACCOUNT_CPU_USER_ENTRY(r13,r10,r11);/* accounting (uses cr0+eq) */ \ 4152: ld r3,excf+EX_R10(r13); /* get back r10 */ \ 416 ld r4,excf+EX_R11(r13); /* get back r11 */ \ 417 mfspr r5,scratch; /* get back r13 */ \ 418 std r12,GPR12(r1); /* save r12 in stackframe */ \ 419 ld r2,PACATOC(r13); /* get kernel TOC into r2 */ \ 420 mflr r6; /* save LR in stackframe */ \ 421 mfctr r7; /* save CTR in stackframe */ \ 422 mfspr r8,SPRN_XER; /* save XER in stackframe */ \ 423 ld r9,excf+EX_R1(r13); /* load orig r1 back from PACA */ \ 424 lwz r10,excf+EX_CR(r13); /* load orig CR back from PACA */ \ 425 lbz r11,PACASOFTIRQEN(r13); /* get current IRQ softe */ \ 426 ld r12,exception_marker@toc(r2); \ 427 li r0,0; \ 428 std r3,GPR10(r1); /* save r10 to stackframe */ \ 429 std r4,GPR11(r1); /* save r11 to stackframe */ \ 430 std r5,GPR13(r1); /* save it to stackframe */ \ 431 std r6,_LINK(r1); \ 432 std r7,_CTR(r1); \ 433 std r8,_XER(r1); \ 434 li r3,(n)+1; /* indicate partial regs in trap */ \ 435 std r9,0(r1); /* store stack frame back link */ \ 436 std r10,_CCR(r1); /* store orig CR in stackframe */ \ 437 std r9,GPR1(r1); /* store stack frame back link */ \ 438 std r11,SOFTE(r1); /* and save it to stackframe */ \ 439 std r12,STACK_FRAME_OVERHEAD-16(r1); /* mark the frame */ \ 440 std r3,_TRAP(r1); /* set trap number */ \ 441 std r0,RESULT(r1); /* clear regs->result */ 442 443#define EXCEPTION_COMMON(n) \ 444 EXCEPTION_COMMON_LVL(n, SPRN_SPRG_GEN_SCRATCH, PACA_EXGEN) 445#define EXCEPTION_COMMON_CRIT(n) \ 446 EXCEPTION_COMMON_LVL(n, SPRN_SPRG_CRIT_SCRATCH, PACA_EXCRIT) 447#define EXCEPTION_COMMON_MC(n) \ 448 EXCEPTION_COMMON_LVL(n, SPRN_SPRG_MC_SCRATCH, PACA_EXMC) 449#define EXCEPTION_COMMON_DBG(n) \ 450 EXCEPTION_COMMON_LVL(n, SPRN_SPRG_DBG_SCRATCH, PACA_EXDBG) 451 452/* 453 * This is meant for exceptions that don't immediately hard-enable. We 454 * set a bit in paca->irq_happened to ensure that a subsequent call to 455 * arch_local_irq_restore() will properly hard-enable and avoid the 456 * fast-path, and then reconcile irq state. 457 */ 458#define INTS_DISABLE RECONCILE_IRQ_STATE(r3,r4) 459 460/* 461 * This is called by exceptions that don't use INTS_DISABLE (that did not 462 * touch irq indicators in the PACA). This will restore MSR:EE to it's 463 * previous value 464 * 465 * XXX In the long run, we may want to open-code it in order to separate the 466 * load from the wrtee, thus limiting the latency caused by the dependency 467 * but at this point, I'll favor code clarity until we have a near to final 468 * implementation 469 */ 470#define INTS_RESTORE_HARD \ 471 ld r11,_MSR(r1); \ 472 wrtee r11; 473 474/* XXX FIXME: Restore r14/r15 when necessary */ 475#define BAD_STACK_TRAMPOLINE(n) \ 476exc_##n##_bad_stack: \ 477 li r1,(n); /* get exception number */ \ 478 sth r1,PACA_TRAP_SAVE(r13); /* store trap */ \ 479 b bad_stack_book3e; /* bad stack error */ 480 481/* WARNING: If you change the layout of this stub, make sure you check 482 * the debug exception handler which handles single stepping 483 * into exceptions from userspace, and the MM code in 484 * arch/powerpc/mm/tlb_nohash.c which patches the branch here 485 * and would need to be updated if that branch is moved 486 */ 487#define EXCEPTION_STUB(loc, label) \ 488 . = interrupt_base_book3e + loc; \ 489 nop; /* To make debug interrupts happy */ \ 490 b exc_##label##_book3e; 491 492#define ACK_NONE(r) 493#define ACK_DEC(r) \ 494 lis r,TSR_DIS@h; \ 495 mtspr SPRN_TSR,r 496#define ACK_FIT(r) \ 497 lis r,TSR_FIS@h; \ 498 mtspr SPRN_TSR,r 499 500/* Used by asynchronous interrupt that may happen in the idle loop. 501 * 502 * This check if the thread was in the idle loop, and if yes, returns 503 * to the caller rather than the PC. This is to avoid a race if 504 * interrupts happen before the wait instruction. 505 */ 506#define CHECK_NAPPING() \ 507 CURRENT_THREAD_INFO(r11, r1); \ 508 ld r10,TI_LOCAL_FLAGS(r11); \ 509 andi. r9,r10,_TLF_NAPPING; \ 510 beq+ 1f; \ 511 ld r8,_LINK(r1); \ 512 rlwinm r7,r10,0,~_TLF_NAPPING; \ 513 std r8,_NIP(r1); \ 514 std r7,TI_LOCAL_FLAGS(r11); \ 5151: 516 517 518#define MASKABLE_EXCEPTION(trapnum, intnum, label, hdlr, ack) \ 519 START_EXCEPTION(label); \ 520 NORMAL_EXCEPTION_PROLOG(trapnum, intnum, PROLOG_ADDITION_MASKABLE)\ 521 EXCEPTION_COMMON(trapnum) \ 522 INTS_DISABLE; \ 523 ack(r8); \ 524 CHECK_NAPPING(); \ 525 addi r3,r1,STACK_FRAME_OVERHEAD; \ 526 bl hdlr; \ 527 b ret_from_except_lite; 528 529/* This value is used to mark exception frames on the stack. */ 530 .section ".toc","aw" 531exception_marker: 532 .tc ID_EXC_MARKER[TC],STACK_FRAME_REGS_MARKER 533 534 535/* 536 * And here we have the exception vectors ! 537 */ 538 539 .text 540 .balign 0x1000 541 .globl interrupt_base_book3e 542interrupt_base_book3e: /* fake trap */ 543 EXCEPTION_STUB(0x000, machine_check) 544 EXCEPTION_STUB(0x020, critical_input) /* 0x0100 */ 545 EXCEPTION_STUB(0x040, debug_crit) /* 0x0d00 */ 546 EXCEPTION_STUB(0x060, data_storage) /* 0x0300 */ 547 EXCEPTION_STUB(0x080, instruction_storage) /* 0x0400 */ 548 EXCEPTION_STUB(0x0a0, external_input) /* 0x0500 */ 549 EXCEPTION_STUB(0x0c0, alignment) /* 0x0600 */ 550 EXCEPTION_STUB(0x0e0, program) /* 0x0700 */ 551 EXCEPTION_STUB(0x100, fp_unavailable) /* 0x0800 */ 552 EXCEPTION_STUB(0x120, system_call) /* 0x0c00 */ 553 EXCEPTION_STUB(0x140, ap_unavailable) /* 0x0f20 */ 554 EXCEPTION_STUB(0x160, decrementer) /* 0x0900 */ 555 EXCEPTION_STUB(0x180, fixed_interval) /* 0x0980 */ 556 EXCEPTION_STUB(0x1a0, watchdog) /* 0x09f0 */ 557 EXCEPTION_STUB(0x1c0, data_tlb_miss) 558 EXCEPTION_STUB(0x1e0, instruction_tlb_miss) 559 EXCEPTION_STUB(0x200, altivec_unavailable) 560 EXCEPTION_STUB(0x220, altivec_assist) 561 EXCEPTION_STUB(0x260, perfmon) 562 EXCEPTION_STUB(0x280, doorbell) 563 EXCEPTION_STUB(0x2a0, doorbell_crit) 564 EXCEPTION_STUB(0x2c0, guest_doorbell) 565 EXCEPTION_STUB(0x2e0, guest_doorbell_crit) 566 EXCEPTION_STUB(0x300, hypercall) 567 EXCEPTION_STUB(0x320, ehpriv) 568 EXCEPTION_STUB(0x340, lrat_error) 569 570 .globl __end_interrupts 571__end_interrupts: 572 573/* Critical Input Interrupt */ 574 START_EXCEPTION(critical_input); 575 CRIT_EXCEPTION_PROLOG(0x100, BOOKE_INTERRUPT_CRITICAL, 576 PROLOG_ADDITION_NONE) 577 EXCEPTION_COMMON_CRIT(0x100) 578 bl save_nvgprs 579 bl special_reg_save 580 CHECK_NAPPING(); 581 addi r3,r1,STACK_FRAME_OVERHEAD 582 bl unknown_exception 583 b ret_from_crit_except 584 585/* Machine Check Interrupt */ 586 START_EXCEPTION(machine_check); 587 MC_EXCEPTION_PROLOG(0x000, BOOKE_INTERRUPT_MACHINE_CHECK, 588 PROLOG_ADDITION_NONE) 589 EXCEPTION_COMMON_MC(0x000) 590 bl save_nvgprs 591 bl special_reg_save 592 CHECK_NAPPING(); 593 addi r3,r1,STACK_FRAME_OVERHEAD 594 bl machine_check_exception 595 b ret_from_mc_except 596 597/* Data Storage Interrupt */ 598 START_EXCEPTION(data_storage) 599 NORMAL_EXCEPTION_PROLOG(0x300, BOOKE_INTERRUPT_DATA_STORAGE, 600 PROLOG_ADDITION_2REGS) 601 mfspr r14,SPRN_DEAR 602 mfspr r15,SPRN_ESR 603 EXCEPTION_COMMON(0x300) 604 INTS_DISABLE 605 b storage_fault_common 606 607/* Instruction Storage Interrupt */ 608 START_EXCEPTION(instruction_storage); 609 NORMAL_EXCEPTION_PROLOG(0x400, BOOKE_INTERRUPT_INST_STORAGE, 610 PROLOG_ADDITION_2REGS) 611 li r15,0 612 mr r14,r10 613 EXCEPTION_COMMON(0x400) 614 INTS_DISABLE 615 b storage_fault_common 616 617/* External Input Interrupt */ 618 MASKABLE_EXCEPTION(0x500, BOOKE_INTERRUPT_EXTERNAL, 619 external_input, do_IRQ, ACK_NONE) 620 621/* Alignment */ 622 START_EXCEPTION(alignment); 623 NORMAL_EXCEPTION_PROLOG(0x600, BOOKE_INTERRUPT_ALIGNMENT, 624 PROLOG_ADDITION_2REGS) 625 mfspr r14,SPRN_DEAR 626 mfspr r15,SPRN_ESR 627 EXCEPTION_COMMON(0x600) 628 b alignment_more /* no room, go out of line */ 629 630/* Program Interrupt */ 631 START_EXCEPTION(program); 632 NORMAL_EXCEPTION_PROLOG(0x700, BOOKE_INTERRUPT_PROGRAM, 633 PROLOG_ADDITION_1REG) 634 mfspr r14,SPRN_ESR 635 EXCEPTION_COMMON(0x700) 636 INTS_DISABLE 637 std r14,_DSISR(r1) 638 addi r3,r1,STACK_FRAME_OVERHEAD 639 ld r14,PACA_EXGEN+EX_R14(r13) 640 bl save_nvgprs 641 bl program_check_exception 642 b ret_from_except 643 644/* Floating Point Unavailable Interrupt */ 645 START_EXCEPTION(fp_unavailable); 646 NORMAL_EXCEPTION_PROLOG(0x800, BOOKE_INTERRUPT_FP_UNAVAIL, 647 PROLOG_ADDITION_NONE) 648 /* we can probably do a shorter exception entry for that one... */ 649 EXCEPTION_COMMON(0x800) 650 ld r12,_MSR(r1) 651 andi. r0,r12,MSR_PR; 652 beq- 1f 653 bl load_up_fpu 654 b fast_exception_return 6551: INTS_DISABLE 656 bl save_nvgprs 657 addi r3,r1,STACK_FRAME_OVERHEAD 658 bl kernel_fp_unavailable_exception 659 b ret_from_except 660 661/* Altivec Unavailable Interrupt */ 662 START_EXCEPTION(altivec_unavailable); 663 NORMAL_EXCEPTION_PROLOG(0x200, BOOKE_INTERRUPT_ALTIVEC_UNAVAIL, 664 PROLOG_ADDITION_NONE) 665 /* we can probably do a shorter exception entry for that one... */ 666 EXCEPTION_COMMON(0x200) 667#ifdef CONFIG_ALTIVEC 668BEGIN_FTR_SECTION 669 ld r12,_MSR(r1) 670 andi. r0,r12,MSR_PR; 671 beq- 1f 672 bl load_up_altivec 673 b fast_exception_return 6741: 675END_FTR_SECTION_IFSET(CPU_FTR_ALTIVEC) 676#endif 677 INTS_DISABLE 678 bl save_nvgprs 679 addi r3,r1,STACK_FRAME_OVERHEAD 680 bl altivec_unavailable_exception 681 b ret_from_except 682 683/* AltiVec Assist */ 684 START_EXCEPTION(altivec_assist); 685 NORMAL_EXCEPTION_PROLOG(0x220, 686 BOOKE_INTERRUPT_ALTIVEC_ASSIST, 687 PROLOG_ADDITION_NONE) 688 EXCEPTION_COMMON(0x220) 689 INTS_DISABLE 690 bl save_nvgprs 691 addi r3,r1,STACK_FRAME_OVERHEAD 692#ifdef CONFIG_ALTIVEC 693BEGIN_FTR_SECTION 694 bl altivec_assist_exception 695END_FTR_SECTION_IFSET(CPU_FTR_ALTIVEC) 696#else 697 bl unknown_exception 698#endif 699 b ret_from_except 700 701 702/* Decrementer Interrupt */ 703 MASKABLE_EXCEPTION(0x900, BOOKE_INTERRUPT_DECREMENTER, 704 decrementer, timer_interrupt, ACK_DEC) 705 706/* Fixed Interval Timer Interrupt */ 707 MASKABLE_EXCEPTION(0x980, BOOKE_INTERRUPT_FIT, 708 fixed_interval, unknown_exception, ACK_FIT) 709 710/* Watchdog Timer Interrupt */ 711 START_EXCEPTION(watchdog); 712 CRIT_EXCEPTION_PROLOG(0x9f0, BOOKE_INTERRUPT_WATCHDOG, 713 PROLOG_ADDITION_NONE) 714 EXCEPTION_COMMON_CRIT(0x9f0) 715 bl save_nvgprs 716 bl special_reg_save 717 CHECK_NAPPING(); 718 addi r3,r1,STACK_FRAME_OVERHEAD 719#ifdef CONFIG_BOOKE_WDT 720 bl WatchdogException 721#else 722 bl unknown_exception 723#endif 724 b ret_from_crit_except 725 726/* System Call Interrupt */ 727 START_EXCEPTION(system_call) 728 mr r9,r13 /* keep a copy of userland r13 */ 729 mfspr r11,SPRN_SRR0 /* get return address */ 730 mfspr r12,SPRN_SRR1 /* get previous MSR */ 731 mfspr r13,SPRN_SPRG_PACA /* get our PACA */ 732 b system_call_common 733 734/* Auxiliary Processor Unavailable Interrupt */ 735 START_EXCEPTION(ap_unavailable); 736 NORMAL_EXCEPTION_PROLOG(0xf20, BOOKE_INTERRUPT_AP_UNAVAIL, 737 PROLOG_ADDITION_NONE) 738 EXCEPTION_COMMON(0xf20) 739 INTS_DISABLE 740 bl save_nvgprs 741 addi r3,r1,STACK_FRAME_OVERHEAD 742 bl unknown_exception 743 b ret_from_except 744 745/* Debug exception as a critical interrupt*/ 746 START_EXCEPTION(debug_crit); 747 CRIT_EXCEPTION_PROLOG(0xd00, BOOKE_INTERRUPT_DEBUG, 748 PROLOG_ADDITION_2REGS) 749 750 /* 751 * If there is a single step or branch-taken exception in an 752 * exception entry sequence, it was probably meant to apply to 753 * the code where the exception occurred (since exception entry 754 * doesn't turn off DE automatically). We simulate the effect 755 * of turning off DE on entry to an exception handler by turning 756 * off DE in the CSRR1 value and clearing the debug status. 757 */ 758 759 mfspr r14,SPRN_DBSR /* check single-step/branch taken */ 760 andis. r15,r14,(DBSR_IC|DBSR_BT)@h 761 beq+ 1f 762 763#ifdef CONFIG_RELOCATABLE 764 ld r15,PACATOC(r13) 765 ld r14,interrupt_base_book3e@got(r15) 766 ld r15,__end_interrupts@got(r15) 767#else 768 LOAD_REG_IMMEDIATE(r14,interrupt_base_book3e) 769 LOAD_REG_IMMEDIATE(r15,__end_interrupts) 770#endif 771 cmpld cr0,r10,r14 772 cmpld cr1,r10,r15 773 blt+ cr0,1f 774 bge+ cr1,1f 775 776 /* here it looks like we got an inappropriate debug exception. */ 777 lis r14,(DBSR_IC|DBSR_BT)@h /* clear the event */ 778 rlwinm r11,r11,0,~MSR_DE /* clear DE in the CSRR1 value */ 779 mtspr SPRN_DBSR,r14 780 mtspr SPRN_CSRR1,r11 781 lwz r10,PACA_EXCRIT+EX_CR(r13) /* restore registers */ 782 ld r1,PACA_EXCRIT+EX_R1(r13) 783 ld r14,PACA_EXCRIT+EX_R14(r13) 784 ld r15,PACA_EXCRIT+EX_R15(r13) 785 mtcr r10 786 ld r10,PACA_EXCRIT+EX_R10(r13) /* restore registers */ 787 ld r11,PACA_EXCRIT+EX_R11(r13) 788 mfspr r13,SPRN_SPRG_CRIT_SCRATCH 789 rfci 790 791 /* Normal debug exception */ 792 /* XXX We only handle coming from userspace for now since we can't 793 * quite save properly an interrupted kernel state yet 794 */ 7951: andi. r14,r11,MSR_PR; /* check for userspace again */ 796 beq kernel_dbg_exc; /* if from kernel mode */ 797 798 /* Now we mash up things to make it look like we are coming on a 799 * normal exception 800 */ 801 mfspr r14,SPRN_DBSR 802 EXCEPTION_COMMON_CRIT(0xd00) 803 std r14,_DSISR(r1) 804 addi r3,r1,STACK_FRAME_OVERHEAD 805 mr r4,r14 806 ld r14,PACA_EXCRIT+EX_R14(r13) 807 ld r15,PACA_EXCRIT+EX_R15(r13) 808 bl save_nvgprs 809 bl DebugException 810 b ret_from_except 811 812kernel_dbg_exc: 813 b . /* NYI */ 814 815/* Debug exception as a debug interrupt*/ 816 START_EXCEPTION(debug_debug); 817 DBG_EXCEPTION_PROLOG(0xd00, BOOKE_INTERRUPT_DEBUG, 818 PROLOG_ADDITION_2REGS) 819 820 /* 821 * If there is a single step or branch-taken exception in an 822 * exception entry sequence, it was probably meant to apply to 823 * the code where the exception occurred (since exception entry 824 * doesn't turn off DE automatically). We simulate the effect 825 * of turning off DE on entry to an exception handler by turning 826 * off DE in the DSRR1 value and clearing the debug status. 827 */ 828 829 mfspr r14,SPRN_DBSR /* check single-step/branch taken */ 830 andis. r15,r14,(DBSR_IC|DBSR_BT)@h 831 beq+ 1f 832 833#ifdef CONFIG_RELOCATABLE 834 ld r15,PACATOC(r13) 835 ld r14,interrupt_base_book3e@got(r15) 836 ld r15,__end_interrupts@got(r15) 837#else 838 LOAD_REG_IMMEDIATE(r14,interrupt_base_book3e) 839 LOAD_REG_IMMEDIATE(r15,__end_interrupts) 840#endif 841 cmpld cr0,r10,r14 842 cmpld cr1,r10,r15 843 blt+ cr0,1f 844 bge+ cr1,1f 845 846 /* here it looks like we got an inappropriate debug exception. */ 847 lis r14,(DBSR_IC|DBSR_BT)@h /* clear the event */ 848 rlwinm r11,r11,0,~MSR_DE /* clear DE in the DSRR1 value */ 849 mtspr SPRN_DBSR,r14 850 mtspr SPRN_DSRR1,r11 851 lwz r10,PACA_EXDBG+EX_CR(r13) /* restore registers */ 852 ld r1,PACA_EXDBG+EX_R1(r13) 853 ld r14,PACA_EXDBG+EX_R14(r13) 854 ld r15,PACA_EXDBG+EX_R15(r13) 855 mtcr r10 856 ld r10,PACA_EXDBG+EX_R10(r13) /* restore registers */ 857 ld r11,PACA_EXDBG+EX_R11(r13) 858 mfspr r13,SPRN_SPRG_DBG_SCRATCH 859 rfdi 860 861 /* Normal debug exception */ 862 /* XXX We only handle coming from userspace for now since we can't 863 * quite save properly an interrupted kernel state yet 864 */ 8651: andi. r14,r11,MSR_PR; /* check for userspace again */ 866 beq kernel_dbg_exc; /* if from kernel mode */ 867 868 /* Now we mash up things to make it look like we are coming on a 869 * normal exception 870 */ 871 mfspr r14,SPRN_DBSR 872 EXCEPTION_COMMON_DBG(0xd08) 873 INTS_DISABLE 874 std r14,_DSISR(r1) 875 addi r3,r1,STACK_FRAME_OVERHEAD 876 mr r4,r14 877 ld r14,PACA_EXDBG+EX_R14(r13) 878 ld r15,PACA_EXDBG+EX_R15(r13) 879 bl save_nvgprs 880 bl DebugException 881 b ret_from_except 882 883 START_EXCEPTION(perfmon); 884 NORMAL_EXCEPTION_PROLOG(0x260, BOOKE_INTERRUPT_PERFORMANCE_MONITOR, 885 PROLOG_ADDITION_NONE) 886 EXCEPTION_COMMON(0x260) 887 INTS_DISABLE 888 CHECK_NAPPING() 889 addi r3,r1,STACK_FRAME_OVERHEAD 890 bl performance_monitor_exception 891 b ret_from_except_lite 892 893/* Doorbell interrupt */ 894 MASKABLE_EXCEPTION(0x280, BOOKE_INTERRUPT_DOORBELL, 895 doorbell, doorbell_exception, ACK_NONE) 896 897/* Doorbell critical Interrupt */ 898 START_EXCEPTION(doorbell_crit); 899 CRIT_EXCEPTION_PROLOG(0x2a0, BOOKE_INTERRUPT_DOORBELL_CRITICAL, 900 PROLOG_ADDITION_NONE) 901 EXCEPTION_COMMON_CRIT(0x2a0) 902 bl save_nvgprs 903 bl special_reg_save 904 CHECK_NAPPING(); 905 addi r3,r1,STACK_FRAME_OVERHEAD 906 bl unknown_exception 907 b ret_from_crit_except 908 909/* 910 * Guest doorbell interrupt 911 * This general exception use GSRRx save/restore registers 912 */ 913 START_EXCEPTION(guest_doorbell); 914 GDBELL_EXCEPTION_PROLOG(0x2c0, BOOKE_INTERRUPT_GUEST_DBELL, 915 PROLOG_ADDITION_NONE) 916 EXCEPTION_COMMON(0x2c0) 917 addi r3,r1,STACK_FRAME_OVERHEAD 918 bl save_nvgprs 919 INTS_RESTORE_HARD 920 bl unknown_exception 921 b ret_from_except 922 923/* Guest Doorbell critical Interrupt */ 924 START_EXCEPTION(guest_doorbell_crit); 925 CRIT_EXCEPTION_PROLOG(0x2e0, BOOKE_INTERRUPT_GUEST_DBELL_CRIT, 926 PROLOG_ADDITION_NONE) 927 EXCEPTION_COMMON_CRIT(0x2e0) 928 bl save_nvgprs 929 bl special_reg_save 930 CHECK_NAPPING(); 931 addi r3,r1,STACK_FRAME_OVERHEAD 932 bl unknown_exception 933 b ret_from_crit_except 934 935/* Hypervisor call */ 936 START_EXCEPTION(hypercall); 937 NORMAL_EXCEPTION_PROLOG(0x310, BOOKE_INTERRUPT_HV_SYSCALL, 938 PROLOG_ADDITION_NONE) 939 EXCEPTION_COMMON(0x310) 940 addi r3,r1,STACK_FRAME_OVERHEAD 941 bl save_nvgprs 942 INTS_RESTORE_HARD 943 bl unknown_exception 944 b ret_from_except 945 946/* Embedded Hypervisor priviledged */ 947 START_EXCEPTION(ehpriv); 948 NORMAL_EXCEPTION_PROLOG(0x320, BOOKE_INTERRUPT_HV_PRIV, 949 PROLOG_ADDITION_NONE) 950 EXCEPTION_COMMON(0x320) 951 addi r3,r1,STACK_FRAME_OVERHEAD 952 bl save_nvgprs 953 INTS_RESTORE_HARD 954 bl unknown_exception 955 b ret_from_except 956 957/* LRAT Error interrupt */ 958 START_EXCEPTION(lrat_error); 959 NORMAL_EXCEPTION_PROLOG(0x340, BOOKE_INTERRUPT_LRAT_ERROR, 960 PROLOG_ADDITION_NONE) 961 EXCEPTION_COMMON(0x340) 962 addi r3,r1,STACK_FRAME_OVERHEAD 963 bl save_nvgprs 964 INTS_RESTORE_HARD 965 bl unknown_exception 966 b ret_from_except 967 968/* 969 * An interrupt came in while soft-disabled; We mark paca->irq_happened 970 * accordingly and if the interrupt is level sensitive, we hard disable 971 */ 972 973.macro masked_interrupt_book3e paca_irq full_mask 974 lbz r10,PACAIRQHAPPENED(r13) 975 ori r10,r10,\paca_irq 976 stb r10,PACAIRQHAPPENED(r13) 977 978 .if \full_mask == 1 979 rldicl r10,r11,48,1 /* clear MSR_EE */ 980 rotldi r11,r10,16 981 mtspr SPRN_SRR1,r11 982 .endif 983 984 lwz r11,PACA_EXGEN+EX_CR(r13) 985 mtcr r11 986 ld r10,PACA_EXGEN+EX_R10(r13) 987 ld r11,PACA_EXGEN+EX_R11(r13) 988 mfspr r13,SPRN_SPRG_GEN_SCRATCH 989 rfi 990 b . 991.endm 992 993masked_interrupt_book3e_0x500: 994 // XXX When adding support for EPR, use PACA_IRQ_EE_EDGE 995 masked_interrupt_book3e PACA_IRQ_EE 1 996 997masked_interrupt_book3e_0x900: 998 ACK_DEC(r10); 999 masked_interrupt_book3e PACA_IRQ_DEC 0 1000 1001masked_interrupt_book3e_0x980: 1002 ACK_FIT(r10); 1003 masked_interrupt_book3e PACA_IRQ_DEC 0 1004 1005masked_interrupt_book3e_0x280: 1006masked_interrupt_book3e_0x2c0: 1007 masked_interrupt_book3e PACA_IRQ_DBELL 0 1008 1009/* 1010 * Called from arch_local_irq_enable when an interrupt needs 1011 * to be resent. r3 contains either 0x500,0x900,0x260 or 0x280 1012 * to indicate the kind of interrupt. MSR:EE is already off. 1013 * We generate a stackframe like if a real interrupt had happened. 1014 * 1015 * Note: While MSR:EE is off, we need to make sure that _MSR 1016 * in the generated frame has EE set to 1 or the exception 1017 * handler will not properly re-enable them. 1018 */ 1019_GLOBAL(__replay_interrupt) 1020 /* We are going to jump to the exception common code which 1021 * will retrieve various register values from the PACA which 1022 * we don't give a damn about. 1023 */ 1024 mflr r10 1025 mfmsr r11 1026 mfcr r4 1027 mtspr SPRN_SPRG_GEN_SCRATCH,r13; 1028 std r1,PACA_EXGEN+EX_R1(r13); 1029 stw r4,PACA_EXGEN+EX_CR(r13); 1030 ori r11,r11,MSR_EE 1031 subi r1,r1,INT_FRAME_SIZE; 1032 cmpwi cr0,r3,0x500 1033 beq exc_0x500_common 1034 cmpwi cr0,r3,0x900 1035 beq exc_0x900_common 1036 cmpwi cr0,r3,0x280 1037 beq exc_0x280_common 1038 blr 1039 1040 1041/* 1042 * This is called from 0x300 and 0x400 handlers after the prologs with 1043 * r14 and r15 containing the fault address and error code, with the 1044 * original values stashed away in the PACA 1045 */ 1046storage_fault_common: 1047 std r14,_DAR(r1) 1048 std r15,_DSISR(r1) 1049 addi r3,r1,STACK_FRAME_OVERHEAD 1050 mr r4,r14 1051 mr r5,r15 1052 ld r14,PACA_EXGEN+EX_R14(r13) 1053 ld r15,PACA_EXGEN+EX_R15(r13) 1054 bl do_page_fault 1055 cmpdi r3,0 1056 bne- 1f 1057 b ret_from_except_lite 10581: bl save_nvgprs 1059 mr r5,r3 1060 addi r3,r1,STACK_FRAME_OVERHEAD 1061 ld r4,_DAR(r1) 1062 bl bad_page_fault 1063 b ret_from_except 1064 1065/* 1066 * Alignment exception doesn't fit entirely in the 0x100 bytes so it 1067 * continues here. 1068 */ 1069alignment_more: 1070 std r14,_DAR(r1) 1071 std r15,_DSISR(r1) 1072 addi r3,r1,STACK_FRAME_OVERHEAD 1073 ld r14,PACA_EXGEN+EX_R14(r13) 1074 ld r15,PACA_EXGEN+EX_R15(r13) 1075 bl save_nvgprs 1076 INTS_RESTORE_HARD 1077 bl alignment_exception 1078 b ret_from_except 1079 1080/* 1081 * We branch here from entry_64.S for the last stage of the exception 1082 * return code path. MSR:EE is expected to be off at that point 1083 */ 1084_GLOBAL(exception_return_book3e) 1085 b 1f 1086 1087/* This is the return from load_up_fpu fast path which could do with 1088 * less GPR restores in fact, but for now we have a single return path 1089 */ 1090 .globl fast_exception_return 1091fast_exception_return: 1092 wrteei 0 10931: mr r0,r13 1094 ld r10,_MSR(r1) 1095 REST_4GPRS(2, r1) 1096 andi. r6,r10,MSR_PR 1097 REST_2GPRS(6, r1) 1098 beq 1f 1099 ACCOUNT_CPU_USER_EXIT(r13, r10, r11) 1100 ld r0,GPR13(r1) 1101 11021: stdcx. r0,0,r1 /* to clear the reservation */ 1103 1104 ld r8,_CCR(r1) 1105 ld r9,_LINK(r1) 1106 ld r10,_CTR(r1) 1107 ld r11,_XER(r1) 1108 mtcr r8 1109 mtlr r9 1110 mtctr r10 1111 mtxer r11 1112 REST_2GPRS(8, r1) 1113 ld r10,GPR10(r1) 1114 ld r11,GPR11(r1) 1115 ld r12,GPR12(r1) 1116 mtspr SPRN_SPRG_GEN_SCRATCH,r0 1117 1118 std r10,PACA_EXGEN+EX_R10(r13); 1119 std r11,PACA_EXGEN+EX_R11(r13); 1120 ld r10,_NIP(r1) 1121 ld r11,_MSR(r1) 1122 ld r0,GPR0(r1) 1123 ld r1,GPR1(r1) 1124 mtspr SPRN_SRR0,r10 1125 mtspr SPRN_SRR1,r11 1126 ld r10,PACA_EXGEN+EX_R10(r13) 1127 ld r11,PACA_EXGEN+EX_R11(r13) 1128 mfspr r13,SPRN_SPRG_GEN_SCRATCH 1129 rfi 1130 1131/* 1132 * Trampolines used when spotting a bad kernel stack pointer in 1133 * the exception entry code. 1134 * 1135 * TODO: move some bits like SRR0 read to trampoline, pass PACA 1136 * index around, etc... to handle crit & mcheck 1137 */ 1138BAD_STACK_TRAMPOLINE(0x000) 1139BAD_STACK_TRAMPOLINE(0x100) 1140BAD_STACK_TRAMPOLINE(0x200) 1141BAD_STACK_TRAMPOLINE(0x220) 1142BAD_STACK_TRAMPOLINE(0x260) 1143BAD_STACK_TRAMPOLINE(0x280) 1144BAD_STACK_TRAMPOLINE(0x2a0) 1145BAD_STACK_TRAMPOLINE(0x2c0) 1146BAD_STACK_TRAMPOLINE(0x2e0) 1147BAD_STACK_TRAMPOLINE(0x300) 1148BAD_STACK_TRAMPOLINE(0x310) 1149BAD_STACK_TRAMPOLINE(0x320) 1150BAD_STACK_TRAMPOLINE(0x340) 1151BAD_STACK_TRAMPOLINE(0x400) 1152BAD_STACK_TRAMPOLINE(0x500) 1153BAD_STACK_TRAMPOLINE(0x600) 1154BAD_STACK_TRAMPOLINE(0x700) 1155BAD_STACK_TRAMPOLINE(0x800) 1156BAD_STACK_TRAMPOLINE(0x900) 1157BAD_STACK_TRAMPOLINE(0x980) 1158BAD_STACK_TRAMPOLINE(0x9f0) 1159BAD_STACK_TRAMPOLINE(0xa00) 1160BAD_STACK_TRAMPOLINE(0xb00) 1161BAD_STACK_TRAMPOLINE(0xc00) 1162BAD_STACK_TRAMPOLINE(0xd00) 1163BAD_STACK_TRAMPOLINE(0xd08) 1164BAD_STACK_TRAMPOLINE(0xe00) 1165BAD_STACK_TRAMPOLINE(0xf00) 1166BAD_STACK_TRAMPOLINE(0xf20) 1167 1168 .globl bad_stack_book3e 1169bad_stack_book3e: 1170 /* XXX: Needs to make SPRN_SPRG_GEN depend on exception type */ 1171 mfspr r10,SPRN_SRR0; /* read SRR0 before touching stack */ 1172 ld r1,PACAEMERGSP(r13) 1173 subi r1,r1,64+INT_FRAME_SIZE 1174 std r10,_NIP(r1) 1175 std r11,_MSR(r1) 1176 ld r10,PACA_EXGEN+EX_R1(r13) /* FIXME for crit & mcheck */ 1177 lwz r11,PACA_EXGEN+EX_CR(r13) /* FIXME for crit & mcheck */ 1178 std r10,GPR1(r1) 1179 std r11,_CCR(r1) 1180 mfspr r10,SPRN_DEAR 1181 mfspr r11,SPRN_ESR 1182 std r10,_DAR(r1) 1183 std r11,_DSISR(r1) 1184 std r0,GPR0(r1); /* save r0 in stackframe */ \ 1185 std r2,GPR2(r1); /* save r2 in stackframe */ \ 1186 SAVE_4GPRS(3, r1); /* save r3 - r6 in stackframe */ \ 1187 SAVE_2GPRS(7, r1); /* save r7, r8 in stackframe */ \ 1188 std r9,GPR9(r1); /* save r9 in stackframe */ \ 1189 ld r3,PACA_EXGEN+EX_R10(r13);/* get back r10 */ \ 1190 ld r4,PACA_EXGEN+EX_R11(r13);/* get back r11 */ \ 1191 mfspr r5,SPRN_SPRG_GEN_SCRATCH;/* get back r13 XXX can be wrong */ \ 1192 std r3,GPR10(r1); /* save r10 to stackframe */ \ 1193 std r4,GPR11(r1); /* save r11 to stackframe */ \ 1194 std r12,GPR12(r1); /* save r12 in stackframe */ \ 1195 std r5,GPR13(r1); /* save it to stackframe */ \ 1196 mflr r10 1197 mfctr r11 1198 mfxer r12 1199 std r10,_LINK(r1) 1200 std r11,_CTR(r1) 1201 std r12,_XER(r1) 1202 SAVE_10GPRS(14,r1) 1203 SAVE_8GPRS(24,r1) 1204 lhz r12,PACA_TRAP_SAVE(r13) 1205 std r12,_TRAP(r1) 1206 addi r11,r1,INT_FRAME_SIZE 1207 std r11,0(r1) 1208 li r12,0 1209 std r12,0(r11) 1210 ld r2,PACATOC(r13) 12111: addi r3,r1,STACK_FRAME_OVERHEAD 1212 bl kernel_bad_stack 1213 b 1b 1214 1215/* 1216 * Setup the initial TLB for a core. This current implementation 1217 * assume that whatever we are running off will not conflict with 1218 * the new mapping at PAGE_OFFSET. 1219 */ 1220_GLOBAL(initial_tlb_book3e) 1221 1222 /* Look for the first TLB with IPROT set */ 1223 mfspr r4,SPRN_TLB0CFG 1224 andi. r3,r4,TLBnCFG_IPROT 1225 lis r3,MAS0_TLBSEL(0)@h 1226 bne found_iprot 1227 1228 mfspr r4,SPRN_TLB1CFG 1229 andi. r3,r4,TLBnCFG_IPROT 1230 lis r3,MAS0_TLBSEL(1)@h 1231 bne found_iprot 1232 1233 mfspr r4,SPRN_TLB2CFG 1234 andi. r3,r4,TLBnCFG_IPROT 1235 lis r3,MAS0_TLBSEL(2)@h 1236 bne found_iprot 1237 1238 lis r3,MAS0_TLBSEL(3)@h 1239 mfspr r4,SPRN_TLB3CFG 1240 /* fall through */ 1241 1242found_iprot: 1243 andi. r5,r4,TLBnCFG_HES 1244 bne have_hes 1245 1246 mflr r8 /* save LR */ 1247/* 1. Find the index of the entry we're executing in 1248 * 1249 * r3 = MAS0_TLBSEL (for the iprot array) 1250 * r4 = SPRN_TLBnCFG 1251 */ 1252 bl invstr /* Find our address */ 1253invstr: mflr r6 /* Make it accessible */ 1254 mfmsr r7 1255 rlwinm r5,r7,27,31,31 /* extract MSR[IS] */ 1256 mfspr r7,SPRN_PID 1257 slwi r7,r7,16 1258 or r7,r7,r5 1259 mtspr SPRN_MAS6,r7 1260 tlbsx 0,r6 /* search MSR[IS], SPID=PID */ 1261 1262 mfspr r3,SPRN_MAS0 1263 rlwinm r5,r3,16,20,31 /* Extract MAS0(Entry) */ 1264 1265 mfspr r7,SPRN_MAS1 /* Insure IPROT set */ 1266 oris r7,r7,MAS1_IPROT@h 1267 mtspr SPRN_MAS1,r7 1268 tlbwe 1269 1270/* 2. Invalidate all entries except the entry we're executing in 1271 * 1272 * r3 = MAS0 w/TLBSEL & ESEL for the entry we are running in 1273 * r4 = SPRN_TLBnCFG 1274 * r5 = ESEL of entry we are running in 1275 */ 1276 andi. r4,r4,TLBnCFG_N_ENTRY /* Extract # entries */ 1277 li r6,0 /* Set Entry counter to 0 */ 12781: mr r7,r3 /* Set MAS0(TLBSEL) */ 1279 rlwimi r7,r6,16,4,15 /* Setup MAS0 = TLBSEL | ESEL(r6) */ 1280 mtspr SPRN_MAS0,r7 1281 tlbre 1282 mfspr r7,SPRN_MAS1 1283 rlwinm r7,r7,0,2,31 /* Clear MAS1 Valid and IPROT */ 1284 cmpw r5,r6 1285 beq skpinv /* Dont update the current execution TLB */ 1286 mtspr SPRN_MAS1,r7 1287 tlbwe 1288 isync 1289skpinv: addi r6,r6,1 /* Increment */ 1290 cmpw r6,r4 /* Are we done? */ 1291 bne 1b /* If not, repeat */ 1292 1293 /* Invalidate all TLBs */ 1294 PPC_TLBILX_ALL(0,R0) 1295 sync 1296 isync 1297 1298/* 3. Setup a temp mapping and jump to it 1299 * 1300 * r3 = MAS0 w/TLBSEL & ESEL for the entry we are running in 1301 * r5 = ESEL of entry we are running in 1302 */ 1303 andi. r7,r5,0x1 /* Find an entry not used and is non-zero */ 1304 addi r7,r7,0x1 1305 mr r4,r3 /* Set MAS0(TLBSEL) = 1 */ 1306 mtspr SPRN_MAS0,r4 1307 tlbre 1308 1309 rlwimi r4,r7,16,4,15 /* Setup MAS0 = TLBSEL | ESEL(r7) */ 1310 mtspr SPRN_MAS0,r4 1311 1312 mfspr r7,SPRN_MAS1 1313 xori r6,r7,MAS1_TS /* Setup TMP mapping in the other Address space */ 1314 mtspr SPRN_MAS1,r6 1315 1316 tlbwe 1317 1318 mfmsr r6 1319 xori r6,r6,MSR_IS 1320 mtspr SPRN_SRR1,r6 1321 bl 1f /* Find our address */ 13221: mflr r6 1323 addi r6,r6,(2f - 1b) 1324 mtspr SPRN_SRR0,r6 1325 rfi 13262: 1327 1328/* 4. Clear out PIDs & Search info 1329 * 1330 * r3 = MAS0 w/TLBSEL & ESEL for the entry we started in 1331 * r4 = MAS0 w/TLBSEL & ESEL for the temp mapping 1332 * r5 = MAS3 1333 */ 1334 li r6,0 1335 mtspr SPRN_MAS6,r6 1336 mtspr SPRN_PID,r6 1337 1338/* 5. Invalidate mapping we started in 1339 * 1340 * r3 = MAS0 w/TLBSEL & ESEL for the entry we started in 1341 * r4 = MAS0 w/TLBSEL & ESEL for the temp mapping 1342 * r5 = MAS3 1343 */ 1344 mtspr SPRN_MAS0,r3 1345 tlbre 1346 mfspr r6,SPRN_MAS1 1347 rlwinm r6,r6,0,2,31 /* clear IPROT and VALID */ 1348 mtspr SPRN_MAS1,r6 1349 tlbwe 1350 sync 1351 isync 1352 1353/* 1354 * The mapping only needs to be cache-coherent on SMP, except on 1355 * Freescale e500mc derivatives where it's also needed for coherent DMA. 1356 */ 1357#if defined(CONFIG_SMP) || defined(CONFIG_PPC_E500MC) 1358#define M_IF_NEEDED MAS2_M 1359#else 1360#define M_IF_NEEDED 0 1361#endif 1362 1363/* 6. Setup KERNELBASE mapping in TLB[0] 1364 * 1365 * r3 = MAS0 w/TLBSEL & ESEL for the entry we started in 1366 * r4 = MAS0 w/TLBSEL & ESEL for the temp mapping 1367 * r5 = MAS3 1368 */ 1369 rlwinm r3,r3,0,16,3 /* clear ESEL */ 1370 mtspr SPRN_MAS0,r3 1371 lis r6,(MAS1_VALID|MAS1_IPROT)@h 1372 ori r6,r6,(MAS1_TSIZE(BOOK3E_PAGESZ_1GB))@l 1373 mtspr SPRN_MAS1,r6 1374 1375 LOAD_REG_IMMEDIATE(r6, PAGE_OFFSET | M_IF_NEEDED) 1376 mtspr SPRN_MAS2,r6 1377 1378 rlwinm r5,r5,0,0,25 1379 ori r5,r5,MAS3_SR | MAS3_SW | MAS3_SX 1380 mtspr SPRN_MAS3,r5 1381 li r5,-1 1382 rlwinm r5,r5,0,0,25 1383 1384 tlbwe 1385 1386/* 7. Jump to KERNELBASE mapping 1387 * 1388 * r4 = MAS0 w/TLBSEL & ESEL for the temp mapping 1389 */ 1390 /* Now we branch the new virtual address mapped by this entry */ 1391 bl 1f /* Find our address */ 13921: mflr r6 1393 addi r6,r6,(2f - 1b) 1394 tovirt(r6,r6) 1395 lis r7,MSR_KERNEL@h 1396 ori r7,r7,MSR_KERNEL@l 1397 mtspr SPRN_SRR0,r6 1398 mtspr SPRN_SRR1,r7 1399 rfi /* start execution out of TLB1[0] entry */ 14002: 1401 1402/* 8. Clear out the temp mapping 1403 * 1404 * r4 = MAS0 w/TLBSEL & ESEL for the entry we are running in 1405 */ 1406 mtspr SPRN_MAS0,r4 1407 tlbre 1408 mfspr r5,SPRN_MAS1 1409 rlwinm r5,r5,0,2,31 /* clear IPROT and VALID */ 1410 mtspr SPRN_MAS1,r5 1411 tlbwe 1412 sync 1413 isync 1414 1415 /* We translate LR and return */ 1416 tovirt(r8,r8) 1417 mtlr r8 1418 blr 1419 1420have_hes: 1421 /* Setup MAS 0,1,2,3 and 7 for tlbwe of a 1G entry that maps the 1422 * kernel linear mapping. We also set MAS8 once for all here though 1423 * that will have to be made dependent on whether we are running under 1424 * a hypervisor I suppose. 1425 */ 1426 1427 /* BEWARE, MAGIC 1428 * This code is called as an ordinary function on the boot CPU. But to 1429 * avoid duplication, this code is also used in SCOM bringup of 1430 * secondary CPUs. We read the code between the initial_tlb_code_start 1431 * and initial_tlb_code_end labels one instruction at a time and RAM it 1432 * into the new core via SCOM. That doesn't process branches, so there 1433 * must be none between those two labels. It also means if this code 1434 * ever takes any parameters, the SCOM code must also be updated to 1435 * provide them. 1436 */ 1437 .globl a2_tlbinit_code_start 1438a2_tlbinit_code_start: 1439 1440 ori r11,r3,MAS0_WQ_ALLWAYS 1441 oris r11,r11,MAS0_ESEL(3)@h /* Use way 3: workaround A2 erratum 376 */ 1442 mtspr SPRN_MAS0,r11 1443 lis r3,(MAS1_VALID | MAS1_IPROT)@h 1444 ori r3,r3,BOOK3E_PAGESZ_1GB << MAS1_TSIZE_SHIFT 1445 mtspr SPRN_MAS1,r3 1446 LOAD_REG_IMMEDIATE(r3, PAGE_OFFSET | MAS2_M) 1447 mtspr SPRN_MAS2,r3 1448 li r3,MAS3_SR | MAS3_SW | MAS3_SX 1449 mtspr SPRN_MAS7_MAS3,r3 1450 li r3,0 1451 mtspr SPRN_MAS8,r3 1452 1453 /* Write the TLB entry */ 1454 tlbwe 1455 1456 .globl a2_tlbinit_after_linear_map 1457a2_tlbinit_after_linear_map: 1458 1459 /* Now we branch the new virtual address mapped by this entry */ 1460 LOAD_REG_IMMEDIATE(r3,1f) 1461 mtctr r3 1462 bctr 1463 14641: /* We are now running at PAGE_OFFSET, clean the TLB of everything 1465 * else (including IPROTed things left by firmware) 1466 * r4 = TLBnCFG 1467 * r3 = current address (more or less) 1468 */ 1469 1470 li r5,0 1471 mtspr SPRN_MAS6,r5 1472 tlbsx 0,r3 1473 1474 rlwinm r9,r4,0,TLBnCFG_N_ENTRY 1475 rlwinm r10,r4,8,0xff 1476 addi r10,r10,-1 /* Get inner loop mask */ 1477 1478 li r3,1 1479 1480 mfspr r5,SPRN_MAS1 1481 rlwinm r5,r5,0,(~(MAS1_VALID|MAS1_IPROT)) 1482 1483 mfspr r6,SPRN_MAS2 1484 rldicr r6,r6,0,51 /* Extract EPN */ 1485 1486 mfspr r7,SPRN_MAS0 1487 rlwinm r7,r7,0,0xffff0fff /* Clear HES and WQ */ 1488 1489 rlwinm r8,r7,16,0xfff /* Extract ESEL */ 1490 14912: add r4,r3,r8 1492 and r4,r4,r10 1493 1494 rlwimi r7,r4,16,MAS0_ESEL_MASK 1495 1496 mtspr SPRN_MAS0,r7 1497 mtspr SPRN_MAS1,r5 1498 mtspr SPRN_MAS2,r6 1499 tlbwe 1500 1501 addi r3,r3,1 1502 and. r4,r3,r10 1503 1504 bne 3f 1505 addis r6,r6,(1<<30)@h 15063: 1507 cmpw r3,r9 1508 blt 2b 1509 1510 .globl a2_tlbinit_after_iprot_flush 1511a2_tlbinit_after_iprot_flush: 1512 1513 PPC_TLBILX(0,0,R0) 1514 sync 1515 isync 1516 1517 .globl a2_tlbinit_code_end 1518a2_tlbinit_code_end: 1519 1520 /* We translate LR and return */ 1521 mflr r3 1522 tovirt(r3,r3) 1523 mtlr r3 1524 blr 1525 1526/* 1527 * Main entry (boot CPU, thread 0) 1528 * 1529 * We enter here from head_64.S, possibly after the prom_init trampoline 1530 * with r3 and r4 already saved to r31 and 30 respectively and in 64 bits 1531 * mode. Anything else is as it was left by the bootloader 1532 * 1533 * Initial requirements of this port: 1534 * 1535 * - Kernel loaded at 0 physical 1536 * - A good lump of memory mapped 0:0 by UTLB entry 0 1537 * - MSR:IS & MSR:DS set to 0 1538 * 1539 * Note that some of the above requirements will be relaxed in the future 1540 * as the kernel becomes smarter at dealing with different initial conditions 1541 * but for now you have to be careful 1542 */ 1543_GLOBAL(start_initialization_book3e) 1544 mflr r28 1545 1546 /* First, we need to setup some initial TLBs to map the kernel 1547 * text, data and bss at PAGE_OFFSET. We don't have a real mode 1548 * and always use AS 0, so we just set it up to match our link 1549 * address and never use 0 based addresses. 1550 */ 1551 bl initial_tlb_book3e 1552 1553 /* Init global core bits */ 1554 bl init_core_book3e 1555 1556 /* Init per-thread bits */ 1557 bl init_thread_book3e 1558 1559 /* Return to common init code */ 1560 tovirt(r28,r28) 1561 mtlr r28 1562 blr 1563 1564 1565/* 1566 * Secondary core/processor entry 1567 * 1568 * This is entered for thread 0 of a secondary core, all other threads 1569 * are expected to be stopped. It's similar to start_initialization_book3e 1570 * except that it's generally entered from the holding loop in head_64.S 1571 * after CPUs have been gathered by Open Firmware. 1572 * 1573 * We assume we are in 32 bits mode running with whatever TLB entry was 1574 * set for us by the firmware or POR engine. 1575 */ 1576_GLOBAL(book3e_secondary_core_init_tlb_set) 1577 li r4,1 1578 b generic_secondary_smp_init 1579 1580_GLOBAL(book3e_secondary_core_init) 1581 mflr r28 1582 1583 /* Do we need to setup initial TLB entry ? */ 1584 cmplwi r4,0 1585 bne 2f 1586 1587 /* Setup TLB for this core */ 1588 bl initial_tlb_book3e 1589 1590 /* We can return from the above running at a different 1591 * address, so recalculate r2 (TOC) 1592 */ 1593 bl relative_toc 1594 1595 /* Init global core bits */ 15962: bl init_core_book3e 1597 1598 /* Init per-thread bits */ 15993: bl init_thread_book3e 1600 1601 /* Return to common init code at proper virtual address. 1602 * 1603 * Due to various previous assumptions, we know we entered this 1604 * function at either the final PAGE_OFFSET mapping or using a 1605 * 1:1 mapping at 0, so we don't bother doing a complicated check 1606 * here, we just ensure the return address has the right top bits. 1607 * 1608 * Note that if we ever want to be smarter about where we can be 1609 * started from, we have to be careful that by the time we reach 1610 * the code below we may already be running at a different location 1611 * than the one we were called from since initial_tlb_book3e can 1612 * have moved us already. 1613 */ 1614 cmpdi cr0,r28,0 1615 blt 1f 1616 lis r3,PAGE_OFFSET@highest 1617 sldi r3,r3,32 1618 or r28,r28,r3 16191: mtlr r28 1620 blr 1621 1622_GLOBAL(book3e_secondary_thread_init) 1623 mflr r28 1624 b 3b 1625 1626 .globl init_core_book3e 1627init_core_book3e: 1628 /* Establish the interrupt vector base */ 1629 tovirt(r2,r2) 1630 LOAD_REG_ADDR(r3, interrupt_base_book3e) 1631 mtspr SPRN_IVPR,r3 1632 sync 1633 blr 1634 1635init_thread_book3e: 1636 lis r3,(SPRN_EPCR_ICM | SPRN_EPCR_GICM)@h 1637 mtspr SPRN_EPCR,r3 1638 1639 /* Make sure interrupts are off */ 1640 wrteei 0 1641 1642 /* disable all timers and clear out status */ 1643 li r3,0 1644 mtspr SPRN_TCR,r3 1645 mfspr r3,SPRN_TSR 1646 mtspr SPRN_TSR,r3 1647 1648 blr 1649 1650_GLOBAL(__setup_base_ivors) 1651 SET_IVOR(0, 0x020) /* Critical Input */ 1652 SET_IVOR(1, 0x000) /* Machine Check */ 1653 SET_IVOR(2, 0x060) /* Data Storage */ 1654 SET_IVOR(3, 0x080) /* Instruction Storage */ 1655 SET_IVOR(4, 0x0a0) /* External Input */ 1656 SET_IVOR(5, 0x0c0) /* Alignment */ 1657 SET_IVOR(6, 0x0e0) /* Program */ 1658 SET_IVOR(7, 0x100) /* FP Unavailable */ 1659 SET_IVOR(8, 0x120) /* System Call */ 1660 SET_IVOR(9, 0x140) /* Auxiliary Processor Unavailable */ 1661 SET_IVOR(10, 0x160) /* Decrementer */ 1662 SET_IVOR(11, 0x180) /* Fixed Interval Timer */ 1663 SET_IVOR(12, 0x1a0) /* Watchdog Timer */ 1664 SET_IVOR(13, 0x1c0) /* Data TLB Error */ 1665 SET_IVOR(14, 0x1e0) /* Instruction TLB Error */ 1666 SET_IVOR(15, 0x040) /* Debug */ 1667 1668 sync 1669 1670 blr 1671 1672_GLOBAL(setup_altivec_ivors) 1673 SET_IVOR(32, 0x200) /* AltiVec Unavailable */ 1674 SET_IVOR(33, 0x220) /* AltiVec Assist */ 1675 blr 1676 1677_GLOBAL(setup_perfmon_ivor) 1678 SET_IVOR(35, 0x260) /* Performance Monitor */ 1679 blr 1680 1681_GLOBAL(setup_doorbell_ivors) 1682 SET_IVOR(36, 0x280) /* Processor Doorbell */ 1683 SET_IVOR(37, 0x2a0) /* Processor Doorbell Crit */ 1684 blr 1685 1686_GLOBAL(setup_ehv_ivors) 1687 SET_IVOR(40, 0x300) /* Embedded Hypervisor System Call */ 1688 SET_IVOR(41, 0x320) /* Embedded Hypervisor Privilege */ 1689 SET_IVOR(38, 0x2c0) /* Guest Processor Doorbell */ 1690 SET_IVOR(39, 0x2e0) /* Guest Processor Doorbell Crit/MC */ 1691 blr 1692 1693_GLOBAL(setup_lrat_ivor) 1694 SET_IVOR(42, 0x340) /* LRAT Error */ 1695 blr 1696