1/* SPDX-License-Identifier: GPL-2.0 */ 2/* 3 * This file contains the 64-bit "server" PowerPC variant 4 * of the low level exception handling including exception 5 * vectors, exception return, part of the slb and stab 6 * handling and other fixed offset specific things. 7 * 8 * This file is meant to be #included from head_64.S due to 9 * position dependent assembly. 10 * 11 * Most of this originates from head_64.S and thus has the same 12 * copyright history. 13 * 14 */ 15 16#include <asm/hw_irq.h> 17#include <asm/exception-64s.h> 18#include <asm/ptrace.h> 19#include <asm/cpuidle.h> 20#include <asm/head-64.h> 21 22/* 23 * There are a few constraints to be concerned with. 24 * - Real mode exceptions code/data must be located at their physical location. 25 * - Virtual mode exceptions must be mapped at their 0xc000... location. 26 * - Fixed location code must not call directly beyond the __end_interrupts 27 * area when built with CONFIG_RELOCATABLE. LOAD_HANDLER / bctr sequence 28 * must be used. 29 * - LOAD_HANDLER targets must be within first 64K of physical 0 / 30 * virtual 0xc00... 31 * - Conditional branch targets must be within +/-32K of caller. 32 * 33 * "Virtual exceptions" run with relocation on (MSR_IR=1, MSR_DR=1), and 34 * therefore don't have to run in physically located code or rfid to 35 * virtual mode kernel code. However on relocatable kernels they do have 36 * to branch to KERNELBASE offset because the rest of the kernel (outside 37 * the exception vectors) may be located elsewhere. 38 * 39 * Virtual exceptions correspond with physical, except their entry points 40 * are offset by 0xc000000000000000 and also tend to get an added 0x4000 41 * offset applied. Virtual exceptions are enabled with the Alternate 42 * Interrupt Location (AIL) bit set in the LPCR. However this does not 43 * guarantee they will be delivered virtually. Some conditions (see the ISA) 44 * cause exceptions to be delivered in real mode. 45 * 46 * It's impossible to receive interrupts below 0x300 via AIL. 47 * 48 * KVM: None of the virtual exceptions are from the guest. Anything that 49 * escalated to HV=1 from HV=0 is delivered via real mode handlers. 50 * 51 * 52 * We layout physical memory as follows: 53 * 0x0000 - 0x00ff : Secondary processor spin code 54 * 0x0100 - 0x18ff : Real mode pSeries interrupt vectors 55 * 0x1900 - 0x3fff : Real mode trampolines 56 * 0x4000 - 0x58ff : Relon (IR=1,DR=1) mode pSeries interrupt vectors 57 * 0x5900 - 0x6fff : Relon mode trampolines 58 * 0x7000 - 0x7fff : FWNMI data area 59 * 0x8000 - .... : Common interrupt handlers, remaining early 60 * setup code, rest of kernel. 61 * 62 * We could reclaim 0x4000-0x42ff for real mode trampolines if the space 63 * is necessary. Until then it's more consistent to explicitly put VIRT_NONE 64 * vectors there. 65 */ 66OPEN_FIXED_SECTION(real_vectors, 0x0100, 0x1900) 67OPEN_FIXED_SECTION(real_trampolines, 0x1900, 0x4000) 68OPEN_FIXED_SECTION(virt_vectors, 0x4000, 0x5900) 69OPEN_FIXED_SECTION(virt_trampolines, 0x5900, 0x7000) 70#if defined(CONFIG_PPC_PSERIES) || defined(CONFIG_PPC_POWERNV) 71/* 72 * Data area reserved for FWNMI option. 73 * This address (0x7000) is fixed by the RPA. 74 * pseries and powernv need to keep the whole page from 75 * 0x7000 to 0x8000 free for use by the firmware 76 */ 77ZERO_FIXED_SECTION(fwnmi_page, 0x7000, 0x8000) 78OPEN_TEXT_SECTION(0x8000) 79#else 80OPEN_TEXT_SECTION(0x7000) 81#endif 82 83USE_FIXED_SECTION(real_vectors) 84 85/* 86 * This is the start of the interrupt handlers for pSeries 87 * This code runs with relocation off. 88 * Code from here to __end_interrupts gets copied down to real 89 * address 0x100 when we are running a relocatable kernel. 90 * Therefore any relative branches in this section must only 91 * branch to labels in this section. 92 */ 93 .globl __start_interrupts 94__start_interrupts: 95 96/* No virt vectors corresponding with 0x0..0x100 */ 97EXC_VIRT_NONE(0x4000, 0x100) 98 99 100#ifdef CONFIG_PPC_P7_NAP 101 /* 102 * If running native on arch 2.06 or later, check if we are waking up 103 * from nap/sleep/winkle, and branch to idle handler. This tests SRR1 104 * bits 46:47. A non-0 value indicates that we are coming from a power 105 * saving state. The idle wakeup handler initially runs in real mode, 106 * but we branch to the 0xc000... address so we can turn on relocation 107 * with mtmsr. 108 */ 109#define IDLETEST(n) \ 110 BEGIN_FTR_SECTION ; \ 111 mfspr r10,SPRN_SRR1 ; \ 112 rlwinm. r10,r10,47-31,30,31 ; \ 113 beq- 1f ; \ 114 cmpwi cr3,r10,2 ; \ 115 BRANCH_TO_C000(r10, system_reset_idle_common) ; \ 1161: \ 117 END_FTR_SECTION_IFSET(CPU_FTR_HVMODE | CPU_FTR_ARCH_206) 118#else 119#define IDLETEST NOTEST 120#endif 121 122EXC_REAL_BEGIN(system_reset, 0x100, 0x100) 123 SET_SCRATCH0(r13) 124 /* 125 * MSR_RI is not enabled, because PACA_EXNMI and nmi stack is 126 * being used, so a nested NMI exception would corrupt it. 127 */ 128 EXCEPTION_PROLOG_PSERIES_NORI(PACA_EXNMI, system_reset_common, EXC_STD, 129 IDLETEST, 0x100) 130 131EXC_REAL_END(system_reset, 0x100, 0x100) 132EXC_VIRT_NONE(0x4100, 0x100) 133 134#ifdef CONFIG_PPC_P7_NAP 135EXC_COMMON_BEGIN(system_reset_idle_common) 136 mfspr r12,SPRN_SRR1 137 b pnv_powersave_wakeup 138#endif 139 140EXC_COMMON_BEGIN(system_reset_common) 141 /* 142 * Increment paca->in_nmi then enable MSR_RI. SLB or MCE will be able 143 * to recover, but nested NMI will notice in_nmi and not recover 144 * because of the use of the NMI stack. in_nmi reentrancy is tested in 145 * system_reset_exception. 146 */ 147 lhz r10,PACA_IN_NMI(r13) 148 addi r10,r10,1 149 sth r10,PACA_IN_NMI(r13) 150 li r10,MSR_RI 151 mtmsrd r10,1 152 153 mr r10,r1 154 ld r1,PACA_NMI_EMERG_SP(r13) 155 subi r1,r1,INT_FRAME_SIZE 156 EXCEPTION_COMMON_NORET_STACK(PACA_EXNMI, 0x100, 157 system_reset, system_reset_exception, 158 ADD_NVGPRS;ADD_RECONCILE) 159 160 /* 161 * The stack is no longer in use, decrement in_nmi. 162 */ 163 lhz r10,PACA_IN_NMI(r13) 164 subi r10,r10,1 165 sth r10,PACA_IN_NMI(r13) 166 167 b ret_from_except 168 169#ifdef CONFIG_PPC_PSERIES 170/* 171 * Vectors for the FWNMI option. Share common code. 172 */ 173TRAMP_REAL_BEGIN(system_reset_fwnmi) 174 SET_SCRATCH0(r13) /* save r13 */ 175 /* See comment at system_reset exception */ 176 EXCEPTION_PROLOG_PSERIES_NORI(PACA_EXNMI, system_reset_common, 177 EXC_STD, NOTEST, 0x100) 178#endif /* CONFIG_PPC_PSERIES */ 179 180 181EXC_REAL_BEGIN(machine_check, 0x200, 0x100) 182 /* This is moved out of line as it can be patched by FW, but 183 * some code path might still want to branch into the original 184 * vector 185 */ 186 SET_SCRATCH0(r13) /* save r13 */ 187 EXCEPTION_PROLOG_0(PACA_EXMC) 188BEGIN_FTR_SECTION 189 b machine_check_powernv_early 190FTR_SECTION_ELSE 191 b machine_check_pSeries_0 192ALT_FTR_SECTION_END_IFSET(CPU_FTR_HVMODE) 193EXC_REAL_END(machine_check, 0x200, 0x100) 194EXC_VIRT_NONE(0x4200, 0x100) 195TRAMP_REAL_BEGIN(machine_check_powernv_early) 196BEGIN_FTR_SECTION 197 EXCEPTION_PROLOG_1(PACA_EXMC, NOTEST, 0x200) 198 /* 199 * Register contents: 200 * R13 = PACA 201 * R9 = CR 202 * Original R9 to R13 is saved on PACA_EXMC 203 * 204 * Switch to mc_emergency stack and handle re-entrancy (we limit 205 * the nested MCE upto level 4 to avoid stack overflow). 206 * Save MCE registers srr1, srr0, dar and dsisr and then set ME=1 207 * 208 * We use paca->in_mce to check whether this is the first entry or 209 * nested machine check. We increment paca->in_mce to track nested 210 * machine checks. 211 * 212 * If this is the first entry then set stack pointer to 213 * paca->mc_emergency_sp, otherwise r1 is already pointing to 214 * stack frame on mc_emergency stack. 215 * 216 * NOTE: We are here with MSR_ME=0 (off), which means we risk a 217 * checkstop if we get another machine check exception before we do 218 * rfid with MSR_ME=1. 219 * 220 * This interrupt can wake directly from idle. If that is the case, 221 * the machine check is handled then the idle wakeup code is called 222 * to restore state. In that case, the POWER9 DD1 idle PACA workaround 223 * is not applied in the early machine check code, which will cause 224 * bugs. 225 */ 226 mr r11,r1 /* Save r1 */ 227 lhz r10,PACA_IN_MCE(r13) 228 cmpwi r10,0 /* Are we in nested machine check */ 229 bne 0f /* Yes, we are. */ 230 /* First machine check entry */ 231 ld r1,PACAMCEMERGSP(r13) /* Use MC emergency stack */ 2320: subi r1,r1,INT_FRAME_SIZE /* alloc stack frame */ 233 addi r10,r10,1 /* increment paca->in_mce */ 234 sth r10,PACA_IN_MCE(r13) 235 /* Limit nested MCE to level 4 to avoid stack overflow */ 236 cmpwi r10,4 237 bgt 2f /* Check if we hit limit of 4 */ 238 std r11,GPR1(r1) /* Save r1 on the stack. */ 239 std r11,0(r1) /* make stack chain pointer */ 240 mfspr r11,SPRN_SRR0 /* Save SRR0 */ 241 std r11,_NIP(r1) 242 mfspr r11,SPRN_SRR1 /* Save SRR1 */ 243 std r11,_MSR(r1) 244 mfspr r11,SPRN_DAR /* Save DAR */ 245 std r11,_DAR(r1) 246 mfspr r11,SPRN_DSISR /* Save DSISR */ 247 std r11,_DSISR(r1) 248 std r9,_CCR(r1) /* Save CR in stackframe */ 249 /* Save r9 through r13 from EXMC save area to stack frame. */ 250 EXCEPTION_PROLOG_COMMON_2(PACA_EXMC) 251 mfmsr r11 /* get MSR value */ 252 ori r11,r11,MSR_ME /* turn on ME bit */ 253 ori r11,r11,MSR_RI /* turn on RI bit */ 254 LOAD_HANDLER(r12, machine_check_handle_early) 2551: mtspr SPRN_SRR0,r12 256 mtspr SPRN_SRR1,r11 257 RFI_TO_KERNEL 258 b . /* prevent speculative execution */ 2592: 260 /* Stack overflow. Stay on emergency stack and panic. 261 * Keep the ME bit off while panic-ing, so that if we hit 262 * another machine check we checkstop. 263 */ 264 addi r1,r1,INT_FRAME_SIZE /* go back to previous stack frame */ 265 ld r11,PACAKMSR(r13) 266 LOAD_HANDLER(r12, unrecover_mce) 267 li r10,MSR_ME 268 andc r11,r11,r10 /* Turn off MSR_ME */ 269 b 1b 270 b . /* prevent speculative execution */ 271END_FTR_SECTION_IFSET(CPU_FTR_HVMODE) 272 273TRAMP_REAL_BEGIN(machine_check_pSeries) 274 .globl machine_check_fwnmi 275machine_check_fwnmi: 276 SET_SCRATCH0(r13) /* save r13 */ 277 EXCEPTION_PROLOG_0(PACA_EXMC) 278machine_check_pSeries_0: 279 EXCEPTION_PROLOG_1(PACA_EXMC, KVMTEST_PR, 0x200) 280 /* 281 * MSR_RI is not enabled, because PACA_EXMC is being used, so a 282 * nested machine check corrupts it. machine_check_common enables 283 * MSR_RI. 284 */ 285 EXCEPTION_PROLOG_PSERIES_1_NORI(machine_check_common, EXC_STD) 286 287TRAMP_KVM_SKIP(PACA_EXMC, 0x200) 288 289EXC_COMMON_BEGIN(machine_check_common) 290 /* 291 * Machine check is different because we use a different 292 * save area: PACA_EXMC instead of PACA_EXGEN. 293 */ 294 mfspr r10,SPRN_DAR 295 std r10,PACA_EXMC+EX_DAR(r13) 296 mfspr r10,SPRN_DSISR 297 stw r10,PACA_EXMC+EX_DSISR(r13) 298 EXCEPTION_PROLOG_COMMON(0x200, PACA_EXMC) 299 FINISH_NAP 300 RECONCILE_IRQ_STATE(r10, r11) 301 ld r3,PACA_EXMC+EX_DAR(r13) 302 lwz r4,PACA_EXMC+EX_DSISR(r13) 303 /* Enable MSR_RI when finished with PACA_EXMC */ 304 li r10,MSR_RI 305 mtmsrd r10,1 306 std r3,_DAR(r1) 307 std r4,_DSISR(r1) 308 bl save_nvgprs 309 addi r3,r1,STACK_FRAME_OVERHEAD 310 bl machine_check_exception 311 b ret_from_except 312 313#define MACHINE_CHECK_HANDLER_WINDUP \ 314 /* Clear MSR_RI before setting SRR0 and SRR1. */\ 315 li r0,MSR_RI; \ 316 mfmsr r9; /* get MSR value */ \ 317 andc r9,r9,r0; \ 318 mtmsrd r9,1; /* Clear MSR_RI */ \ 319 /* Move original SRR0 and SRR1 into the respective regs */ \ 320 ld r9,_MSR(r1); \ 321 mtspr SPRN_SRR1,r9; \ 322 ld r3,_NIP(r1); \ 323 mtspr SPRN_SRR0,r3; \ 324 ld r9,_CTR(r1); \ 325 mtctr r9; \ 326 ld r9,_XER(r1); \ 327 mtxer r9; \ 328 ld r9,_LINK(r1); \ 329 mtlr r9; \ 330 REST_GPR(0, r1); \ 331 REST_8GPRS(2, r1); \ 332 REST_GPR(10, r1); \ 333 ld r11,_CCR(r1); \ 334 mtcr r11; \ 335 /* Decrement paca->in_mce. */ \ 336 lhz r12,PACA_IN_MCE(r13); \ 337 subi r12,r12,1; \ 338 sth r12,PACA_IN_MCE(r13); \ 339 REST_GPR(11, r1); \ 340 REST_2GPRS(12, r1); \ 341 /* restore original r1. */ \ 342 ld r1,GPR1(r1) 343 344#ifdef CONFIG_PPC_P7_NAP 345/* 346 * This is an idle wakeup. Low level machine check has already been 347 * done. Queue the event then call the idle code to do the wake up. 348 */ 349EXC_COMMON_BEGIN(machine_check_idle_common) 350 bl machine_check_queue_event 351 352 /* 353 * We have not used any non-volatile GPRs here, and as a rule 354 * most exception code including machine check does not. 355 * Therefore PACA_NAPSTATELOST does not need to be set. Idle 356 * wakeup will restore volatile registers. 357 * 358 * Load the original SRR1 into r3 for pnv_powersave_wakeup_mce. 359 * 360 * Then decrement MCE nesting after finishing with the stack. 361 */ 362 ld r3,_MSR(r1) 363 364 lhz r11,PACA_IN_MCE(r13) 365 subi r11,r11,1 366 sth r11,PACA_IN_MCE(r13) 367 368 /* Turn off the RI bit because SRR1 is used by idle wakeup code. */ 369 /* Recoverability could be improved by reducing the use of SRR1. */ 370 li r11,0 371 mtmsrd r11,1 372 373 b pnv_powersave_wakeup_mce 374#endif 375 /* 376 * Handle machine check early in real mode. We come here with 377 * ME=1, MMU (IR=0 and DR=0) off and using MC emergency stack. 378 */ 379EXC_COMMON_BEGIN(machine_check_handle_early) 380 std r0,GPR0(r1) /* Save r0 */ 381 EXCEPTION_PROLOG_COMMON_3(0x200) 382 bl save_nvgprs 383 addi r3,r1,STACK_FRAME_OVERHEAD 384 bl machine_check_early 385 std r3,RESULT(r1) /* Save result */ 386 ld r12,_MSR(r1) 387 388#ifdef CONFIG_PPC_P7_NAP 389 /* 390 * Check if thread was in power saving mode. We come here when any 391 * of the following is true: 392 * a. thread wasn't in power saving mode 393 * b. thread was in power saving mode with no state loss, 394 * supervisor state loss or hypervisor state loss. 395 * 396 * Go back to nap/sleep/winkle mode again if (b) is true. 397 */ 398 BEGIN_FTR_SECTION 399 rlwinm. r11,r12,47-31,30,31 400 bne machine_check_idle_common 401 END_FTR_SECTION_IFSET(CPU_FTR_HVMODE | CPU_FTR_ARCH_206) 402#endif 403 404 /* 405 * Check if we are coming from hypervisor userspace. If yes then we 406 * continue in host kernel in V mode to deliver the MC event. 407 */ 408 rldicl. r11,r12,4,63 /* See if MC hit while in HV mode. */ 409 beq 5f 410 andi. r11,r12,MSR_PR /* See if coming from user. */ 411 bne 9f /* continue in V mode if we are. */ 412 4135: 414#ifdef CONFIG_KVM_BOOK3S_64_HANDLER 415 /* 416 * We are coming from kernel context. Check if we are coming from 417 * guest. if yes, then we can continue. We will fall through 418 * do_kvm_200->kvmppc_interrupt to deliver the MC event to guest. 419 */ 420 lbz r11,HSTATE_IN_GUEST(r13) 421 cmpwi r11,0 /* Check if coming from guest */ 422 bne 9f /* continue if we are. */ 423#endif 424 /* 425 * At this point we are not sure about what context we come from. 426 * Queue up the MCE event and return from the interrupt. 427 * But before that, check if this is an un-recoverable exception. 428 * If yes, then stay on emergency stack and panic. 429 */ 430 andi. r11,r12,MSR_RI 431 bne 2f 4321: mfspr r11,SPRN_SRR0 433 LOAD_HANDLER(r10,unrecover_mce) 434 mtspr SPRN_SRR0,r10 435 ld r10,PACAKMSR(r13) 436 /* 437 * We are going down. But there are chances that we might get hit by 438 * another MCE during panic path and we may run into unstable state 439 * with no way out. Hence, turn ME bit off while going down, so that 440 * when another MCE is hit during panic path, system will checkstop 441 * and hypervisor will get restarted cleanly by SP. 442 */ 443 li r3,MSR_ME 444 andc r10,r10,r3 /* Turn off MSR_ME */ 445 mtspr SPRN_SRR1,r10 446 RFI_TO_KERNEL 447 b . 4482: 449 /* 450 * Check if we have successfully handled/recovered from error, if not 451 * then stay on emergency stack and panic. 452 */ 453 ld r3,RESULT(r1) /* Load result */ 454 cmpdi r3,0 /* see if we handled MCE successfully */ 455 456 beq 1b /* if !handled then panic */ 457 /* 458 * Return from MC interrupt. 459 * Queue up the MCE event so that we can log it later, while 460 * returning from kernel or opal call. 461 */ 462 bl machine_check_queue_event 463 MACHINE_CHECK_HANDLER_WINDUP 464 RFI_TO_USER_OR_KERNEL 4659: 466 /* Deliver the machine check to host kernel in V mode. */ 467BEGIN_FTR_SECTION 468 ld r10,ORIG_GPR3(r1) 469 mtspr SPRN_CFAR,r10 470END_FTR_SECTION_IFSET(CPU_FTR_CFAR) 471 MACHINE_CHECK_HANDLER_WINDUP 472 b machine_check_pSeries 473 474EXC_COMMON_BEGIN(unrecover_mce) 475 /* Invoke machine_check_exception to print MCE event and panic. */ 476 addi r3,r1,STACK_FRAME_OVERHEAD 477 bl machine_check_exception 478 /* 479 * We will not reach here. Even if we did, there is no way out. Call 480 * unrecoverable_exception and die. 481 */ 4821: addi r3,r1,STACK_FRAME_OVERHEAD 483 bl unrecoverable_exception 484 b 1b 485 486 487EXC_REAL(data_access, 0x300, 0x80) 488EXC_VIRT(data_access, 0x4300, 0x80, 0x300) 489TRAMP_KVM_SKIP(PACA_EXGEN, 0x300) 490 491EXC_COMMON_BEGIN(data_access_common) 492 /* 493 * Here r13 points to the paca, r9 contains the saved CR, 494 * SRR0 and SRR1 are saved in r11 and r12, 495 * r9 - r13 are saved in paca->exgen. 496 */ 497 mfspr r10,SPRN_DAR 498 std r10,PACA_EXGEN+EX_DAR(r13) 499 mfspr r10,SPRN_DSISR 500 stw r10,PACA_EXGEN+EX_DSISR(r13) 501 EXCEPTION_PROLOG_COMMON(0x300, PACA_EXGEN) 502 RECONCILE_IRQ_STATE(r10, r11) 503 ld r12,_MSR(r1) 504 ld r3,PACA_EXGEN+EX_DAR(r13) 505 lwz r4,PACA_EXGEN+EX_DSISR(r13) 506 li r5,0x300 507 std r3,_DAR(r1) 508 std r4,_DSISR(r1) 509BEGIN_MMU_FTR_SECTION 510 b do_hash_page /* Try to handle as hpte fault */ 511MMU_FTR_SECTION_ELSE 512 b handle_page_fault 513ALT_MMU_FTR_SECTION_END_IFCLR(MMU_FTR_TYPE_RADIX) 514 515 516EXC_REAL_BEGIN(data_access_slb, 0x380, 0x80) 517 SET_SCRATCH0(r13) 518 EXCEPTION_PROLOG_0(PACA_EXSLB) 519 EXCEPTION_PROLOG_1(PACA_EXSLB, KVMTEST_PR, 0x380) 520 mr r12,r3 /* save r3 */ 521 mfspr r3,SPRN_DAR 522 mfspr r11,SPRN_SRR1 523 crset 4*cr6+eq 524 BRANCH_TO_COMMON(r10, slb_miss_common) 525EXC_REAL_END(data_access_slb, 0x380, 0x80) 526 527EXC_VIRT_BEGIN(data_access_slb, 0x4380, 0x80) 528 SET_SCRATCH0(r13) 529 EXCEPTION_PROLOG_0(PACA_EXSLB) 530 EXCEPTION_PROLOG_1(PACA_EXSLB, NOTEST, 0x380) 531 mr r12,r3 /* save r3 */ 532 mfspr r3,SPRN_DAR 533 mfspr r11,SPRN_SRR1 534 crset 4*cr6+eq 535 BRANCH_TO_COMMON(r10, slb_miss_common) 536EXC_VIRT_END(data_access_slb, 0x4380, 0x80) 537TRAMP_KVM_SKIP(PACA_EXSLB, 0x380) 538 539 540EXC_REAL(instruction_access, 0x400, 0x80) 541EXC_VIRT(instruction_access, 0x4400, 0x80, 0x400) 542TRAMP_KVM(PACA_EXGEN, 0x400) 543 544EXC_COMMON_BEGIN(instruction_access_common) 545 EXCEPTION_PROLOG_COMMON(0x400, PACA_EXGEN) 546 RECONCILE_IRQ_STATE(r10, r11) 547 ld r12,_MSR(r1) 548 ld r3,_NIP(r1) 549 andis. r4,r12,DSISR_SRR1_MATCH_64S@h 550 li r5,0x400 551 std r3,_DAR(r1) 552 std r4,_DSISR(r1) 553BEGIN_MMU_FTR_SECTION 554 b do_hash_page /* Try to handle as hpte fault */ 555MMU_FTR_SECTION_ELSE 556 b handle_page_fault 557ALT_MMU_FTR_SECTION_END_IFCLR(MMU_FTR_TYPE_RADIX) 558 559 560EXC_REAL_BEGIN(instruction_access_slb, 0x480, 0x80) 561 SET_SCRATCH0(r13) 562 EXCEPTION_PROLOG_0(PACA_EXSLB) 563 EXCEPTION_PROLOG_1(PACA_EXSLB, KVMTEST_PR, 0x480) 564 mr r12,r3 /* save r3 */ 565 mfspr r3,SPRN_SRR0 /* SRR0 is faulting address */ 566 mfspr r11,SPRN_SRR1 567 crclr 4*cr6+eq 568 BRANCH_TO_COMMON(r10, slb_miss_common) 569EXC_REAL_END(instruction_access_slb, 0x480, 0x80) 570 571EXC_VIRT_BEGIN(instruction_access_slb, 0x4480, 0x80) 572 SET_SCRATCH0(r13) 573 EXCEPTION_PROLOG_0(PACA_EXSLB) 574 EXCEPTION_PROLOG_1(PACA_EXSLB, NOTEST, 0x480) 575 mr r12,r3 /* save r3 */ 576 mfspr r3,SPRN_SRR0 /* SRR0 is faulting address */ 577 mfspr r11,SPRN_SRR1 578 crclr 4*cr6+eq 579 BRANCH_TO_COMMON(r10, slb_miss_common) 580EXC_VIRT_END(instruction_access_slb, 0x4480, 0x80) 581TRAMP_KVM(PACA_EXSLB, 0x480) 582 583 584/* 585 * This handler is used by the 0x380 and 0x480 SLB miss interrupts, as well as 586 * the virtual mode 0x4380 and 0x4480 interrupts if AIL is enabled. 587 */ 588EXC_COMMON_BEGIN(slb_miss_common) 589 /* 590 * r13 points to the PACA, r9 contains the saved CR, 591 * r12 contains the saved r3, 592 * r11 contain the saved SRR1, SRR0 is still ready for return 593 * r3 has the faulting address 594 * r9 - r13 are saved in paca->exslb. 595 * cr6.eq is set for a D-SLB miss, clear for a I-SLB miss 596 * We assume we aren't going to take any exceptions during this 597 * procedure. 598 */ 599 mflr r10 600 stw r9,PACA_EXSLB+EX_CCR(r13) /* save CR in exc. frame */ 601 std r10,PACA_EXSLB+EX_LR(r13) /* save LR */ 602 603 andi. r9,r11,MSR_PR // Check for exception from userspace 604 cmpdi cr4,r9,MSR_PR // And save the result in CR4 for later 605 606 /* 607 * Test MSR_RI before calling slb_allocate_realmode, because the 608 * MSR in r11 gets clobbered. However we still want to allocate 609 * SLB in case MSR_RI=0, to minimise the risk of getting stuck in 610 * recursive SLB faults. So use cr5 for this, which is preserved. 611 */ 612 andi. r11,r11,MSR_RI /* check for unrecoverable exception */ 613 cmpdi cr5,r11,MSR_RI 614 615 crset 4*cr0+eq 616#ifdef CONFIG_PPC_STD_MMU_64 617BEGIN_MMU_FTR_SECTION 618 bl slb_allocate 619END_MMU_FTR_SECTION_IFCLR(MMU_FTR_TYPE_RADIX) 620#endif 621 622 ld r10,PACA_EXSLB+EX_LR(r13) 623 lwz r9,PACA_EXSLB+EX_CCR(r13) /* get saved CR */ 624 mtlr r10 625 626 beq- 8f /* if bad address, make full stack frame */ 627 628 bne- cr5,2f /* if unrecoverable exception, oops */ 629 630 /* All done -- return from exception. */ 631 632 bne cr4,1f /* returning to kernel */ 633 634.machine push 635.machine "power4" 636 mtcrf 0x80,r9 637 mtcrf 0x08,r9 /* MSR[PR] indication is in cr4 */ 638 mtcrf 0x04,r9 /* MSR[RI] indication is in cr5 */ 639 mtcrf 0x02,r9 /* I/D indication is in cr6 */ 640 mtcrf 0x01,r9 /* slb_allocate uses cr0 and cr7 */ 641.machine pop 642 643 RESTORE_CTR(r9, PACA_EXSLB) 644 RESTORE_PPR_PACA(PACA_EXSLB, r9) 645 mr r3,r12 646 ld r9,PACA_EXSLB+EX_R9(r13) 647 ld r10,PACA_EXSLB+EX_R10(r13) 648 ld r11,PACA_EXSLB+EX_R11(r13) 649 ld r12,PACA_EXSLB+EX_R12(r13) 650 ld r13,PACA_EXSLB+EX_R13(r13) 651 RFI_TO_USER 652 b . /* prevent speculative execution */ 6531: 654.machine push 655.machine "power4" 656 mtcrf 0x80,r9 657 mtcrf 0x08,r9 /* MSR[PR] indication is in cr4 */ 658 mtcrf 0x04,r9 /* MSR[RI] indication is in cr5 */ 659 mtcrf 0x02,r9 /* I/D indication is in cr6 */ 660 mtcrf 0x01,r9 /* slb_allocate uses cr0 and cr7 */ 661.machine pop 662 663 RESTORE_CTR(r9, PACA_EXSLB) 664 RESTORE_PPR_PACA(PACA_EXSLB, r9) 665 mr r3,r12 666 ld r9,PACA_EXSLB+EX_R9(r13) 667 ld r10,PACA_EXSLB+EX_R10(r13) 668 ld r11,PACA_EXSLB+EX_R11(r13) 669 ld r12,PACA_EXSLB+EX_R12(r13) 670 ld r13,PACA_EXSLB+EX_R13(r13) 671 RFI_TO_KERNEL 672 b . /* prevent speculative execution */ 673 674 6752: std r3,PACA_EXSLB+EX_DAR(r13) 676 mr r3,r12 677 mfspr r11,SPRN_SRR0 678 mfspr r12,SPRN_SRR1 679 LOAD_HANDLER(r10,unrecov_slb) 680 mtspr SPRN_SRR0,r10 681 ld r10,PACAKMSR(r13) 682 mtspr SPRN_SRR1,r10 683 RFI_TO_KERNEL 684 b . 685 6868: std r3,PACA_EXSLB+EX_DAR(r13) 687 mr r3,r12 688 mfspr r11,SPRN_SRR0 689 mfspr r12,SPRN_SRR1 690 LOAD_HANDLER(r10,bad_addr_slb) 691 mtspr SPRN_SRR0,r10 692 ld r10,PACAKMSR(r13) 693 mtspr SPRN_SRR1,r10 694 RFI_TO_KERNEL 695 b . 696 697EXC_COMMON_BEGIN(unrecov_slb) 698 EXCEPTION_PROLOG_COMMON(0x4100, PACA_EXSLB) 699 RECONCILE_IRQ_STATE(r10, r11) 700 bl save_nvgprs 7011: addi r3,r1,STACK_FRAME_OVERHEAD 702 bl unrecoverable_exception 703 b 1b 704 705EXC_COMMON_BEGIN(bad_addr_slb) 706 EXCEPTION_PROLOG_COMMON(0x380, PACA_EXSLB) 707 RECONCILE_IRQ_STATE(r10, r11) 708 ld r3, PACA_EXSLB+EX_DAR(r13) 709 std r3, _DAR(r1) 710 beq cr6, 2f 711 li r10, 0x481 /* fix trap number for I-SLB miss */ 712 std r10, _TRAP(r1) 7132: bl save_nvgprs 714 addi r3, r1, STACK_FRAME_OVERHEAD 715 bl slb_miss_bad_addr 716 b ret_from_except 717 718EXC_REAL_BEGIN(hardware_interrupt, 0x500, 0x100) 719 .globl hardware_interrupt_hv; 720hardware_interrupt_hv: 721 BEGIN_FTR_SECTION 722 _MASKABLE_EXCEPTION_PSERIES(0x500, hardware_interrupt_common, 723 EXC_HV, SOFTEN_TEST_HV) 724 FTR_SECTION_ELSE 725 _MASKABLE_EXCEPTION_PSERIES(0x500, hardware_interrupt_common, 726 EXC_STD, SOFTEN_TEST_PR) 727 ALT_FTR_SECTION_END_IFSET(CPU_FTR_HVMODE | CPU_FTR_ARCH_206) 728EXC_REAL_END(hardware_interrupt, 0x500, 0x100) 729 730EXC_VIRT_BEGIN(hardware_interrupt, 0x4500, 0x100) 731 .globl hardware_interrupt_relon_hv; 732hardware_interrupt_relon_hv: 733 BEGIN_FTR_SECTION 734 _MASKABLE_RELON_EXCEPTION_PSERIES(0x500, hardware_interrupt_common, EXC_HV, SOFTEN_TEST_HV) 735 FTR_SECTION_ELSE 736 _MASKABLE_RELON_EXCEPTION_PSERIES(0x500, hardware_interrupt_common, EXC_STD, SOFTEN_TEST_PR) 737 ALT_FTR_SECTION_END_IFSET(CPU_FTR_HVMODE) 738EXC_VIRT_END(hardware_interrupt, 0x4500, 0x100) 739 740TRAMP_KVM(PACA_EXGEN, 0x500) 741TRAMP_KVM_HV(PACA_EXGEN, 0x500) 742EXC_COMMON_ASYNC(hardware_interrupt_common, 0x500, do_IRQ) 743 744 745EXC_REAL(alignment, 0x600, 0x100) 746EXC_VIRT(alignment, 0x4600, 0x100, 0x600) 747TRAMP_KVM(PACA_EXGEN, 0x600) 748EXC_COMMON_BEGIN(alignment_common) 749 mfspr r10,SPRN_DAR 750 std r10,PACA_EXGEN+EX_DAR(r13) 751 mfspr r10,SPRN_DSISR 752 stw r10,PACA_EXGEN+EX_DSISR(r13) 753 EXCEPTION_PROLOG_COMMON(0x600, PACA_EXGEN) 754 ld r3,PACA_EXGEN+EX_DAR(r13) 755 lwz r4,PACA_EXGEN+EX_DSISR(r13) 756 std r3,_DAR(r1) 757 std r4,_DSISR(r1) 758 bl save_nvgprs 759 RECONCILE_IRQ_STATE(r10, r11) 760 addi r3,r1,STACK_FRAME_OVERHEAD 761 bl alignment_exception 762 b ret_from_except 763 764 765EXC_REAL(program_check, 0x700, 0x100) 766EXC_VIRT(program_check, 0x4700, 0x100, 0x700) 767TRAMP_KVM(PACA_EXGEN, 0x700) 768EXC_COMMON_BEGIN(program_check_common) 769 /* 770 * It's possible to receive a TM Bad Thing type program check with 771 * userspace register values (in particular r1), but with SRR1 reporting 772 * that we came from the kernel. Normally that would confuse the bad 773 * stack logic, and we would report a bad kernel stack pointer. Instead 774 * we switch to the emergency stack if we're taking a TM Bad Thing from 775 * the kernel. 776 */ 777 li r10,MSR_PR /* Build a mask of MSR_PR .. */ 778 oris r10,r10,0x200000@h /* .. and SRR1_PROGTM */ 779 and r10,r10,r12 /* Mask SRR1 with that. */ 780 srdi r10,r10,8 /* Shift it so we can compare */ 781 cmpldi r10,(0x200000 >> 8) /* .. with an immediate. */ 782 bne 1f /* If != go to normal path. */ 783 784 /* SRR1 had PR=0 and SRR1_PROGTM=1, so use the emergency stack */ 785 andi. r10,r12,MSR_PR; /* Set CR0 correctly for label */ 786 /* 3 in EXCEPTION_PROLOG_COMMON */ 787 mr r10,r1 /* Save r1 */ 788 ld r1,PACAEMERGSP(r13) /* Use emergency stack */ 789 subi r1,r1,INT_FRAME_SIZE /* alloc stack frame */ 790 b 3f /* Jump into the macro !! */ 7911: EXCEPTION_PROLOG_COMMON(0x700, PACA_EXGEN) 792 bl save_nvgprs 793 RECONCILE_IRQ_STATE(r10, r11) 794 addi r3,r1,STACK_FRAME_OVERHEAD 795 bl program_check_exception 796 b ret_from_except 797 798 799EXC_REAL(fp_unavailable, 0x800, 0x100) 800EXC_VIRT(fp_unavailable, 0x4800, 0x100, 0x800) 801TRAMP_KVM(PACA_EXGEN, 0x800) 802EXC_COMMON_BEGIN(fp_unavailable_common) 803 EXCEPTION_PROLOG_COMMON(0x800, PACA_EXGEN) 804 bne 1f /* if from user, just load it up */ 805 bl save_nvgprs 806 RECONCILE_IRQ_STATE(r10, r11) 807 addi r3,r1,STACK_FRAME_OVERHEAD 808 bl kernel_fp_unavailable_exception 809 BUG_OPCODE 8101: 811#ifdef CONFIG_PPC_TRANSACTIONAL_MEM 812BEGIN_FTR_SECTION 813 /* Test if 2 TM state bits are zero. If non-zero (ie. userspace was in 814 * transaction), go do TM stuff 815 */ 816 rldicl. r0, r12, (64-MSR_TS_LG), (64-2) 817 bne- 2f 818END_FTR_SECTION_IFSET(CPU_FTR_TM) 819#endif 820 bl load_up_fpu 821 b fast_exception_return 822#ifdef CONFIG_PPC_TRANSACTIONAL_MEM 8232: /* User process was in a transaction */ 824 bl save_nvgprs 825 RECONCILE_IRQ_STATE(r10, r11) 826 addi r3,r1,STACK_FRAME_OVERHEAD 827 bl fp_unavailable_tm 828 b ret_from_except 829#endif 830 831 832EXC_REAL_OOL_MASKABLE(decrementer, 0x900, 0x80) 833EXC_VIRT_MASKABLE(decrementer, 0x4900, 0x80, 0x900) 834TRAMP_KVM(PACA_EXGEN, 0x900) 835EXC_COMMON_ASYNC(decrementer_common, 0x900, timer_interrupt) 836 837 838EXC_REAL_HV(hdecrementer, 0x980, 0x80) 839EXC_VIRT_HV(hdecrementer, 0x4980, 0x80, 0x980) 840TRAMP_KVM_HV(PACA_EXGEN, 0x980) 841EXC_COMMON(hdecrementer_common, 0x980, hdec_interrupt) 842 843 844EXC_REAL_MASKABLE(doorbell_super, 0xa00, 0x100) 845EXC_VIRT_MASKABLE(doorbell_super, 0x4a00, 0x100, 0xa00) 846TRAMP_KVM(PACA_EXGEN, 0xa00) 847#ifdef CONFIG_PPC_DOORBELL 848EXC_COMMON_ASYNC(doorbell_super_common, 0xa00, doorbell_exception) 849#else 850EXC_COMMON_ASYNC(doorbell_super_common, 0xa00, unknown_exception) 851#endif 852 853 854EXC_REAL(trap_0b, 0xb00, 0x100) 855EXC_VIRT(trap_0b, 0x4b00, 0x100, 0xb00) 856TRAMP_KVM(PACA_EXGEN, 0xb00) 857EXC_COMMON(trap_0b_common, 0xb00, unknown_exception) 858 859/* 860 * system call / hypercall (0xc00, 0x4c00) 861 * 862 * The system call exception is invoked with "sc 0" and does not alter HV bit. 863 * There is support for kernel code to invoke system calls but there are no 864 * in-tree users. 865 * 866 * The hypercall is invoked with "sc 1" and sets HV=1. 867 * 868 * In HPT, sc 1 always goes to 0xc00 real mode. In RADIX, sc 1 can go to 869 * 0x4c00 virtual mode. 870 * 871 * Call convention: 872 * 873 * syscall register convention is in Documentation/powerpc/syscall64-abi.txt 874 * 875 * For hypercalls, the register convention is as follows: 876 * r0 volatile 877 * r1-2 nonvolatile 878 * r3 volatile parameter and return value for status 879 * r4-r10 volatile input and output value 880 * r11 volatile hypercall number and output value 881 * r12 volatile input and output value 882 * r13-r31 nonvolatile 883 * LR nonvolatile 884 * CTR volatile 885 * XER volatile 886 * CR0-1 CR5-7 volatile 887 * CR2-4 nonvolatile 888 * Other registers nonvolatile 889 * 890 * The intersection of volatile registers that don't contain possible 891 * inputs is: cr0, xer, ctr. We may use these as scratch regs upon entry 892 * without saving, though xer is not a good idea to use, as hardware may 893 * interpret some bits so it may be costly to change them. 894 */ 895#ifdef CONFIG_KVM_BOOK3S_64_HANDLER 896 /* 897 * There is a little bit of juggling to get syscall and hcall 898 * working well. Save r13 in ctr to avoid using SPRG scratch 899 * register. 900 * 901 * Userspace syscalls have already saved the PPR, hcalls must save 902 * it before setting HMT_MEDIUM. 903 */ 904#define SYSCALL_KVMTEST \ 905 mtctr r13; \ 906 GET_PACA(r13); \ 907 std r10,PACA_EXGEN+EX_R10(r13); \ 908 INTERRUPT_TO_KERNEL; \ 909 KVMTEST_PR(0xc00); /* uses r10, branch to do_kvm_0xc00_system_call */ \ 910 HMT_MEDIUM; \ 911 mfctr r9; 912 913#else 914#define SYSCALL_KVMTEST \ 915 HMT_MEDIUM; \ 916 mr r9,r13; \ 917 GET_PACA(r13); \ 918 INTERRUPT_TO_KERNEL; 919#endif 920 921#define LOAD_SYSCALL_HANDLER(reg) \ 922 __LOAD_HANDLER(reg, system_call_common) 923 924#define SYSCALL_FASTENDIAN_TEST \ 925BEGIN_FTR_SECTION \ 926 cmpdi r0,0x1ebe ; \ 927 beq- 1f ; \ 928END_FTR_SECTION_IFSET(CPU_FTR_REAL_LE) \ 929 930/* 931 * After SYSCALL_KVMTEST, we reach here with PACA in r13, r13 in r9, 932 * and HMT_MEDIUM. 933 */ 934#define SYSCALL_REAL \ 935 mfspr r11,SPRN_SRR0 ; \ 936 mfspr r12,SPRN_SRR1 ; \ 937 LOAD_SYSCALL_HANDLER(r10) ; \ 938 mtspr SPRN_SRR0,r10 ; \ 939 ld r10,PACAKMSR(r13) ; \ 940 mtspr SPRN_SRR1,r10 ; \ 941 RFI_TO_KERNEL ; \ 942 b . ; /* prevent speculative execution */ 943 944#define SYSCALL_FASTENDIAN \ 945 /* Fast LE/BE switch system call */ \ 9461: mfspr r12,SPRN_SRR1 ; \ 947 xori r12,r12,MSR_LE ; \ 948 mtspr SPRN_SRR1,r12 ; \ 949 mr r13,r9 ; \ 950 RFI_TO_USER ; /* return to userspace */ \ 951 b . ; /* prevent speculative execution */ 952 953#if defined(CONFIG_RELOCATABLE) 954 /* 955 * We can't branch directly so we do it via the CTR which 956 * is volatile across system calls. 957 */ 958#define SYSCALL_VIRT \ 959 LOAD_SYSCALL_HANDLER(r10) ; \ 960 mtctr r10 ; \ 961 mfspr r11,SPRN_SRR0 ; \ 962 mfspr r12,SPRN_SRR1 ; \ 963 li r10,MSR_RI ; \ 964 mtmsrd r10,1 ; \ 965 bctr ; 966#else 967 /* We can branch directly */ 968#define SYSCALL_VIRT \ 969 mfspr r11,SPRN_SRR0 ; \ 970 mfspr r12,SPRN_SRR1 ; \ 971 li r10,MSR_RI ; \ 972 mtmsrd r10,1 ; /* Set RI (EE=0) */ \ 973 b system_call_common ; 974#endif 975 976EXC_REAL_BEGIN(system_call, 0xc00, 0x100) 977 SYSCALL_KVMTEST /* loads PACA into r13, and saves r13 to r9 */ 978 SYSCALL_FASTENDIAN_TEST 979 SYSCALL_REAL 980 SYSCALL_FASTENDIAN 981EXC_REAL_END(system_call, 0xc00, 0x100) 982 983EXC_VIRT_BEGIN(system_call, 0x4c00, 0x100) 984 SYSCALL_KVMTEST /* loads PACA into r13, and saves r13 to r9 */ 985 SYSCALL_FASTENDIAN_TEST 986 SYSCALL_VIRT 987 SYSCALL_FASTENDIAN 988EXC_VIRT_END(system_call, 0x4c00, 0x100) 989 990#ifdef CONFIG_KVM_BOOK3S_64_HANDLER 991 /* 992 * This is a hcall, so register convention is as above, with these 993 * differences: 994 * r13 = PACA 995 * ctr = orig r13 996 * orig r10 saved in PACA 997 */ 998TRAMP_KVM_BEGIN(do_kvm_0xc00) 999 /* 1000 * Save the PPR (on systems that support it) before changing to 1001 * HMT_MEDIUM. That allows the KVM code to save that value into the 1002 * guest state (it is the guest's PPR value). 1003 */ 1004 OPT_GET_SPR(r10, SPRN_PPR, CPU_FTR_HAS_PPR) 1005 HMT_MEDIUM 1006 OPT_SAVE_REG_TO_PACA(PACA_EXGEN+EX_PPR, r10, CPU_FTR_HAS_PPR) 1007 mfctr r10 1008 SET_SCRATCH0(r10) 1009 std r9,PACA_EXGEN+EX_R9(r13) 1010 mfcr r9 1011 KVM_HANDLER(PACA_EXGEN, EXC_STD, 0xc00) 1012#endif 1013 1014 1015EXC_REAL(single_step, 0xd00, 0x100) 1016EXC_VIRT(single_step, 0x4d00, 0x100, 0xd00) 1017TRAMP_KVM(PACA_EXGEN, 0xd00) 1018EXC_COMMON(single_step_common, 0xd00, single_step_exception) 1019 1020EXC_REAL_OOL_HV(h_data_storage, 0xe00, 0x20) 1021EXC_VIRT_OOL_HV(h_data_storage, 0x4e00, 0x20, 0xe00) 1022TRAMP_KVM_HV_SKIP(PACA_EXGEN, 0xe00) 1023EXC_COMMON_BEGIN(h_data_storage_common) 1024 mfspr r10,SPRN_HDAR 1025 std r10,PACA_EXGEN+EX_DAR(r13) 1026 mfspr r10,SPRN_HDSISR 1027 stw r10,PACA_EXGEN+EX_DSISR(r13) 1028 EXCEPTION_PROLOG_COMMON(0xe00, PACA_EXGEN) 1029 bl save_nvgprs 1030 RECONCILE_IRQ_STATE(r10, r11) 1031 addi r3,r1,STACK_FRAME_OVERHEAD 1032 bl unknown_exception 1033 b ret_from_except 1034 1035 1036EXC_REAL_OOL_HV(h_instr_storage, 0xe20, 0x20) 1037EXC_VIRT_OOL_HV(h_instr_storage, 0x4e20, 0x20, 0xe20) 1038TRAMP_KVM_HV(PACA_EXGEN, 0xe20) 1039EXC_COMMON(h_instr_storage_common, 0xe20, unknown_exception) 1040 1041 1042EXC_REAL_OOL_HV(emulation_assist, 0xe40, 0x20) 1043EXC_VIRT_OOL_HV(emulation_assist, 0x4e40, 0x20, 0xe40) 1044TRAMP_KVM_HV(PACA_EXGEN, 0xe40) 1045EXC_COMMON(emulation_assist_common, 0xe40, emulation_assist_interrupt) 1046 1047 1048/* 1049 * hmi_exception trampoline is a special case. It jumps to hmi_exception_early 1050 * first, and then eventaully from there to the trampoline to get into virtual 1051 * mode. 1052 */ 1053__EXC_REAL_OOL_HV_DIRECT(hmi_exception, 0xe60, 0x20, hmi_exception_early) 1054__TRAMP_REAL_OOL_MASKABLE_HV(hmi_exception, 0xe60) 1055EXC_VIRT_NONE(0x4e60, 0x20) 1056TRAMP_KVM_HV(PACA_EXGEN, 0xe60) 1057TRAMP_REAL_BEGIN(hmi_exception_early) 1058 EXCEPTION_PROLOG_1(PACA_EXGEN, KVMTEST_HV, 0xe60) 1059 mr r10,r1 /* Save r1 */ 1060 ld r1,PACAEMERGSP(r13) /* Use emergency stack for realmode */ 1061 subi r1,r1,INT_FRAME_SIZE /* alloc stack frame */ 1062 mfspr r11,SPRN_HSRR0 /* Save HSRR0 */ 1063 mfspr r12,SPRN_HSRR1 /* Save HSRR1 */ 1064 EXCEPTION_PROLOG_COMMON_1() 1065 EXCEPTION_PROLOG_COMMON_2(PACA_EXGEN) 1066 EXCEPTION_PROLOG_COMMON_3(0xe60) 1067 addi r3,r1,STACK_FRAME_OVERHEAD 1068 BRANCH_LINK_TO_FAR(hmi_exception_realmode) /* Function call ABI */ 1069 /* Windup the stack. */ 1070 /* Move original HSRR0 and HSRR1 into the respective regs */ 1071 ld r9,_MSR(r1) 1072 mtspr SPRN_HSRR1,r9 1073 ld r3,_NIP(r1) 1074 mtspr SPRN_HSRR0,r3 1075 ld r9,_CTR(r1) 1076 mtctr r9 1077 ld r9,_XER(r1) 1078 mtxer r9 1079 ld r9,_LINK(r1) 1080 mtlr r9 1081 REST_GPR(0, r1) 1082 REST_8GPRS(2, r1) 1083 REST_GPR(10, r1) 1084 ld r11,_CCR(r1) 1085 mtcr r11 1086 REST_GPR(11, r1) 1087 REST_2GPRS(12, r1) 1088 /* restore original r1. */ 1089 ld r1,GPR1(r1) 1090 1091 /* 1092 * Go to virtual mode and pull the HMI event information from 1093 * firmware. 1094 */ 1095 .globl hmi_exception_after_realmode 1096hmi_exception_after_realmode: 1097 SET_SCRATCH0(r13) 1098 EXCEPTION_PROLOG_0(PACA_EXGEN) 1099 b tramp_real_hmi_exception 1100 1101EXC_COMMON_ASYNC(hmi_exception_common, 0xe60, handle_hmi_exception) 1102 1103 1104EXC_REAL_OOL_MASKABLE_HV(h_doorbell, 0xe80, 0x20) 1105EXC_VIRT_OOL_MASKABLE_HV(h_doorbell, 0x4e80, 0x20, 0xe80) 1106TRAMP_KVM_HV(PACA_EXGEN, 0xe80) 1107#ifdef CONFIG_PPC_DOORBELL 1108EXC_COMMON_ASYNC(h_doorbell_common, 0xe80, doorbell_exception) 1109#else 1110EXC_COMMON_ASYNC(h_doorbell_common, 0xe80, unknown_exception) 1111#endif 1112 1113 1114EXC_REAL_OOL_MASKABLE_HV(h_virt_irq, 0xea0, 0x20) 1115EXC_VIRT_OOL_MASKABLE_HV(h_virt_irq, 0x4ea0, 0x20, 0xea0) 1116TRAMP_KVM_HV(PACA_EXGEN, 0xea0) 1117EXC_COMMON_ASYNC(h_virt_irq_common, 0xea0, do_IRQ) 1118 1119 1120EXC_REAL_NONE(0xec0, 0x20) 1121EXC_VIRT_NONE(0x4ec0, 0x20) 1122EXC_REAL_NONE(0xee0, 0x20) 1123EXC_VIRT_NONE(0x4ee0, 0x20) 1124 1125 1126EXC_REAL_OOL(performance_monitor, 0xf00, 0x20) 1127EXC_VIRT_OOL(performance_monitor, 0x4f00, 0x20, 0xf00) 1128TRAMP_KVM(PACA_EXGEN, 0xf00) 1129EXC_COMMON_ASYNC(performance_monitor_common, 0xf00, performance_monitor_exception) 1130 1131 1132EXC_REAL_OOL(altivec_unavailable, 0xf20, 0x20) 1133EXC_VIRT_OOL(altivec_unavailable, 0x4f20, 0x20, 0xf20) 1134TRAMP_KVM(PACA_EXGEN, 0xf20) 1135EXC_COMMON_BEGIN(altivec_unavailable_common) 1136 EXCEPTION_PROLOG_COMMON(0xf20, PACA_EXGEN) 1137#ifdef CONFIG_ALTIVEC 1138BEGIN_FTR_SECTION 1139 beq 1f 1140#ifdef CONFIG_PPC_TRANSACTIONAL_MEM 1141 BEGIN_FTR_SECTION_NESTED(69) 1142 /* Test if 2 TM state bits are zero. If non-zero (ie. userspace was in 1143 * transaction), go do TM stuff 1144 */ 1145 rldicl. r0, r12, (64-MSR_TS_LG), (64-2) 1146 bne- 2f 1147 END_FTR_SECTION_NESTED(CPU_FTR_TM, CPU_FTR_TM, 69) 1148#endif 1149 bl load_up_altivec 1150 b fast_exception_return 1151#ifdef CONFIG_PPC_TRANSACTIONAL_MEM 11522: /* User process was in a transaction */ 1153 bl save_nvgprs 1154 RECONCILE_IRQ_STATE(r10, r11) 1155 addi r3,r1,STACK_FRAME_OVERHEAD 1156 bl altivec_unavailable_tm 1157 b ret_from_except 1158#endif 11591: 1160END_FTR_SECTION_IFSET(CPU_FTR_ALTIVEC) 1161#endif 1162 bl save_nvgprs 1163 RECONCILE_IRQ_STATE(r10, r11) 1164 addi r3,r1,STACK_FRAME_OVERHEAD 1165 bl altivec_unavailable_exception 1166 b ret_from_except 1167 1168 1169EXC_REAL_OOL(vsx_unavailable, 0xf40, 0x20) 1170EXC_VIRT_OOL(vsx_unavailable, 0x4f40, 0x20, 0xf40) 1171TRAMP_KVM(PACA_EXGEN, 0xf40) 1172EXC_COMMON_BEGIN(vsx_unavailable_common) 1173 EXCEPTION_PROLOG_COMMON(0xf40, PACA_EXGEN) 1174#ifdef CONFIG_VSX 1175BEGIN_FTR_SECTION 1176 beq 1f 1177#ifdef CONFIG_PPC_TRANSACTIONAL_MEM 1178 BEGIN_FTR_SECTION_NESTED(69) 1179 /* Test if 2 TM state bits are zero. If non-zero (ie. userspace was in 1180 * transaction), go do TM stuff 1181 */ 1182 rldicl. r0, r12, (64-MSR_TS_LG), (64-2) 1183 bne- 2f 1184 END_FTR_SECTION_NESTED(CPU_FTR_TM, CPU_FTR_TM, 69) 1185#endif 1186 b load_up_vsx 1187#ifdef CONFIG_PPC_TRANSACTIONAL_MEM 11882: /* User process was in a transaction */ 1189 bl save_nvgprs 1190 RECONCILE_IRQ_STATE(r10, r11) 1191 addi r3,r1,STACK_FRAME_OVERHEAD 1192 bl vsx_unavailable_tm 1193 b ret_from_except 1194#endif 11951: 1196END_FTR_SECTION_IFSET(CPU_FTR_VSX) 1197#endif 1198 bl save_nvgprs 1199 RECONCILE_IRQ_STATE(r10, r11) 1200 addi r3,r1,STACK_FRAME_OVERHEAD 1201 bl vsx_unavailable_exception 1202 b ret_from_except 1203 1204 1205EXC_REAL_OOL(facility_unavailable, 0xf60, 0x20) 1206EXC_VIRT_OOL(facility_unavailable, 0x4f60, 0x20, 0xf60) 1207TRAMP_KVM(PACA_EXGEN, 0xf60) 1208EXC_COMMON(facility_unavailable_common, 0xf60, facility_unavailable_exception) 1209 1210 1211EXC_REAL_OOL_HV(h_facility_unavailable, 0xf80, 0x20) 1212EXC_VIRT_OOL_HV(h_facility_unavailable, 0x4f80, 0x20, 0xf80) 1213TRAMP_KVM_HV(PACA_EXGEN, 0xf80) 1214EXC_COMMON(h_facility_unavailable_common, 0xf80, facility_unavailable_exception) 1215 1216 1217EXC_REAL_NONE(0xfa0, 0x20) 1218EXC_VIRT_NONE(0x4fa0, 0x20) 1219EXC_REAL_NONE(0xfc0, 0x20) 1220EXC_VIRT_NONE(0x4fc0, 0x20) 1221EXC_REAL_NONE(0xfe0, 0x20) 1222EXC_VIRT_NONE(0x4fe0, 0x20) 1223 1224EXC_REAL_NONE(0x1000, 0x100) 1225EXC_VIRT_NONE(0x5000, 0x100) 1226EXC_REAL_NONE(0x1100, 0x100) 1227EXC_VIRT_NONE(0x5100, 0x100) 1228 1229#ifdef CONFIG_CBE_RAS 1230EXC_REAL_HV(cbe_system_error, 0x1200, 0x100) 1231EXC_VIRT_NONE(0x5200, 0x100) 1232TRAMP_KVM_HV_SKIP(PACA_EXGEN, 0x1200) 1233EXC_COMMON(cbe_system_error_common, 0x1200, cbe_system_error_exception) 1234#else /* CONFIG_CBE_RAS */ 1235EXC_REAL_NONE(0x1200, 0x100) 1236EXC_VIRT_NONE(0x5200, 0x100) 1237#endif 1238 1239 1240EXC_REAL(instruction_breakpoint, 0x1300, 0x100) 1241EXC_VIRT(instruction_breakpoint, 0x5300, 0x100, 0x1300) 1242TRAMP_KVM_SKIP(PACA_EXGEN, 0x1300) 1243EXC_COMMON(instruction_breakpoint_common, 0x1300, instruction_breakpoint_exception) 1244 1245EXC_REAL_NONE(0x1400, 0x100) 1246EXC_VIRT_NONE(0x5400, 0x100) 1247 1248EXC_REAL_BEGIN(denorm_exception_hv, 0x1500, 0x100) 1249 mtspr SPRN_SPRG_HSCRATCH0,r13 1250 EXCEPTION_PROLOG_0(PACA_EXGEN) 1251 EXCEPTION_PROLOG_1(PACA_EXGEN, NOTEST, 0x1500) 1252 1253#ifdef CONFIG_PPC_DENORMALISATION 1254 mfspr r10,SPRN_HSRR1 1255 mfspr r11,SPRN_HSRR0 /* save HSRR0 */ 1256 andis. r10,r10,(HSRR1_DENORM)@h /* denorm? */ 1257 addi r11,r11,-4 /* HSRR0 is next instruction */ 1258 bne+ denorm_assist 1259#endif 1260 1261 KVMTEST_PR(0x1500) 1262 EXCEPTION_PROLOG_PSERIES_1(denorm_common, EXC_HV) 1263EXC_REAL_END(denorm_exception_hv, 0x1500, 0x100) 1264 1265#ifdef CONFIG_PPC_DENORMALISATION 1266EXC_VIRT_BEGIN(denorm_exception, 0x5500, 0x100) 1267 b exc_real_0x1500_denorm_exception_hv 1268EXC_VIRT_END(denorm_exception, 0x5500, 0x100) 1269#else 1270EXC_VIRT_NONE(0x5500, 0x100) 1271#endif 1272 1273TRAMP_KVM_SKIP(PACA_EXGEN, 0x1500) 1274 1275#ifdef CONFIG_PPC_DENORMALISATION 1276TRAMP_REAL_BEGIN(denorm_assist) 1277BEGIN_FTR_SECTION 1278/* 1279 * To denormalise we need to move a copy of the register to itself. 1280 * For POWER6 do that here for all FP regs. 1281 */ 1282 mfmsr r10 1283 ori r10,r10,(MSR_FP|MSR_FE0|MSR_FE1) 1284 xori r10,r10,(MSR_FE0|MSR_FE1) 1285 mtmsrd r10 1286 sync 1287 1288#define FMR2(n) fmr (n), (n) ; fmr n+1, n+1 1289#define FMR4(n) FMR2(n) ; FMR2(n+2) 1290#define FMR8(n) FMR4(n) ; FMR4(n+4) 1291#define FMR16(n) FMR8(n) ; FMR8(n+8) 1292#define FMR32(n) FMR16(n) ; FMR16(n+16) 1293 FMR32(0) 1294 1295FTR_SECTION_ELSE 1296/* 1297 * To denormalise we need to move a copy of the register to itself. 1298 * For POWER7 do that here for the first 32 VSX registers only. 1299 */ 1300 mfmsr r10 1301 oris r10,r10,MSR_VSX@h 1302 mtmsrd r10 1303 sync 1304 1305#define XVCPSGNDP2(n) XVCPSGNDP(n,n,n) ; XVCPSGNDP(n+1,n+1,n+1) 1306#define XVCPSGNDP4(n) XVCPSGNDP2(n) ; XVCPSGNDP2(n+2) 1307#define XVCPSGNDP8(n) XVCPSGNDP4(n) ; XVCPSGNDP4(n+4) 1308#define XVCPSGNDP16(n) XVCPSGNDP8(n) ; XVCPSGNDP8(n+8) 1309#define XVCPSGNDP32(n) XVCPSGNDP16(n) ; XVCPSGNDP16(n+16) 1310 XVCPSGNDP32(0) 1311 1312ALT_FTR_SECTION_END_IFCLR(CPU_FTR_ARCH_206) 1313 1314BEGIN_FTR_SECTION 1315 b denorm_done 1316END_FTR_SECTION_IFCLR(CPU_FTR_ARCH_207S) 1317/* 1318 * To denormalise we need to move a copy of the register to itself. 1319 * For POWER8 we need to do that for all 64 VSX registers 1320 */ 1321 XVCPSGNDP32(32) 1322denorm_done: 1323 mtspr SPRN_HSRR0,r11 1324 mtcrf 0x80,r9 1325 ld r9,PACA_EXGEN+EX_R9(r13) 1326 RESTORE_PPR_PACA(PACA_EXGEN, r10) 1327BEGIN_FTR_SECTION 1328 ld r10,PACA_EXGEN+EX_CFAR(r13) 1329 mtspr SPRN_CFAR,r10 1330END_FTR_SECTION_IFSET(CPU_FTR_CFAR) 1331 ld r10,PACA_EXGEN+EX_R10(r13) 1332 ld r11,PACA_EXGEN+EX_R11(r13) 1333 ld r12,PACA_EXGEN+EX_R12(r13) 1334 ld r13,PACA_EXGEN+EX_R13(r13) 1335 HRFI_TO_UNKNOWN 1336 b . 1337#endif 1338 1339EXC_COMMON_HV(denorm_common, 0x1500, unknown_exception) 1340 1341 1342#ifdef CONFIG_CBE_RAS 1343EXC_REAL_HV(cbe_maintenance, 0x1600, 0x100) 1344EXC_VIRT_NONE(0x5600, 0x100) 1345TRAMP_KVM_HV_SKIP(PACA_EXGEN, 0x1600) 1346EXC_COMMON(cbe_maintenance_common, 0x1600, cbe_maintenance_exception) 1347#else /* CONFIG_CBE_RAS */ 1348EXC_REAL_NONE(0x1600, 0x100) 1349EXC_VIRT_NONE(0x5600, 0x100) 1350#endif 1351 1352 1353EXC_REAL(altivec_assist, 0x1700, 0x100) 1354EXC_VIRT(altivec_assist, 0x5700, 0x100, 0x1700) 1355TRAMP_KVM(PACA_EXGEN, 0x1700) 1356#ifdef CONFIG_ALTIVEC 1357EXC_COMMON(altivec_assist_common, 0x1700, altivec_assist_exception) 1358#else 1359EXC_COMMON(altivec_assist_common, 0x1700, unknown_exception) 1360#endif 1361 1362 1363#ifdef CONFIG_CBE_RAS 1364EXC_REAL_HV(cbe_thermal, 0x1800, 0x100) 1365EXC_VIRT_NONE(0x5800, 0x100) 1366TRAMP_KVM_HV_SKIP(PACA_EXGEN, 0x1800) 1367EXC_COMMON(cbe_thermal_common, 0x1800, cbe_thermal_exception) 1368#else /* CONFIG_CBE_RAS */ 1369EXC_REAL_NONE(0x1800, 0x100) 1370EXC_VIRT_NONE(0x5800, 0x100) 1371#endif 1372 1373#ifdef CONFIG_PPC_WATCHDOG 1374 1375#define MASKED_DEC_HANDLER_LABEL 3f 1376 1377#define MASKED_DEC_HANDLER(_H) \ 13783: /* soft-nmi */ \ 1379 std r12,PACA_EXGEN+EX_R12(r13); \ 1380 GET_SCRATCH0(r10); \ 1381 std r10,PACA_EXGEN+EX_R13(r13); \ 1382 EXCEPTION_PROLOG_PSERIES_1(soft_nmi_common, _H) 1383 1384/* 1385 * Branch to soft_nmi_interrupt using the emergency stack. The emergency 1386 * stack is one that is usable by maskable interrupts so long as MSR_EE 1387 * remains off. It is used for recovery when something has corrupted the 1388 * normal kernel stack, for example. The "soft NMI" must not use the process 1389 * stack because we want irq disabled sections to avoid touching the stack 1390 * at all (other than PMU interrupts), so use the emergency stack for this, 1391 * and run it entirely with interrupts hard disabled. 1392 */ 1393EXC_COMMON_BEGIN(soft_nmi_common) 1394 mr r10,r1 1395 ld r1,PACAEMERGSP(r13) 1396 subi r1,r1,INT_FRAME_SIZE 1397 EXCEPTION_COMMON_NORET_STACK(PACA_EXGEN, 0x900, 1398 system_reset, soft_nmi_interrupt, 1399 ADD_NVGPRS;ADD_RECONCILE) 1400 b ret_from_except 1401 1402#else /* CONFIG_PPC_WATCHDOG */ 1403#define MASKED_DEC_HANDLER_LABEL 2f /* normal return */ 1404#define MASKED_DEC_HANDLER(_H) 1405#endif /* CONFIG_PPC_WATCHDOG */ 1406 1407/* 1408 * An interrupt came in while soft-disabled. We set paca->irq_happened, then: 1409 * - If it was a decrementer interrupt, we bump the dec to max and and return. 1410 * - If it was a doorbell we return immediately since doorbells are edge 1411 * triggered and won't automatically refire. 1412 * - If it was a HMI we return immediately since we handled it in realmode 1413 * and it won't refire. 1414 * - else we hard disable and return. 1415 * This is called with r10 containing the value to OR to the paca field. 1416 */ 1417#define MASKED_INTERRUPT(_H) \ 1418masked_##_H##interrupt: \ 1419 std r11,PACA_EXGEN+EX_R11(r13); \ 1420 lbz r11,PACAIRQHAPPENED(r13); \ 1421 or r11,r11,r10; \ 1422 stb r11,PACAIRQHAPPENED(r13); \ 1423 cmpwi r10,PACA_IRQ_DEC; \ 1424 bne 1f; \ 1425 lis r10,0x7fff; \ 1426 ori r10,r10,0xffff; \ 1427 mtspr SPRN_DEC,r10; \ 1428 b MASKED_DEC_HANDLER_LABEL; \ 14291: andi. r10,r10,(PACA_IRQ_DBELL|PACA_IRQ_HMI); \ 1430 bne 2f; \ 1431 mfspr r10,SPRN_##_H##SRR1; \ 1432 xori r10,r10,MSR_EE; /* clear MSR_EE */ \ 1433 mtspr SPRN_##_H##SRR1,r10; \ 14342: mtcrf 0x80,r9; \ 1435 ld r9,PACA_EXGEN+EX_R9(r13); \ 1436 ld r10,PACA_EXGEN+EX_R10(r13); \ 1437 ld r11,PACA_EXGEN+EX_R11(r13); \ 1438 /* returns to kernel where r13 must be set up, so don't restore it */ \ 1439 ##_H##RFI_TO_KERNEL; \ 1440 b .; \ 1441 MASKED_DEC_HANDLER(_H) 1442 1443TRAMP_REAL_BEGIN(stf_barrier_fallback) 1444 std r9,PACA_EXRFI+EX_R9(r13) 1445 std r10,PACA_EXRFI+EX_R10(r13) 1446 sync 1447 ld r9,PACA_EXRFI+EX_R9(r13) 1448 ld r10,PACA_EXRFI+EX_R10(r13) 1449 ori 31,31,0 1450 .rept 14 1451 b 1f 14521: 1453 .endr 1454 blr 1455 1456TRAMP_REAL_BEGIN(rfi_flush_fallback) 1457 SET_SCRATCH0(r13); 1458 GET_PACA(r13); 1459 std r1,PACA_EXRFI+EX_R12(r13) 1460 ld r1,PACAKSAVE(r13) 1461 std r9,PACA_EXRFI+EX_R9(r13) 1462 std r10,PACA_EXRFI+EX_R10(r13) 1463 std r11,PACA_EXRFI+EX_R11(r13) 1464 mfctr r9 1465 ld r10,PACA_RFI_FLUSH_FALLBACK_AREA(r13) 1466 ld r11,PACA_L1D_FLUSH_SIZE(r13) 1467 srdi r11,r11,(7 + 3) /* 128 byte lines, unrolled 8x */ 1468 mtctr r11 1469 DCBT_STOP_ALL_STREAM_IDS(r11) /* Stop prefetch streams */ 1470 1471 /* order ld/st prior to dcbt stop all streams with flushing */ 1472 sync 1473 1474 /* 1475 * The load adresses are at staggered offsets within cachelines, 1476 * which suits some pipelines better (on others it should not 1477 * hurt). 1478 */ 14791: 1480 ld r11,(0x80 + 8)*0(r10) 1481 ld r11,(0x80 + 8)*1(r10) 1482 ld r11,(0x80 + 8)*2(r10) 1483 ld r11,(0x80 + 8)*3(r10) 1484 ld r11,(0x80 + 8)*4(r10) 1485 ld r11,(0x80 + 8)*5(r10) 1486 ld r11,(0x80 + 8)*6(r10) 1487 ld r11,(0x80 + 8)*7(r10) 1488 addi r10,r10,0x80*8 1489 bdnz 1b 1490 1491 mtctr r9 1492 ld r9,PACA_EXRFI+EX_R9(r13) 1493 ld r10,PACA_EXRFI+EX_R10(r13) 1494 ld r11,PACA_EXRFI+EX_R11(r13) 1495 ld r1,PACA_EXRFI+EX_R12(r13) 1496 GET_SCRATCH0(r13); 1497 rfid 1498 1499TRAMP_REAL_BEGIN(hrfi_flush_fallback) 1500 SET_SCRATCH0(r13); 1501 GET_PACA(r13); 1502 std r1,PACA_EXRFI+EX_R12(r13) 1503 ld r1,PACAKSAVE(r13) 1504 std r9,PACA_EXRFI+EX_R9(r13) 1505 std r10,PACA_EXRFI+EX_R10(r13) 1506 std r11,PACA_EXRFI+EX_R11(r13) 1507 mfctr r9 1508 ld r10,PACA_RFI_FLUSH_FALLBACK_AREA(r13) 1509 ld r11,PACA_L1D_FLUSH_SIZE(r13) 1510 srdi r11,r11,(7 + 3) /* 128 byte lines, unrolled 8x */ 1511 mtctr r11 1512 DCBT_STOP_ALL_STREAM_IDS(r11) /* Stop prefetch streams */ 1513 1514 /* order ld/st prior to dcbt stop all streams with flushing */ 1515 sync 1516 1517 /* 1518 * The load adresses are at staggered offsets within cachelines, 1519 * which suits some pipelines better (on others it should not 1520 * hurt). 1521 */ 15221: 1523 ld r11,(0x80 + 8)*0(r10) 1524 ld r11,(0x80 + 8)*1(r10) 1525 ld r11,(0x80 + 8)*2(r10) 1526 ld r11,(0x80 + 8)*3(r10) 1527 ld r11,(0x80 + 8)*4(r10) 1528 ld r11,(0x80 + 8)*5(r10) 1529 ld r11,(0x80 + 8)*6(r10) 1530 ld r11,(0x80 + 8)*7(r10) 1531 addi r10,r10,0x80*8 1532 bdnz 1b 1533 1534 mtctr r9 1535 ld r9,PACA_EXRFI+EX_R9(r13) 1536 ld r10,PACA_EXRFI+EX_R10(r13) 1537 ld r11,PACA_EXRFI+EX_R11(r13) 1538 ld r1,PACA_EXRFI+EX_R12(r13) 1539 GET_SCRATCH0(r13); 1540 hrfid 1541 1542/* 1543 * Real mode exceptions actually use this too, but alternate 1544 * instruction code patches (which end up in the common .text area) 1545 * cannot reach these if they are put there. 1546 */ 1547USE_FIXED_SECTION(virt_trampolines) 1548 MASKED_INTERRUPT() 1549 MASKED_INTERRUPT(H) 1550 1551#ifdef CONFIG_KVM_BOOK3S_64_HANDLER 1552TRAMP_REAL_BEGIN(kvmppc_skip_interrupt) 1553 /* 1554 * Here all GPRs are unchanged from when the interrupt happened 1555 * except for r13, which is saved in SPRG_SCRATCH0. 1556 */ 1557 mfspr r13, SPRN_SRR0 1558 addi r13, r13, 4 1559 mtspr SPRN_SRR0, r13 1560 GET_SCRATCH0(r13) 1561 RFI_TO_KERNEL 1562 b . 1563 1564TRAMP_REAL_BEGIN(kvmppc_skip_Hinterrupt) 1565 /* 1566 * Here all GPRs are unchanged from when the interrupt happened 1567 * except for r13, which is saved in SPRG_SCRATCH0. 1568 */ 1569 mfspr r13, SPRN_HSRR0 1570 addi r13, r13, 4 1571 mtspr SPRN_HSRR0, r13 1572 GET_SCRATCH0(r13) 1573 HRFI_TO_KERNEL 1574 b . 1575#endif 1576 1577/* 1578 * Ensure that any handlers that get invoked from the exception prologs 1579 * above are below the first 64KB (0x10000) of the kernel image because 1580 * the prologs assemble the addresses of these handlers using the 1581 * LOAD_HANDLER macro, which uses an ori instruction. 1582 */ 1583 1584/*** Common interrupt handlers ***/ 1585 1586 1587 /* 1588 * Relocation-on interrupts: A subset of the interrupts can be delivered 1589 * with IR=1/DR=1, if AIL==2 and MSR.HV won't be changed by delivering 1590 * it. Addresses are the same as the original interrupt addresses, but 1591 * offset by 0xc000000000004000. 1592 * It's impossible to receive interrupts below 0x300 via this mechanism. 1593 * KVM: None of these traps are from the guest ; anything that escalated 1594 * to HV=1 from HV=0 is delivered via real mode handlers. 1595 */ 1596 1597 /* 1598 * This uses the standard macro, since the original 0x300 vector 1599 * only has extra guff for STAB-based processors -- which never 1600 * come here. 1601 */ 1602 1603EXC_COMMON_BEGIN(ppc64_runlatch_on_trampoline) 1604 b __ppc64_runlatch_on 1605 1606USE_FIXED_SECTION(virt_trampolines) 1607 /* 1608 * The __end_interrupts marker must be past the out-of-line (OOL) 1609 * handlers, so that they are copied to real address 0x100 when running 1610 * a relocatable kernel. This ensures they can be reached from the short 1611 * trampoline handlers (like 0x4f00, 0x4f20, etc.) which branch 1612 * directly, without using LOAD_HANDLER(). 1613 */ 1614 .align 7 1615 .globl __end_interrupts 1616__end_interrupts: 1617DEFINE_FIXED_SYMBOL(__end_interrupts) 1618 1619#ifdef CONFIG_PPC_970_NAP 1620EXC_COMMON_BEGIN(power4_fixup_nap) 1621 andc r9,r9,r10 1622 std r9,TI_LOCAL_FLAGS(r11) 1623 ld r10,_LINK(r1) /* make idle task do the */ 1624 std r10,_NIP(r1) /* equivalent of a blr */ 1625 blr 1626#endif 1627 1628CLOSE_FIXED_SECTION(real_vectors); 1629CLOSE_FIXED_SECTION(real_trampolines); 1630CLOSE_FIXED_SECTION(virt_vectors); 1631CLOSE_FIXED_SECTION(virt_trampolines); 1632 1633USE_TEXT_SECTION() 1634 1635/* 1636 * Hash table stuff 1637 */ 1638 .balign IFETCH_ALIGN_BYTES 1639do_hash_page: 1640 #ifdef CONFIG_PPC_STD_MMU_64 1641 lis r0,(DSISR_BAD_FAULT_64S|DSISR_DABRMATCH)@h 1642 ori r0,r0,DSISR_BAD_FAULT_64S@l 1643 and. r0,r4,r0 /* weird error? */ 1644 bne- handle_page_fault /* if not, try to insert a HPTE */ 1645 CURRENT_THREAD_INFO(r11, r1) 1646 lwz r0,TI_PREEMPT(r11) /* If we're in an "NMI" */ 1647 andis. r0,r0,NMI_MASK@h /* (i.e. an irq when soft-disabled) */ 1648 bne 77f /* then don't call hash_page now */ 1649 1650 /* 1651 * r3 contains the faulting address 1652 * r4 msr 1653 * r5 contains the trap number 1654 * r6 contains dsisr 1655 * 1656 * at return r3 = 0 for success, 1 for page fault, negative for error 1657 */ 1658 mr r4,r12 1659 ld r6,_DSISR(r1) 1660 bl __hash_page /* build HPTE if possible */ 1661 cmpdi r3,0 /* see if __hash_page succeeded */ 1662 1663 /* Success */ 1664 beq fast_exc_return_irq /* Return from exception on success */ 1665 1666 /* Error */ 1667 blt- 13f 1668 1669 /* Reload DSISR into r4 for the DABR check below */ 1670 ld r4,_DSISR(r1) 1671#endif /* CONFIG_PPC_STD_MMU_64 */ 1672 1673/* Here we have a page fault that hash_page can't handle. */ 1674handle_page_fault: 167511: andis. r0,r4,DSISR_DABRMATCH@h 1676 bne- handle_dabr_fault 1677 ld r4,_DAR(r1) 1678 ld r5,_DSISR(r1) 1679 addi r3,r1,STACK_FRAME_OVERHEAD 1680 bl do_page_fault 1681 cmpdi r3,0 1682 beq+ ret_from_except_lite 1683 bl save_nvgprs 1684 mr r5,r3 1685 addi r3,r1,STACK_FRAME_OVERHEAD 1686 lwz r4,_DAR(r1) 1687 bl bad_page_fault 1688 b ret_from_except 1689 1690/* We have a data breakpoint exception - handle it */ 1691handle_dabr_fault: 1692 bl save_nvgprs 1693 ld r4,_DAR(r1) 1694 ld r5,_DSISR(r1) 1695 addi r3,r1,STACK_FRAME_OVERHEAD 1696 bl do_break 1697 /* 1698 * do_break() may have changed the NV GPRS while handling a breakpoint. 1699 * If so, we need to restore them with their updated values. Don't use 1700 * ret_from_except_lite here. 1701 */ 1702 b ret_from_except 1703 1704 1705#ifdef CONFIG_PPC_STD_MMU_64 1706/* We have a page fault that hash_page could handle but HV refused 1707 * the PTE insertion 1708 */ 170913: bl save_nvgprs 1710 mr r5,r3 1711 addi r3,r1,STACK_FRAME_OVERHEAD 1712 ld r4,_DAR(r1) 1713 bl low_hash_fault 1714 b ret_from_except 1715#endif 1716 1717/* 1718 * We come here as a result of a DSI at a point where we don't want 1719 * to call hash_page, such as when we are accessing memory (possibly 1720 * user memory) inside a PMU interrupt that occurred while interrupts 1721 * were soft-disabled. We want to invoke the exception handler for 1722 * the access, or panic if there isn't a handler. 1723 */ 172477: bl save_nvgprs 1725 mr r4,r3 1726 addi r3,r1,STACK_FRAME_OVERHEAD 1727 li r5,SIGSEGV 1728 bl bad_page_fault 1729 b ret_from_except 1730 1731/* 1732 * Here we have detected that the kernel stack pointer is bad. 1733 * R9 contains the saved CR, r13 points to the paca, 1734 * r10 contains the (bad) kernel stack pointer, 1735 * r11 and r12 contain the saved SRR0 and SRR1. 1736 * We switch to using an emergency stack, save the registers there, 1737 * and call kernel_bad_stack(), which panics. 1738 */ 1739bad_stack: 1740 ld r1,PACAEMERGSP(r13) 1741 subi r1,r1,64+INT_FRAME_SIZE 1742 std r9,_CCR(r1) 1743 std r10,GPR1(r1) 1744 std r11,_NIP(r1) 1745 std r12,_MSR(r1) 1746 mfspr r11,SPRN_DAR 1747 mfspr r12,SPRN_DSISR 1748 std r11,_DAR(r1) 1749 std r12,_DSISR(r1) 1750 mflr r10 1751 mfctr r11 1752 mfxer r12 1753 std r10,_LINK(r1) 1754 std r11,_CTR(r1) 1755 std r12,_XER(r1) 1756 SAVE_GPR(0,r1) 1757 SAVE_GPR(2,r1) 1758 ld r10,EX_R3(r3) 1759 std r10,GPR3(r1) 1760 SAVE_GPR(4,r1) 1761 SAVE_4GPRS(5,r1) 1762 ld r9,EX_R9(r3) 1763 ld r10,EX_R10(r3) 1764 SAVE_2GPRS(9,r1) 1765 ld r9,EX_R11(r3) 1766 ld r10,EX_R12(r3) 1767 ld r11,EX_R13(r3) 1768 std r9,GPR11(r1) 1769 std r10,GPR12(r1) 1770 std r11,GPR13(r1) 1771BEGIN_FTR_SECTION 1772 ld r10,EX_CFAR(r3) 1773 std r10,ORIG_GPR3(r1) 1774END_FTR_SECTION_IFSET(CPU_FTR_CFAR) 1775 SAVE_8GPRS(14,r1) 1776 SAVE_10GPRS(22,r1) 1777 lhz r12,PACA_TRAP_SAVE(r13) 1778 std r12,_TRAP(r1) 1779 addi r11,r1,INT_FRAME_SIZE 1780 std r11,0(r1) 1781 li r12,0 1782 std r12,0(r11) 1783 ld r2,PACATOC(r13) 1784 ld r11,exception_marker@toc(r2) 1785 std r12,RESULT(r1) 1786 std r11,STACK_FRAME_OVERHEAD-16(r1) 17871: addi r3,r1,STACK_FRAME_OVERHEAD 1788 bl kernel_bad_stack 1789 b 1b 1790_ASM_NOKPROBE_SYMBOL(bad_stack); 1791 1792/* 1793 * When doorbell is triggered from system reset wakeup, the message is 1794 * not cleared, so it would fire again when EE is enabled. 1795 * 1796 * When coming from local_irq_enable, there may be the same problem if 1797 * we were hard disabled. 1798 * 1799 * Execute msgclr to clear pending exceptions before handling it. 1800 */ 1801h_doorbell_common_msgclr: 1802 LOAD_REG_IMMEDIATE(r3, PPC_DBELL_MSGTYPE << (63-36)) 1803 PPC_MSGCLR(3) 1804 b h_doorbell_common 1805 1806doorbell_super_common_msgclr: 1807 LOAD_REG_IMMEDIATE(r3, PPC_DBELL_MSGTYPE << (63-36)) 1808 PPC_MSGCLRP(3) 1809 b doorbell_super_common 1810 1811/* 1812 * Called from arch_local_irq_enable when an interrupt needs 1813 * to be resent. r3 contains 0x500, 0x900, 0xa00 or 0xe80 to indicate 1814 * which kind of interrupt. MSR:EE is already off. We generate a 1815 * stackframe like if a real interrupt had happened. 1816 * 1817 * Note: While MSR:EE is off, we need to make sure that _MSR 1818 * in the generated frame has EE set to 1 or the exception 1819 * handler will not properly re-enable them. 1820 * 1821 * Note that we don't specify LR as the NIP (return address) for 1822 * the interrupt because that would unbalance the return branch 1823 * predictor. 1824 */ 1825_GLOBAL(__replay_interrupt) 1826 /* We are going to jump to the exception common code which 1827 * will retrieve various register values from the PACA which 1828 * we don't give a damn about, so we don't bother storing them. 1829 */ 1830 mfmsr r12 1831 LOAD_REG_ADDR(r11, replay_interrupt_return) 1832 mfcr r9 1833 ori r12,r12,MSR_EE 1834 cmpwi r3,0x900 1835 beq decrementer_common 1836 cmpwi r3,0x500 1837BEGIN_FTR_SECTION 1838 beq h_virt_irq_common 1839FTR_SECTION_ELSE 1840 beq hardware_interrupt_common 1841ALT_FTR_SECTION_END_IFSET(CPU_FTR_HVMODE | CPU_FTR_ARCH_300) 1842BEGIN_FTR_SECTION 1843 cmpwi r3,0xa00 1844 beq h_doorbell_common_msgclr 1845 cmpwi r3,0xe60 1846 beq hmi_exception_common 1847FTR_SECTION_ELSE 1848 cmpwi r3,0xa00 1849 beq doorbell_super_common_msgclr 1850ALT_FTR_SECTION_END_IFSET(CPU_FTR_HVMODE) 1851replay_interrupt_return: 1852 blr 1853 1854_ASM_NOKPROBE_SYMBOL(__replay_interrupt) 1855