1/* SPDX-License-Identifier: GPL-2.0 */ 2/* 3 * Copyright IBM Corp 2000, 2011 4 * Author(s): Holger Smolinski <Holger.Smolinski@de.ibm.com>, 5 * Denis Joseph Barrow, 6 */ 7 8#include <linux/linkage.h> 9#include <asm/asm-offsets.h> 10#include <asm/nospec-insn.h> 11#include <asm/sigp.h> 12 13 GEN_BR_THUNK %r9 14 15# 16# Issue "store status" for the current CPU to its prefix page 17# and call passed function afterwards 18# 19# r2 = Function to be called after store status 20# r3 = Parameter for function 21# 22ENTRY(store_status) 23 /* Save register one and load save area base */ 24 stg %r1,__LC_SAVE_AREA_RESTART 25 /* General purpose registers */ 26 lghi %r1,__LC_GPREGS_SAVE_AREA 27 stmg %r0,%r15,0(%r1) 28 mvc 8(8,%r1),__LC_SAVE_AREA_RESTART 29 /* Control registers */ 30 lghi %r1,__LC_CREGS_SAVE_AREA 31 stctg %c0,%c15,0(%r1) 32 /* Access registers */ 33 lghi %r1,__LC_AREGS_SAVE_AREA 34 stam %a0,%a15,0(%r1) 35 /* Floating point registers */ 36 lghi %r1,__LC_FPREGS_SAVE_AREA 37 std %f0, 0x00(%r1) 38 std %f1, 0x08(%r1) 39 std %f2, 0x10(%r1) 40 std %f3, 0x18(%r1) 41 std %f4, 0x20(%r1) 42 std %f5, 0x28(%r1) 43 std %f6, 0x30(%r1) 44 std %f7, 0x38(%r1) 45 std %f8, 0x40(%r1) 46 std %f9, 0x48(%r1) 47 std %f10,0x50(%r1) 48 std %f11,0x58(%r1) 49 std %f12,0x60(%r1) 50 std %f13,0x68(%r1) 51 std %f14,0x70(%r1) 52 std %f15,0x78(%r1) 53 /* Floating point control register */ 54 lghi %r1,__LC_FP_CREG_SAVE_AREA 55 stfpc 0(%r1) 56 /* CPU timer */ 57 lghi %r1,__LC_CPU_TIMER_SAVE_AREA 58 stpt 0(%r1) 59 /* Store prefix register */ 60 lghi %r1,__LC_PREFIX_SAVE_AREA 61 stpx 0(%r1) 62 /* Clock comparator - seven bytes */ 63 lghi %r1,__LC_CLOCK_COMP_SAVE_AREA 64 larl %r4,.Lclkcmp 65 stckc 0(%r4) 66 mvc 1(7,%r1),1(%r4) 67 /* Program status word */ 68 lghi %r1,__LC_PSW_SAVE_AREA 69 epsw %r4,%r5 70 st %r4,0(%r1) 71 st %r5,4(%r1) 72 stg %r2,8(%r1) 73 lgr %r9,%r2 74 lgr %r2,%r3 75 BR_EX %r9 76 77 .section .bss 78 .align 8 79.Lclkcmp: .quad 0x0000000000000000 80 .previous 81 82# 83# do_reipl_asm 84# Parameter: r2 = schid of reipl device 85# 86 87ENTRY(do_reipl_asm) 88 basr %r13,0 89.Lpg0: lpswe .Lnewpsw-.Lpg0(%r13) 90.Lpg1: lgr %r3,%r2 91 larl %r2,.Lstatus 92 brasl %r14,store_status 93 94.Lstatus: lctlg %c6,%c6,.Lall-.Lpg0(%r13) 95 lgr %r1,%r2 96 mvc __LC_PGM_NEW_PSW(16),.Lpcnew-.Lpg0(%r13) 97 stsch .Lschib-.Lpg0(%r13) 98 oi .Lschib+5-.Lpg0(%r13),0x84 99.Lecs: xi .Lschib+27-.Lpg0(%r13),0x01 100 msch .Lschib-.Lpg0(%r13) 101 lghi %r0,5 102.Lssch: ssch .Liplorb-.Lpg0(%r13) 103 jz .L001 104 brct %r0,.Lssch 105 bas %r14,.Ldisab-.Lpg0(%r13) 106.L001: mvc __LC_IO_NEW_PSW(16),.Lionew-.Lpg0(%r13) 107.Ltpi: lpswe .Lwaitpsw-.Lpg0(%r13) 108.Lcont: c %r1,__LC_SUBCHANNEL_ID 109 jnz .Ltpi 110 clc __LC_IO_INT_PARM(4),.Liplorb-.Lpg0(%r13) 111 jnz .Ltpi 112 tsch .Liplirb-.Lpg0(%r13) 113 tm .Liplirb+9-.Lpg0(%r13),0xbf 114 jz .L002 115 bas %r14,.Ldisab-.Lpg0(%r13) 116.L002: tm .Liplirb+8-.Lpg0(%r13),0xf3 117 jz .L003 118 bas %r14,.Ldisab-.Lpg0(%r13) 119.L003: st %r1,__LC_SUBCHANNEL_ID 120 lhi %r1,0 # mode 0 = esa 121 slr %r0,%r0 # set cpuid to zero 122 sigp %r1,%r0,SIGP_SET_ARCHITECTURE # switch to esa mode 123 lpsw 0 124.Ldisab: sll %r14,1 125 srl %r14,1 # need to kill hi bit to avoid specification exceptions. 126 st %r14,.Ldispsw+12-.Lpg0(%r13) 127 lpswe .Ldispsw-.Lpg0(%r13) 128 .align 8 129.Lall: .quad 0x00000000ff000000 130 .align 16 131/* 132 * These addresses have to be 31 bit otherwise 133 * the sigp will throw a specifcation exception 134 * when switching to ESA mode as bit 31 be set 135 * in the ESA psw. 136 * Bit 31 of the addresses has to be 0 for the 137 * 31bit lpswe instruction a fact they appear to have 138 * omitted from the pop. 139 */ 140.Lnewpsw: .quad 0x0000000080000000 141 .quad .Lpg1 142.Lpcnew: .quad 0x0000000080000000 143 .quad .Lecs 144.Lionew: .quad 0x0000000080000000 145 .quad .Lcont 146.Lwaitpsw: .quad 0x0202000080000000 147 .quad .Ltpi 148.Ldispsw: .quad 0x0002000080000000 149 .quad 0x0000000000000000 150.Liplccws: .long 0x02000000,0x60000018 151 .long 0x08000008,0x20000001 152.Liplorb: .long 0x0049504c,0x0040ff80 153 .long 0x00000000+.Liplccws 154.Lschib: .long 0x00000000,0x00000000 155 .long 0x00000000,0x00000000 156 .long 0x00000000,0x00000000 157 .long 0x00000000,0x00000000 158 .long 0x00000000,0x00000000 159 .long 0x00000000,0x00000000 160.Liplirb: .long 0x00000000,0x00000000 161 .long 0x00000000,0x00000000 162 .long 0x00000000,0x00000000 163 .long 0x00000000,0x00000000 164 .long 0x00000000,0x00000000 165 .long 0x00000000,0x00000000 166 .long 0x00000000,0x00000000 167 .long 0x00000000,0x00000000 168