1 /* SPDX-License-Identifier: GPL-2.0 */
2 #ifndef __SPARC64_MMU_CONTEXT_H
3 #define __SPARC64_MMU_CONTEXT_H
4
5 /* Derived heavily from Linus's Alpha/AXP ASN code... */
6
7 #ifndef __ASSEMBLY__
8
9 #include <linux/spinlock.h>
10 #include <linux/mm_types.h>
11 #include <linux/smp.h>
12
13 #include <asm/spitfire.h>
14 #include <asm-generic/mm_hooks.h>
15 #include <asm/percpu.h>
16
enter_lazy_tlb(struct mm_struct * mm,struct task_struct * tsk)17 static inline void enter_lazy_tlb(struct mm_struct *mm, struct task_struct *tsk)
18 {
19 }
20
21 extern spinlock_t ctx_alloc_lock;
22 extern unsigned long tlb_context_cache;
23 extern unsigned long mmu_context_bmap[];
24
25 DECLARE_PER_CPU(struct mm_struct *, per_cpu_secondary_mm);
26 void get_new_mmu_context(struct mm_struct *mm);
27 int init_new_context(struct task_struct *tsk, struct mm_struct *mm);
28 void destroy_context(struct mm_struct *mm);
29
30 void __tsb_context_switch(unsigned long pgd_pa,
31 struct tsb_config *tsb_base,
32 struct tsb_config *tsb_huge,
33 unsigned long tsb_descr_pa,
34 unsigned long secondary_ctx);
35
tsb_context_switch_ctx(struct mm_struct * mm,unsigned long ctx)36 static inline void tsb_context_switch_ctx(struct mm_struct *mm,
37 unsigned long ctx)
38 {
39 __tsb_context_switch(__pa(mm->pgd),
40 &mm->context.tsb_block[MM_TSB_BASE],
41 #if defined(CONFIG_HUGETLB_PAGE) || defined(CONFIG_TRANSPARENT_HUGEPAGE)
42 (mm->context.tsb_block[MM_TSB_HUGE].tsb ?
43 &mm->context.tsb_block[MM_TSB_HUGE] :
44 NULL)
45 #else
46 NULL
47 #endif
48 , __pa(&mm->context.tsb_descr[MM_TSB_BASE]),
49 ctx);
50 }
51
52 #define tsb_context_switch(X) tsb_context_switch_ctx(X, 0)
53
54 void tsb_grow(struct mm_struct *mm,
55 unsigned long tsb_index,
56 unsigned long mm_rss);
57 #ifdef CONFIG_SMP
58 void smp_tsb_sync(struct mm_struct *mm);
59 #else
60 #define smp_tsb_sync(__mm) do { } while (0)
61 #endif
62
63 /* Set MMU context in the actual hardware. */
64 #define load_secondary_context(__mm) \
65 __asm__ __volatile__( \
66 "\n661: stxa %0, [%1] %2\n" \
67 " .section .sun4v_1insn_patch, \"ax\"\n" \
68 " .word 661b\n" \
69 " stxa %0, [%1] %3\n" \
70 " .previous\n" \
71 " flush %%g6\n" \
72 : /* No outputs */ \
73 : "r" (CTX_HWBITS((__mm)->context)), \
74 "r" (SECONDARY_CONTEXT), "i" (ASI_DMMU), "i" (ASI_MMU))
75
76 void __flush_tlb_mm(unsigned long, unsigned long);
77
78 /* Switch the current MM context. */
switch_mm(struct mm_struct * old_mm,struct mm_struct * mm,struct task_struct * tsk)79 static inline void switch_mm(struct mm_struct *old_mm, struct mm_struct *mm, struct task_struct *tsk)
80 {
81 unsigned long ctx_valid, flags;
82 int cpu = smp_processor_id();
83
84 per_cpu(per_cpu_secondary_mm, cpu) = mm;
85 if (unlikely(mm == &init_mm))
86 return;
87
88 spin_lock_irqsave(&mm->context.lock, flags);
89 ctx_valid = CTX_VALID(mm->context);
90 if (!ctx_valid)
91 get_new_mmu_context(mm);
92
93 /* We have to be extremely careful here or else we will miss
94 * a TSB grow if we switch back and forth between a kernel
95 * thread and an address space which has it's TSB size increased
96 * on another processor.
97 *
98 * It is possible to play some games in order to optimize the
99 * switch, but the safest thing to do is to unconditionally
100 * perform the secondary context load and the TSB context switch.
101 *
102 * For reference the bad case is, for address space "A":
103 *
104 * CPU 0 CPU 1
105 * run address space A
106 * set cpu0's bits in cpu_vm_mask
107 * switch to kernel thread, borrow
108 * address space A via entry_lazy_tlb
109 * run address space A
110 * set cpu1's bit in cpu_vm_mask
111 * flush_tlb_pending()
112 * reset cpu_vm_mask to just cpu1
113 * TSB grow
114 * run address space A
115 * context was valid, so skip
116 * TSB context switch
117 *
118 * At that point cpu0 continues to use a stale TSB, the one from
119 * before the TSB grow performed on cpu1. cpu1 did not cross-call
120 * cpu0 to update it's TSB because at that point the cpu_vm_mask
121 * only had cpu1 set in it.
122 */
123 tsb_context_switch_ctx(mm, CTX_HWBITS(mm->context));
124
125 /* Any time a processor runs a context on an address space
126 * for the first time, we must flush that context out of the
127 * local TLB.
128 */
129 if (!ctx_valid || !cpumask_test_cpu(cpu, mm_cpumask(mm))) {
130 cpumask_set_cpu(cpu, mm_cpumask(mm));
131 __flush_tlb_mm(CTX_HWBITS(mm->context),
132 SECONDARY_CONTEXT);
133 }
134 spin_unlock_irqrestore(&mm->context.lock, flags);
135 }
136
137 #define deactivate_mm(tsk,mm) do { } while (0)
138 #define activate_mm(active_mm, mm) switch_mm(active_mm, mm, NULL)
139 #endif /* !(__ASSEMBLY__) */
140
141 #endif /* !(__SPARC64_MMU_CONTEXT_H) */
142