1 /*
2 * Performance events - AMD IBS
3 *
4 * Copyright (C) 2011 Advanced Micro Devices, Inc., Robert Richter
5 *
6 * For licencing details see kernel-base/COPYING
7 */
8
9 #include <linux/perf_event.h>
10 #include <linux/init.h>
11 #include <linux/export.h>
12 #include <linux/pci.h>
13 #include <linux/ptrace.h>
14 #include <linux/syscore_ops.h>
15 #include <linux/sched/clock.h>
16
17 #include <asm/apic.h>
18
19 #include "../perf_event.h"
20
21 static u32 ibs_caps;
22
23 #if defined(CONFIG_PERF_EVENTS) && defined(CONFIG_CPU_SUP_AMD)
24
25 #include <linux/kprobes.h>
26 #include <linux/hardirq.h>
27
28 #include <asm/nmi.h>
29
30 #define IBS_FETCH_CONFIG_MASK (IBS_FETCH_RAND_EN | IBS_FETCH_MAX_CNT)
31 #define IBS_OP_CONFIG_MASK IBS_OP_MAX_CNT
32
33
34 /*
35 * IBS states:
36 *
37 * ENABLED; tracks the pmu::add(), pmu::del() state, when set the counter is taken
38 * and any further add()s must fail.
39 *
40 * STARTED/STOPPING/STOPPED; deal with pmu::start(), pmu::stop() state but are
41 * complicated by the fact that the IBS hardware can send late NMIs (ie. after
42 * we've cleared the EN bit).
43 *
44 * In order to consume these late NMIs we have the STOPPED state, any NMI that
45 * happens after we've cleared the EN state will clear this bit and report the
46 * NMI handled (this is fundamentally racy in the face or multiple NMI sources,
47 * someone else can consume our BIT and our NMI will go unhandled).
48 *
49 * And since we cannot set/clear this separate bit together with the EN bit,
50 * there are races; if we cleared STARTED early, an NMI could land in
51 * between clearing STARTED and clearing the EN bit (in fact multiple NMIs
52 * could happen if the period is small enough), and consume our STOPPED bit
53 * and trigger streams of unhandled NMIs.
54 *
55 * If, however, we clear STARTED late, an NMI can hit between clearing the
56 * EN bit and clearing STARTED, still see STARTED set and process the event.
57 * If this event will have the VALID bit clear, we bail properly, but this
58 * is not a given. With VALID set we can end up calling pmu::stop() again
59 * (the throttle logic) and trigger the WARNs in there.
60 *
61 * So what we do is set STOPPING before clearing EN to avoid the pmu::stop()
62 * nesting, and clear STARTED late, so that we have a well defined state over
63 * the clearing of the EN bit.
64 *
65 * XXX: we could probably be using !atomic bitops for all this.
66 */
67
68 enum ibs_states {
69 IBS_ENABLED = 0,
70 IBS_STARTED = 1,
71 IBS_STOPPING = 2,
72 IBS_STOPPED = 3,
73
74 IBS_MAX_STATES,
75 };
76
77 struct cpu_perf_ibs {
78 struct perf_event *event;
79 unsigned long state[BITS_TO_LONGS(IBS_MAX_STATES)];
80 };
81
82 struct perf_ibs {
83 struct pmu pmu;
84 unsigned int msr;
85 u64 config_mask;
86 u64 cnt_mask;
87 u64 enable_mask;
88 u64 valid_mask;
89 u64 max_period;
90 unsigned long offset_mask[1];
91 int offset_max;
92 struct cpu_perf_ibs __percpu *pcpu;
93
94 struct attribute **format_attrs;
95 struct attribute_group format_group;
96 const struct attribute_group *attr_groups[2];
97
98 u64 (*get_count)(u64 config);
99 };
100
101 struct perf_ibs_data {
102 u32 size;
103 union {
104 u32 data[0]; /* data buffer starts here */
105 u32 caps;
106 };
107 u64 regs[MSR_AMD64_IBS_REG_COUNT_MAX];
108 };
109
110 static int
perf_event_set_period(struct hw_perf_event * hwc,u64 min,u64 max,u64 * hw_period)111 perf_event_set_period(struct hw_perf_event *hwc, u64 min, u64 max, u64 *hw_period)
112 {
113 s64 left = local64_read(&hwc->period_left);
114 s64 period = hwc->sample_period;
115 int overflow = 0;
116
117 /*
118 * If we are way outside a reasonable range then just skip forward:
119 */
120 if (unlikely(left <= -period)) {
121 left = period;
122 local64_set(&hwc->period_left, left);
123 hwc->last_period = period;
124 overflow = 1;
125 }
126
127 if (unlikely(left < (s64)min)) {
128 left += period;
129 local64_set(&hwc->period_left, left);
130 hwc->last_period = period;
131 overflow = 1;
132 }
133
134 /*
135 * If the hw period that triggers the sw overflow is too short
136 * we might hit the irq handler. This biases the results.
137 * Thus we shorten the next-to-last period and set the last
138 * period to the max period.
139 */
140 if (left > max) {
141 left -= max;
142 if (left > max)
143 left = max;
144 else if (left < min)
145 left = min;
146 }
147
148 *hw_period = (u64)left;
149
150 return overflow;
151 }
152
153 static int
perf_event_try_update(struct perf_event * event,u64 new_raw_count,int width)154 perf_event_try_update(struct perf_event *event, u64 new_raw_count, int width)
155 {
156 struct hw_perf_event *hwc = &event->hw;
157 int shift = 64 - width;
158 u64 prev_raw_count;
159 u64 delta;
160
161 /*
162 * Careful: an NMI might modify the previous event value.
163 *
164 * Our tactic to handle this is to first atomically read and
165 * exchange a new raw count - then add that new-prev delta
166 * count to the generic event atomically:
167 */
168 prev_raw_count = local64_read(&hwc->prev_count);
169 if (local64_cmpxchg(&hwc->prev_count, prev_raw_count,
170 new_raw_count) != prev_raw_count)
171 return 0;
172
173 /*
174 * Now we have the new raw value and have updated the prev
175 * timestamp already. We can now calculate the elapsed delta
176 * (event-)time and add that to the generic event.
177 *
178 * Careful, not all hw sign-extends above the physical width
179 * of the count.
180 */
181 delta = (new_raw_count << shift) - (prev_raw_count << shift);
182 delta >>= shift;
183
184 local64_add(delta, &event->count);
185 local64_sub(delta, &hwc->period_left);
186
187 return 1;
188 }
189
190 static struct perf_ibs perf_ibs_fetch;
191 static struct perf_ibs perf_ibs_op;
192
get_ibs_pmu(int type)193 static struct perf_ibs *get_ibs_pmu(int type)
194 {
195 if (perf_ibs_fetch.pmu.type == type)
196 return &perf_ibs_fetch;
197 if (perf_ibs_op.pmu.type == type)
198 return &perf_ibs_op;
199 return NULL;
200 }
201
202 /*
203 * Use IBS for precise event sampling:
204 *
205 * perf record -a -e cpu-cycles:p ... # use ibs op counting cycle count
206 * perf record -a -e r076:p ... # same as -e cpu-cycles:p
207 * perf record -a -e r0C1:p ... # use ibs op counting micro-ops
208 *
209 * IbsOpCntCtl (bit 19) of IBS Execution Control Register (IbsOpCtl,
210 * MSRC001_1033) is used to select either cycle or micro-ops counting
211 * mode.
212 *
213 * The rip of IBS samples has skid 0. Thus, IBS supports precise
214 * levels 1 and 2 and the PERF_EFLAGS_EXACT is set. In rare cases the
215 * rip is invalid when IBS was not able to record the rip correctly.
216 * We clear PERF_EFLAGS_EXACT and take the rip from pt_regs then.
217 *
218 */
perf_ibs_precise_event(struct perf_event * event,u64 * config)219 static int perf_ibs_precise_event(struct perf_event *event, u64 *config)
220 {
221 switch (event->attr.precise_ip) {
222 case 0:
223 return -ENOENT;
224 case 1:
225 case 2:
226 break;
227 default:
228 return -EOPNOTSUPP;
229 }
230
231 switch (event->attr.type) {
232 case PERF_TYPE_HARDWARE:
233 switch (event->attr.config) {
234 case PERF_COUNT_HW_CPU_CYCLES:
235 *config = 0;
236 return 0;
237 }
238 break;
239 case PERF_TYPE_RAW:
240 switch (event->attr.config) {
241 case 0x0076:
242 *config = 0;
243 return 0;
244 case 0x00C1:
245 *config = IBS_OP_CNT_CTL;
246 return 0;
247 }
248 break;
249 default:
250 return -ENOENT;
251 }
252
253 return -EOPNOTSUPP;
254 }
255
256 static const struct perf_event_attr ibs_notsupp = {
257 .exclude_user = 1,
258 .exclude_kernel = 1,
259 .exclude_hv = 1,
260 .exclude_idle = 1,
261 .exclude_host = 1,
262 .exclude_guest = 1,
263 };
264
perf_ibs_init(struct perf_event * event)265 static int perf_ibs_init(struct perf_event *event)
266 {
267 struct hw_perf_event *hwc = &event->hw;
268 struct perf_ibs *perf_ibs;
269 u64 max_cnt, config;
270 int ret;
271
272 perf_ibs = get_ibs_pmu(event->attr.type);
273 if (perf_ibs) {
274 config = event->attr.config;
275 } else {
276 perf_ibs = &perf_ibs_op;
277 ret = perf_ibs_precise_event(event, &config);
278 if (ret)
279 return ret;
280 }
281
282 if (event->pmu != &perf_ibs->pmu)
283 return -ENOENT;
284
285 if (perf_flags(&event->attr) & perf_flags(&ibs_notsupp))
286 return -EINVAL;
287
288 if (config & ~perf_ibs->config_mask)
289 return -EINVAL;
290
291 if (hwc->sample_period) {
292 if (config & perf_ibs->cnt_mask)
293 /* raw max_cnt may not be set */
294 return -EINVAL;
295 if (!event->attr.sample_freq && hwc->sample_period & 0x0f)
296 /*
297 * lower 4 bits can not be set in ibs max cnt,
298 * but allowing it in case we adjust the
299 * sample period to set a frequency.
300 */
301 return -EINVAL;
302 hwc->sample_period &= ~0x0FULL;
303 if (!hwc->sample_period)
304 hwc->sample_period = 0x10;
305 } else {
306 max_cnt = config & perf_ibs->cnt_mask;
307 config &= ~perf_ibs->cnt_mask;
308 event->attr.sample_period = max_cnt << 4;
309 hwc->sample_period = event->attr.sample_period;
310 }
311
312 if (!hwc->sample_period)
313 return -EINVAL;
314
315 /*
316 * If we modify hwc->sample_period, we also need to update
317 * hwc->last_period and hwc->period_left.
318 */
319 hwc->last_period = hwc->sample_period;
320 local64_set(&hwc->period_left, hwc->sample_period);
321
322 hwc->config_base = perf_ibs->msr;
323 hwc->config = config;
324
325 return 0;
326 }
327
perf_ibs_set_period(struct perf_ibs * perf_ibs,struct hw_perf_event * hwc,u64 * period)328 static int perf_ibs_set_period(struct perf_ibs *perf_ibs,
329 struct hw_perf_event *hwc, u64 *period)
330 {
331 int overflow;
332
333 /* ignore lower 4 bits in min count: */
334 overflow = perf_event_set_period(hwc, 1<<4, perf_ibs->max_period, period);
335 local64_set(&hwc->prev_count, 0);
336
337 return overflow;
338 }
339
get_ibs_fetch_count(u64 config)340 static u64 get_ibs_fetch_count(u64 config)
341 {
342 return (config & IBS_FETCH_CNT) >> 12;
343 }
344
get_ibs_op_count(u64 config)345 static u64 get_ibs_op_count(u64 config)
346 {
347 u64 count = 0;
348
349 if (config & IBS_OP_VAL)
350 count += (config & IBS_OP_MAX_CNT) << 4; /* cnt rolled over */
351
352 if (ibs_caps & IBS_CAPS_RDWROPCNT)
353 count += (config & IBS_OP_CUR_CNT) >> 32;
354
355 return count;
356 }
357
358 static void
perf_ibs_event_update(struct perf_ibs * perf_ibs,struct perf_event * event,u64 * config)359 perf_ibs_event_update(struct perf_ibs *perf_ibs, struct perf_event *event,
360 u64 *config)
361 {
362 u64 count = perf_ibs->get_count(*config);
363
364 /*
365 * Set width to 64 since we do not overflow on max width but
366 * instead on max count. In perf_ibs_set_period() we clear
367 * prev count manually on overflow.
368 */
369 while (!perf_event_try_update(event, count, 64)) {
370 rdmsrl(event->hw.config_base, *config);
371 count = perf_ibs->get_count(*config);
372 }
373 }
374
perf_ibs_enable_event(struct perf_ibs * perf_ibs,struct hw_perf_event * hwc,u64 config)375 static inline void perf_ibs_enable_event(struct perf_ibs *perf_ibs,
376 struct hw_perf_event *hwc, u64 config)
377 {
378 wrmsrl(hwc->config_base, hwc->config | config | perf_ibs->enable_mask);
379 }
380
381 /*
382 * Erratum #420 Instruction-Based Sampling Engine May Generate
383 * Interrupt that Cannot Be Cleared:
384 *
385 * Must clear counter mask first, then clear the enable bit. See
386 * Revision Guide for AMD Family 10h Processors, Publication #41322.
387 */
perf_ibs_disable_event(struct perf_ibs * perf_ibs,struct hw_perf_event * hwc,u64 config)388 static inline void perf_ibs_disable_event(struct perf_ibs *perf_ibs,
389 struct hw_perf_event *hwc, u64 config)
390 {
391 config &= ~perf_ibs->cnt_mask;
392 if (boot_cpu_data.x86 == 0x10)
393 wrmsrl(hwc->config_base, config);
394 config &= ~perf_ibs->enable_mask;
395 wrmsrl(hwc->config_base, config);
396 }
397
398 /*
399 * We cannot restore the ibs pmu state, so we always needs to update
400 * the event while stopping it and then reset the state when starting
401 * again. Thus, ignoring PERF_EF_RELOAD and PERF_EF_UPDATE flags in
402 * perf_ibs_start()/perf_ibs_stop() and instead always do it.
403 */
perf_ibs_start(struct perf_event * event,int flags)404 static void perf_ibs_start(struct perf_event *event, int flags)
405 {
406 struct hw_perf_event *hwc = &event->hw;
407 struct perf_ibs *perf_ibs = container_of(event->pmu, struct perf_ibs, pmu);
408 struct cpu_perf_ibs *pcpu = this_cpu_ptr(perf_ibs->pcpu);
409 u64 period;
410
411 if (WARN_ON_ONCE(!(hwc->state & PERF_HES_STOPPED)))
412 return;
413
414 WARN_ON_ONCE(!(hwc->state & PERF_HES_UPTODATE));
415 hwc->state = 0;
416
417 perf_ibs_set_period(perf_ibs, hwc, &period);
418 /*
419 * Set STARTED before enabling the hardware, such that a subsequent NMI
420 * must observe it.
421 */
422 set_bit(IBS_STARTED, pcpu->state);
423 clear_bit(IBS_STOPPING, pcpu->state);
424 perf_ibs_enable_event(perf_ibs, hwc, period >> 4);
425
426 perf_event_update_userpage(event);
427 }
428
perf_ibs_stop(struct perf_event * event,int flags)429 static void perf_ibs_stop(struct perf_event *event, int flags)
430 {
431 struct hw_perf_event *hwc = &event->hw;
432 struct perf_ibs *perf_ibs = container_of(event->pmu, struct perf_ibs, pmu);
433 struct cpu_perf_ibs *pcpu = this_cpu_ptr(perf_ibs->pcpu);
434 u64 config;
435 int stopping;
436
437 if (test_and_set_bit(IBS_STOPPING, pcpu->state))
438 return;
439
440 stopping = test_bit(IBS_STARTED, pcpu->state);
441
442 if (!stopping && (hwc->state & PERF_HES_UPTODATE))
443 return;
444
445 rdmsrl(hwc->config_base, config);
446
447 if (stopping) {
448 /*
449 * Set STOPPED before disabling the hardware, such that it
450 * must be visible to NMIs the moment we clear the EN bit,
451 * at which point we can generate an !VALID sample which
452 * we need to consume.
453 */
454 set_bit(IBS_STOPPED, pcpu->state);
455 perf_ibs_disable_event(perf_ibs, hwc, config);
456 /*
457 * Clear STARTED after disabling the hardware; if it were
458 * cleared before an NMI hitting after the clear but before
459 * clearing the EN bit might think it a spurious NMI and not
460 * handle it.
461 *
462 * Clearing it after, however, creates the problem of the NMI
463 * handler seeing STARTED but not having a valid sample.
464 */
465 clear_bit(IBS_STARTED, pcpu->state);
466 WARN_ON_ONCE(hwc->state & PERF_HES_STOPPED);
467 hwc->state |= PERF_HES_STOPPED;
468 }
469
470 if (hwc->state & PERF_HES_UPTODATE)
471 return;
472
473 /*
474 * Clear valid bit to not count rollovers on update, rollovers
475 * are only updated in the irq handler.
476 */
477 config &= ~perf_ibs->valid_mask;
478
479 perf_ibs_event_update(perf_ibs, event, &config);
480 hwc->state |= PERF_HES_UPTODATE;
481 }
482
perf_ibs_add(struct perf_event * event,int flags)483 static int perf_ibs_add(struct perf_event *event, int flags)
484 {
485 struct perf_ibs *perf_ibs = container_of(event->pmu, struct perf_ibs, pmu);
486 struct cpu_perf_ibs *pcpu = this_cpu_ptr(perf_ibs->pcpu);
487
488 if (test_and_set_bit(IBS_ENABLED, pcpu->state))
489 return -ENOSPC;
490
491 event->hw.state = PERF_HES_UPTODATE | PERF_HES_STOPPED;
492
493 pcpu->event = event;
494
495 if (flags & PERF_EF_START)
496 perf_ibs_start(event, PERF_EF_RELOAD);
497
498 return 0;
499 }
500
perf_ibs_del(struct perf_event * event,int flags)501 static void perf_ibs_del(struct perf_event *event, int flags)
502 {
503 struct perf_ibs *perf_ibs = container_of(event->pmu, struct perf_ibs, pmu);
504 struct cpu_perf_ibs *pcpu = this_cpu_ptr(perf_ibs->pcpu);
505
506 if (!test_and_clear_bit(IBS_ENABLED, pcpu->state))
507 return;
508
509 perf_ibs_stop(event, PERF_EF_UPDATE);
510
511 pcpu->event = NULL;
512
513 perf_event_update_userpage(event);
514 }
515
perf_ibs_read(struct perf_event * event)516 static void perf_ibs_read(struct perf_event *event) { }
517
518 PMU_FORMAT_ATTR(rand_en, "config:57");
519 PMU_FORMAT_ATTR(cnt_ctl, "config:19");
520
521 static struct attribute *ibs_fetch_format_attrs[] = {
522 &format_attr_rand_en.attr,
523 NULL,
524 };
525
526 static struct attribute *ibs_op_format_attrs[] = {
527 NULL, /* &format_attr_cnt_ctl.attr if IBS_CAPS_OPCNT */
528 NULL,
529 };
530
531 static struct perf_ibs perf_ibs_fetch = {
532 .pmu = {
533 .task_ctx_nr = perf_invalid_context,
534
535 .event_init = perf_ibs_init,
536 .add = perf_ibs_add,
537 .del = perf_ibs_del,
538 .start = perf_ibs_start,
539 .stop = perf_ibs_stop,
540 .read = perf_ibs_read,
541 },
542 .msr = MSR_AMD64_IBSFETCHCTL,
543 .config_mask = IBS_FETCH_CONFIG_MASK,
544 .cnt_mask = IBS_FETCH_MAX_CNT,
545 .enable_mask = IBS_FETCH_ENABLE,
546 .valid_mask = IBS_FETCH_VAL,
547 .max_period = IBS_FETCH_MAX_CNT << 4,
548 .offset_mask = { MSR_AMD64_IBSFETCH_REG_MASK },
549 .offset_max = MSR_AMD64_IBSFETCH_REG_COUNT,
550 .format_attrs = ibs_fetch_format_attrs,
551
552 .get_count = get_ibs_fetch_count,
553 };
554
555 static struct perf_ibs perf_ibs_op = {
556 .pmu = {
557 .task_ctx_nr = perf_invalid_context,
558
559 .event_init = perf_ibs_init,
560 .add = perf_ibs_add,
561 .del = perf_ibs_del,
562 .start = perf_ibs_start,
563 .stop = perf_ibs_stop,
564 .read = perf_ibs_read,
565 },
566 .msr = MSR_AMD64_IBSOPCTL,
567 .config_mask = IBS_OP_CONFIG_MASK,
568 .cnt_mask = IBS_OP_MAX_CNT | IBS_OP_CUR_CNT |
569 IBS_OP_CUR_CNT_RAND,
570 .enable_mask = IBS_OP_ENABLE,
571 .valid_mask = IBS_OP_VAL,
572 .max_period = IBS_OP_MAX_CNT << 4,
573 .offset_mask = { MSR_AMD64_IBSOP_REG_MASK },
574 .offset_max = MSR_AMD64_IBSOP_REG_COUNT,
575 .format_attrs = ibs_op_format_attrs,
576
577 .get_count = get_ibs_op_count,
578 };
579
perf_ibs_handle_irq(struct perf_ibs * perf_ibs,struct pt_regs * iregs)580 static int perf_ibs_handle_irq(struct perf_ibs *perf_ibs, struct pt_regs *iregs)
581 {
582 struct cpu_perf_ibs *pcpu = this_cpu_ptr(perf_ibs->pcpu);
583 struct perf_event *event = pcpu->event;
584 struct hw_perf_event *hwc;
585 struct perf_sample_data data;
586 struct perf_raw_record raw;
587 struct pt_regs regs;
588 struct perf_ibs_data ibs_data;
589 int offset, size, check_rip, offset_max, throttle = 0;
590 unsigned int msr;
591 u64 *buf, *config, period;
592
593 if (!test_bit(IBS_STARTED, pcpu->state)) {
594 fail:
595 /*
596 * Catch spurious interrupts after stopping IBS: After
597 * disabling IBS there could be still incoming NMIs
598 * with samples that even have the valid bit cleared.
599 * Mark all this NMIs as handled.
600 */
601 if (test_and_clear_bit(IBS_STOPPED, pcpu->state))
602 return 1;
603
604 return 0;
605 }
606
607 if (WARN_ON_ONCE(!event))
608 goto fail;
609
610 hwc = &event->hw;
611 msr = hwc->config_base;
612 buf = ibs_data.regs;
613 rdmsrl(msr, *buf);
614 if (!(*buf++ & perf_ibs->valid_mask))
615 goto fail;
616
617 config = &ibs_data.regs[0];
618 perf_ibs_event_update(perf_ibs, event, config);
619 perf_sample_data_init(&data, 0, hwc->last_period);
620 if (!perf_ibs_set_period(perf_ibs, hwc, &period))
621 goto out; /* no sw counter overflow */
622
623 ibs_data.caps = ibs_caps;
624 size = 1;
625 offset = 1;
626 check_rip = (perf_ibs == &perf_ibs_op && (ibs_caps & IBS_CAPS_RIPINVALIDCHK));
627 if (event->attr.sample_type & PERF_SAMPLE_RAW)
628 offset_max = perf_ibs->offset_max;
629 else if (check_rip)
630 offset_max = 3;
631 else
632 offset_max = 1;
633 do {
634 rdmsrl(msr + offset, *buf++);
635 size++;
636 offset = find_next_bit(perf_ibs->offset_mask,
637 perf_ibs->offset_max,
638 offset + 1);
639 } while (offset < offset_max);
640 if (event->attr.sample_type & PERF_SAMPLE_RAW) {
641 /*
642 * Read IbsBrTarget and IbsOpData4 separately
643 * depending on their availability.
644 * Can't add to offset_max as they are staggered
645 */
646 if (ibs_caps & IBS_CAPS_BRNTRGT) {
647 rdmsrl(MSR_AMD64_IBSBRTARGET, *buf++);
648 size++;
649 }
650 if (ibs_caps & IBS_CAPS_OPDATA4) {
651 rdmsrl(MSR_AMD64_IBSOPDATA4, *buf++);
652 size++;
653 }
654 }
655 ibs_data.size = sizeof(u64) * size;
656
657 regs = *iregs;
658 if (check_rip && (ibs_data.regs[2] & IBS_RIP_INVALID)) {
659 regs.flags &= ~PERF_EFLAGS_EXACT;
660 } else {
661 set_linear_ip(®s, ibs_data.regs[1]);
662 regs.flags |= PERF_EFLAGS_EXACT;
663 }
664
665 if (event->attr.sample_type & PERF_SAMPLE_RAW) {
666 raw = (struct perf_raw_record){
667 .frag = {
668 .size = sizeof(u32) + ibs_data.size,
669 .data = ibs_data.data,
670 },
671 };
672 data.raw = &raw;
673 }
674
675 throttle = perf_event_overflow(event, &data, ®s);
676 out:
677 if (throttle) {
678 perf_ibs_stop(event, 0);
679 } else {
680 period >>= 4;
681
682 if ((ibs_caps & IBS_CAPS_RDWROPCNT) &&
683 (*config & IBS_OP_CNT_CTL))
684 period |= *config & IBS_OP_CUR_CNT_RAND;
685
686 perf_ibs_enable_event(perf_ibs, hwc, period);
687 }
688
689 perf_event_update_userpage(event);
690
691 return 1;
692 }
693
694 static int
perf_ibs_nmi_handler(unsigned int cmd,struct pt_regs * regs)695 perf_ibs_nmi_handler(unsigned int cmd, struct pt_regs *regs)
696 {
697 u64 stamp = sched_clock();
698 int handled = 0;
699
700 handled += perf_ibs_handle_irq(&perf_ibs_fetch, regs);
701 handled += perf_ibs_handle_irq(&perf_ibs_op, regs);
702
703 if (handled)
704 inc_irq_stat(apic_perf_irqs);
705
706 perf_sample_event_took(sched_clock() - stamp);
707
708 return handled;
709 }
710 NOKPROBE_SYMBOL(perf_ibs_nmi_handler);
711
perf_ibs_pmu_init(struct perf_ibs * perf_ibs,char * name)712 static __init int perf_ibs_pmu_init(struct perf_ibs *perf_ibs, char *name)
713 {
714 struct cpu_perf_ibs __percpu *pcpu;
715 int ret;
716
717 pcpu = alloc_percpu(struct cpu_perf_ibs);
718 if (!pcpu)
719 return -ENOMEM;
720
721 perf_ibs->pcpu = pcpu;
722
723 /* register attributes */
724 if (perf_ibs->format_attrs[0]) {
725 memset(&perf_ibs->format_group, 0, sizeof(perf_ibs->format_group));
726 perf_ibs->format_group.name = "format";
727 perf_ibs->format_group.attrs = perf_ibs->format_attrs;
728
729 memset(&perf_ibs->attr_groups, 0, sizeof(perf_ibs->attr_groups));
730 perf_ibs->attr_groups[0] = &perf_ibs->format_group;
731 perf_ibs->pmu.attr_groups = perf_ibs->attr_groups;
732 }
733
734 ret = perf_pmu_register(&perf_ibs->pmu, name, -1);
735 if (ret) {
736 perf_ibs->pcpu = NULL;
737 free_percpu(pcpu);
738 }
739
740 return ret;
741 }
742
perf_event_ibs_init(void)743 static __init void perf_event_ibs_init(void)
744 {
745 struct attribute **attr = ibs_op_format_attrs;
746
747 perf_ibs_pmu_init(&perf_ibs_fetch, "ibs_fetch");
748
749 if (ibs_caps & IBS_CAPS_OPCNT) {
750 perf_ibs_op.config_mask |= IBS_OP_CNT_CTL;
751 *attr++ = &format_attr_cnt_ctl.attr;
752 }
753 perf_ibs_pmu_init(&perf_ibs_op, "ibs_op");
754
755 register_nmi_handler(NMI_LOCAL, perf_ibs_nmi_handler, 0, "perf_ibs");
756 pr_info("perf: AMD IBS detected (0x%08x)\n", ibs_caps);
757 }
758
759 #else /* defined(CONFIG_PERF_EVENTS) && defined(CONFIG_CPU_SUP_AMD) */
760
perf_event_ibs_init(void)761 static __init void perf_event_ibs_init(void) { }
762
763 #endif
764
765 /* IBS - apic initialization, for perf and oprofile */
766
__get_ibs_caps(void)767 static __init u32 __get_ibs_caps(void)
768 {
769 u32 caps;
770 unsigned int max_level;
771
772 if (!boot_cpu_has(X86_FEATURE_IBS))
773 return 0;
774
775 /* check IBS cpuid feature flags */
776 max_level = cpuid_eax(0x80000000);
777 if (max_level < IBS_CPUID_FEATURES)
778 return IBS_CAPS_DEFAULT;
779
780 caps = cpuid_eax(IBS_CPUID_FEATURES);
781 if (!(caps & IBS_CAPS_AVAIL))
782 /* cpuid flags not valid */
783 return IBS_CAPS_DEFAULT;
784
785 return caps;
786 }
787
get_ibs_caps(void)788 u32 get_ibs_caps(void)
789 {
790 return ibs_caps;
791 }
792
793 EXPORT_SYMBOL(get_ibs_caps);
794
get_eilvt(int offset)795 static inline int get_eilvt(int offset)
796 {
797 return !setup_APIC_eilvt(offset, 0, APIC_EILVT_MSG_NMI, 1);
798 }
799
put_eilvt(int offset)800 static inline int put_eilvt(int offset)
801 {
802 return !setup_APIC_eilvt(offset, 0, 0, 1);
803 }
804
805 /*
806 * Check and reserve APIC extended interrupt LVT offset for IBS if available.
807 */
ibs_eilvt_valid(void)808 static inline int ibs_eilvt_valid(void)
809 {
810 int offset;
811 u64 val;
812 int valid = 0;
813
814 preempt_disable();
815
816 rdmsrl(MSR_AMD64_IBSCTL, val);
817 offset = val & IBSCTL_LVT_OFFSET_MASK;
818
819 if (!(val & IBSCTL_LVT_OFFSET_VALID)) {
820 pr_err(FW_BUG "cpu %d, invalid IBS interrupt offset %d (MSR%08X=0x%016llx)\n",
821 smp_processor_id(), offset, MSR_AMD64_IBSCTL, val);
822 goto out;
823 }
824
825 if (!get_eilvt(offset)) {
826 pr_err(FW_BUG "cpu %d, IBS interrupt offset %d not available (MSR%08X=0x%016llx)\n",
827 smp_processor_id(), offset, MSR_AMD64_IBSCTL, val);
828 goto out;
829 }
830
831 valid = 1;
832 out:
833 preempt_enable();
834
835 return valid;
836 }
837
setup_ibs_ctl(int ibs_eilvt_off)838 static int setup_ibs_ctl(int ibs_eilvt_off)
839 {
840 struct pci_dev *cpu_cfg;
841 int nodes;
842 u32 value = 0;
843
844 nodes = 0;
845 cpu_cfg = NULL;
846 do {
847 cpu_cfg = pci_get_device(PCI_VENDOR_ID_AMD,
848 PCI_DEVICE_ID_AMD_10H_NB_MISC,
849 cpu_cfg);
850 if (!cpu_cfg)
851 break;
852 ++nodes;
853 pci_write_config_dword(cpu_cfg, IBSCTL, ibs_eilvt_off
854 | IBSCTL_LVT_OFFSET_VALID);
855 pci_read_config_dword(cpu_cfg, IBSCTL, &value);
856 if (value != (ibs_eilvt_off | IBSCTL_LVT_OFFSET_VALID)) {
857 pci_dev_put(cpu_cfg);
858 pr_debug("Failed to setup IBS LVT offset, IBSCTL = 0x%08x\n",
859 value);
860 return -EINVAL;
861 }
862 } while (1);
863
864 if (!nodes) {
865 pr_debug("No CPU node configured for IBS\n");
866 return -ENODEV;
867 }
868
869 return 0;
870 }
871
872 /*
873 * This runs only on the current cpu. We try to find an LVT offset and
874 * setup the local APIC. For this we must disable preemption. On
875 * success we initialize all nodes with this offset. This updates then
876 * the offset in the IBS_CTL per-node msr. The per-core APIC setup of
877 * the IBS interrupt vector is handled by perf_ibs_cpu_notifier that
878 * is using the new offset.
879 */
force_ibs_eilvt_setup(void)880 static void force_ibs_eilvt_setup(void)
881 {
882 int offset;
883 int ret;
884
885 preempt_disable();
886 /* find the next free available EILVT entry, skip offset 0 */
887 for (offset = 1; offset < APIC_EILVT_NR_MAX; offset++) {
888 if (get_eilvt(offset))
889 break;
890 }
891 preempt_enable();
892
893 if (offset == APIC_EILVT_NR_MAX) {
894 pr_debug("No EILVT entry available\n");
895 return;
896 }
897
898 ret = setup_ibs_ctl(offset);
899 if (ret)
900 goto out;
901
902 if (!ibs_eilvt_valid())
903 goto out;
904
905 pr_info("IBS: LVT offset %d assigned\n", offset);
906
907 return;
908 out:
909 preempt_disable();
910 put_eilvt(offset);
911 preempt_enable();
912 return;
913 }
914
ibs_eilvt_setup(void)915 static void ibs_eilvt_setup(void)
916 {
917 /*
918 * Force LVT offset assignment for family 10h: The offsets are
919 * not assigned by the BIOS for this family, so the OS is
920 * responsible for doing it. If the OS assignment fails, fall
921 * back to BIOS settings and try to setup this.
922 */
923 if (boot_cpu_data.x86 == 0x10)
924 force_ibs_eilvt_setup();
925 }
926
get_ibs_lvt_offset(void)927 static inline int get_ibs_lvt_offset(void)
928 {
929 u64 val;
930
931 rdmsrl(MSR_AMD64_IBSCTL, val);
932 if (!(val & IBSCTL_LVT_OFFSET_VALID))
933 return -EINVAL;
934
935 return val & IBSCTL_LVT_OFFSET_MASK;
936 }
937
setup_APIC_ibs(void)938 static void setup_APIC_ibs(void)
939 {
940 int offset;
941
942 offset = get_ibs_lvt_offset();
943 if (offset < 0)
944 goto failed;
945
946 if (!setup_APIC_eilvt(offset, 0, APIC_EILVT_MSG_NMI, 0))
947 return;
948 failed:
949 pr_warn("perf: IBS APIC setup failed on cpu #%d\n",
950 smp_processor_id());
951 }
952
clear_APIC_ibs(void)953 static void clear_APIC_ibs(void)
954 {
955 int offset;
956
957 offset = get_ibs_lvt_offset();
958 if (offset >= 0)
959 setup_APIC_eilvt(offset, 0, APIC_EILVT_MSG_FIX, 1);
960 }
961
x86_pmu_amd_ibs_starting_cpu(unsigned int cpu)962 static int x86_pmu_amd_ibs_starting_cpu(unsigned int cpu)
963 {
964 setup_APIC_ibs();
965 return 0;
966 }
967
968 #ifdef CONFIG_PM
969
perf_ibs_suspend(void)970 static int perf_ibs_suspend(void)
971 {
972 clear_APIC_ibs();
973 return 0;
974 }
975
perf_ibs_resume(void)976 static void perf_ibs_resume(void)
977 {
978 ibs_eilvt_setup();
979 setup_APIC_ibs();
980 }
981
982 static struct syscore_ops perf_ibs_syscore_ops = {
983 .resume = perf_ibs_resume,
984 .suspend = perf_ibs_suspend,
985 };
986
perf_ibs_pm_init(void)987 static void perf_ibs_pm_init(void)
988 {
989 register_syscore_ops(&perf_ibs_syscore_ops);
990 }
991
992 #else
993
perf_ibs_pm_init(void)994 static inline void perf_ibs_pm_init(void) { }
995
996 #endif
997
x86_pmu_amd_ibs_dying_cpu(unsigned int cpu)998 static int x86_pmu_amd_ibs_dying_cpu(unsigned int cpu)
999 {
1000 clear_APIC_ibs();
1001 return 0;
1002 }
1003
amd_ibs_init(void)1004 static __init int amd_ibs_init(void)
1005 {
1006 u32 caps;
1007
1008 caps = __get_ibs_caps();
1009 if (!caps)
1010 return -ENODEV; /* ibs not supported by the cpu */
1011
1012 ibs_eilvt_setup();
1013
1014 if (!ibs_eilvt_valid())
1015 return -EINVAL;
1016
1017 perf_ibs_pm_init();
1018
1019 ibs_caps = caps;
1020 /* make ibs_caps visible to other cpus: */
1021 smp_mb();
1022 /*
1023 * x86_pmu_amd_ibs_starting_cpu will be called from core on
1024 * all online cpus.
1025 */
1026 cpuhp_setup_state(CPUHP_AP_PERF_X86_AMD_IBS_STARTING,
1027 "perf/x86/amd/ibs:starting",
1028 x86_pmu_amd_ibs_starting_cpu,
1029 x86_pmu_amd_ibs_dying_cpu);
1030
1031 perf_event_ibs_init();
1032
1033 return 0;
1034 }
1035
1036 /* Since we need the pci subsystem to init ibs we can't do this earlier: */
1037 device_initcall(amd_ibs_init);
1038