1 #include <linux/export.h>
2 #include <linux/bitops.h>
3 #include <linux/elf.h>
4 #include <linux/mm.h>
5
6 #include <linux/io.h>
7 #include <linux/sched.h>
8 #include <linux/sched/clock.h>
9 #include <linux/random.h>
10 #include <asm/processor.h>
11 #include <asm/apic.h>
12 #include <asm/cpu.h>
13 #include <asm/spec-ctrl.h>
14 #include <asm/smp.h>
15 #include <asm/pci-direct.h>
16 #include <asm/delay.h>
17
18 #ifdef CONFIG_X86_64
19 # include <asm/mmconfig.h>
20 # include <asm/set_memory.h>
21 #endif
22
23 #include "cpu.h"
24
25 static const int amd_erratum_383[];
26 static const int amd_erratum_400[];
27 static bool cpu_has_amd_erratum(struct cpuinfo_x86 *cpu, const int *erratum);
28
29 /*
30 * nodes_per_socket: Stores the number of nodes per socket.
31 * Refer to Fam15h Models 00-0fh BKDG - CPUID Fn8000_001E_ECX
32 * Node Identifiers[10:8]
33 */
34 static u32 nodes_per_socket = 1;
35
rdmsrl_amd_safe(unsigned msr,unsigned long long * p)36 static inline int rdmsrl_amd_safe(unsigned msr, unsigned long long *p)
37 {
38 u32 gprs[8] = { 0 };
39 int err;
40
41 WARN_ONCE((boot_cpu_data.x86 != 0xf),
42 "%s should only be used on K8!\n", __func__);
43
44 gprs[1] = msr;
45 gprs[7] = 0x9c5a203a;
46
47 err = rdmsr_safe_regs(gprs);
48
49 *p = gprs[0] | ((u64)gprs[2] << 32);
50
51 return err;
52 }
53
wrmsrl_amd_safe(unsigned msr,unsigned long long val)54 static inline int wrmsrl_amd_safe(unsigned msr, unsigned long long val)
55 {
56 u32 gprs[8] = { 0 };
57
58 WARN_ONCE((boot_cpu_data.x86 != 0xf),
59 "%s should only be used on K8!\n", __func__);
60
61 gprs[0] = (u32)val;
62 gprs[1] = msr;
63 gprs[2] = val >> 32;
64 gprs[7] = 0x9c5a203a;
65
66 return wrmsr_safe_regs(gprs);
67 }
68
69 /*
70 * B step AMD K6 before B 9730xxxx have hardware bugs that can cause
71 * misexecution of code under Linux. Owners of such processors should
72 * contact AMD for precise details and a CPU swap.
73 *
74 * See http://www.multimania.com/poulot/k6bug.html
75 * and section 2.6.2 of "AMD-K6 Processor Revision Guide - Model 6"
76 * (Publication # 21266 Issue Date: August 1998)
77 *
78 * The following test is erm.. interesting. AMD neglected to up
79 * the chip setting when fixing the bug but they also tweaked some
80 * performance at the same time..
81 */
82
83 extern __visible void vide(void);
84 __asm__(".globl vide\n"
85 ".type vide, @function\n"
86 ".align 4\n"
87 "vide: ret\n");
88
init_amd_k5(struct cpuinfo_x86 * c)89 static void init_amd_k5(struct cpuinfo_x86 *c)
90 {
91 #ifdef CONFIG_X86_32
92 /*
93 * General Systems BIOSen alias the cpu frequency registers
94 * of the Elan at 0x000df000. Unfortunately, one of the Linux
95 * drivers subsequently pokes it, and changes the CPU speed.
96 * Workaround : Remove the unneeded alias.
97 */
98 #define CBAR (0xfffc) /* Configuration Base Address (32-bit) */
99 #define CBAR_ENB (0x80000000)
100 #define CBAR_KEY (0X000000CB)
101 if (c->x86_model == 9 || c->x86_model == 10) {
102 if (inl(CBAR) & CBAR_ENB)
103 outl(0 | CBAR_KEY, CBAR);
104 }
105 #endif
106 }
107
init_amd_k6(struct cpuinfo_x86 * c)108 static void init_amd_k6(struct cpuinfo_x86 *c)
109 {
110 #ifdef CONFIG_X86_32
111 u32 l, h;
112 int mbytes = get_num_physpages() >> (20-PAGE_SHIFT);
113
114 if (c->x86_model < 6) {
115 /* Based on AMD doc 20734R - June 2000 */
116 if (c->x86_model == 0) {
117 clear_cpu_cap(c, X86_FEATURE_APIC);
118 set_cpu_cap(c, X86_FEATURE_PGE);
119 }
120 return;
121 }
122
123 if (c->x86_model == 6 && c->x86_stepping == 1) {
124 const int K6_BUG_LOOP = 1000000;
125 int n;
126 void (*f_vide)(void);
127 u64 d, d2;
128
129 pr_info("AMD K6 stepping B detected - ");
130
131 /*
132 * It looks like AMD fixed the 2.6.2 bug and improved indirect
133 * calls at the same time.
134 */
135
136 n = K6_BUG_LOOP;
137 f_vide = vide;
138 OPTIMIZER_HIDE_VAR(f_vide);
139 d = rdtsc();
140 while (n--)
141 f_vide();
142 d2 = rdtsc();
143 d = d2-d;
144
145 if (d > 20*K6_BUG_LOOP)
146 pr_cont("system stability may be impaired when more than 32 MB are used.\n");
147 else
148 pr_cont("probably OK (after B9730xxxx).\n");
149 }
150
151 /* K6 with old style WHCR */
152 if (c->x86_model < 8 ||
153 (c->x86_model == 8 && c->x86_stepping < 8)) {
154 /* We can only write allocate on the low 508Mb */
155 if (mbytes > 508)
156 mbytes = 508;
157
158 rdmsr(MSR_K6_WHCR, l, h);
159 if ((l&0x0000FFFF) == 0) {
160 unsigned long flags;
161 l = (1<<0)|((mbytes/4)<<1);
162 local_irq_save(flags);
163 wbinvd();
164 wrmsr(MSR_K6_WHCR, l, h);
165 local_irq_restore(flags);
166 pr_info("Enabling old style K6 write allocation for %d Mb\n",
167 mbytes);
168 }
169 return;
170 }
171
172 if ((c->x86_model == 8 && c->x86_stepping > 7) ||
173 c->x86_model == 9 || c->x86_model == 13) {
174 /* The more serious chips .. */
175
176 if (mbytes > 4092)
177 mbytes = 4092;
178
179 rdmsr(MSR_K6_WHCR, l, h);
180 if ((l&0xFFFF0000) == 0) {
181 unsigned long flags;
182 l = ((mbytes>>2)<<22)|(1<<16);
183 local_irq_save(flags);
184 wbinvd();
185 wrmsr(MSR_K6_WHCR, l, h);
186 local_irq_restore(flags);
187 pr_info("Enabling new style K6 write allocation for %d Mb\n",
188 mbytes);
189 }
190
191 return;
192 }
193
194 if (c->x86_model == 10) {
195 /* AMD Geode LX is model 10 */
196 /* placeholder for any needed mods */
197 return;
198 }
199 #endif
200 }
201
init_amd_k7(struct cpuinfo_x86 * c)202 static void init_amd_k7(struct cpuinfo_x86 *c)
203 {
204 #ifdef CONFIG_X86_32
205 u32 l, h;
206
207 /*
208 * Bit 15 of Athlon specific MSR 15, needs to be 0
209 * to enable SSE on Palomino/Morgan/Barton CPU's.
210 * If the BIOS didn't enable it already, enable it here.
211 */
212 if (c->x86_model >= 6 && c->x86_model <= 10) {
213 if (!cpu_has(c, X86_FEATURE_XMM)) {
214 pr_info("Enabling disabled K7/SSE Support.\n");
215 msr_clear_bit(MSR_K7_HWCR, 15);
216 set_cpu_cap(c, X86_FEATURE_XMM);
217 }
218 }
219
220 /*
221 * It's been determined by AMD that Athlons since model 8 stepping 1
222 * are more robust with CLK_CTL set to 200xxxxx instead of 600xxxxx
223 * As per AMD technical note 27212 0.2
224 */
225 if ((c->x86_model == 8 && c->x86_stepping >= 1) || (c->x86_model > 8)) {
226 rdmsr(MSR_K7_CLK_CTL, l, h);
227 if ((l & 0xfff00000) != 0x20000000) {
228 pr_info("CPU: CLK_CTL MSR was %x. Reprogramming to %x\n",
229 l, ((l & 0x000fffff)|0x20000000));
230 wrmsr(MSR_K7_CLK_CTL, (l & 0x000fffff)|0x20000000, h);
231 }
232 }
233
234 set_cpu_cap(c, X86_FEATURE_K7);
235
236 /* calling is from identify_secondary_cpu() ? */
237 if (!c->cpu_index)
238 return;
239
240 /*
241 * Certain Athlons might work (for various values of 'work') in SMP
242 * but they are not certified as MP capable.
243 */
244 /* Athlon 660/661 is valid. */
245 if ((c->x86_model == 6) && ((c->x86_stepping == 0) ||
246 (c->x86_stepping == 1)))
247 return;
248
249 /* Duron 670 is valid */
250 if ((c->x86_model == 7) && (c->x86_stepping == 0))
251 return;
252
253 /*
254 * Athlon 662, Duron 671, and Athlon >model 7 have capability
255 * bit. It's worth noting that the A5 stepping (662) of some
256 * Athlon XP's have the MP bit set.
257 * See http://www.heise.de/newsticker/data/jow-18.10.01-000 for
258 * more.
259 */
260 if (((c->x86_model == 6) && (c->x86_stepping >= 2)) ||
261 ((c->x86_model == 7) && (c->x86_stepping >= 1)) ||
262 (c->x86_model > 7))
263 if (cpu_has(c, X86_FEATURE_MP))
264 return;
265
266 /* If we get here, not a certified SMP capable AMD system. */
267
268 /*
269 * Don't taint if we are running SMP kernel on a single non-MP
270 * approved Athlon
271 */
272 WARN_ONCE(1, "WARNING: This combination of AMD"
273 " processors is not suitable for SMP.\n");
274 add_taint(TAINT_CPU_OUT_OF_SPEC, LOCKDEP_NOW_UNRELIABLE);
275 #endif
276 }
277
278 #ifdef CONFIG_NUMA
279 /*
280 * To workaround broken NUMA config. Read the comment in
281 * srat_detect_node().
282 */
nearby_node(int apicid)283 static int nearby_node(int apicid)
284 {
285 int i, node;
286
287 for (i = apicid - 1; i >= 0; i--) {
288 node = __apicid_to_node[i];
289 if (node != NUMA_NO_NODE && node_online(node))
290 return node;
291 }
292 for (i = apicid + 1; i < MAX_LOCAL_APIC; i++) {
293 node = __apicid_to_node[i];
294 if (node != NUMA_NO_NODE && node_online(node))
295 return node;
296 }
297 return first_node(node_online_map); /* Shouldn't happen */
298 }
299 #endif
300
301 /*
302 * Fix up cpu_core_id for pre-F17h systems to be in the
303 * [0 .. cores_per_node - 1] range. Not really needed but
304 * kept so as not to break existing setups.
305 */
legacy_fixup_core_id(struct cpuinfo_x86 * c)306 static void legacy_fixup_core_id(struct cpuinfo_x86 *c)
307 {
308 u32 cus_per_node;
309
310 if (c->x86 >= 0x17)
311 return;
312
313 cus_per_node = c->x86_max_cores / nodes_per_socket;
314 c->cpu_core_id %= cus_per_node;
315 }
316
317
amd_get_topology_early(struct cpuinfo_x86 * c)318 static void amd_get_topology_early(struct cpuinfo_x86 *c)
319 {
320 if (cpu_has(c, X86_FEATURE_TOPOEXT))
321 smp_num_siblings = ((cpuid_ebx(0x8000001e) >> 8) & 0xff) + 1;
322 }
323
324 /*
325 * Fixup core topology information for
326 * (1) AMD multi-node processors
327 * Assumption: Number of cores in each internal node is the same.
328 * (2) AMD processors supporting compute units
329 */
amd_get_topology(struct cpuinfo_x86 * c)330 static void amd_get_topology(struct cpuinfo_x86 *c)
331 {
332 u8 node_id;
333 int cpu = smp_processor_id();
334
335 /* get information required for multi-node processors */
336 if (boot_cpu_has(X86_FEATURE_TOPOEXT)) {
337 u32 eax, ebx, ecx, edx;
338
339 cpuid(0x8000001e, &eax, &ebx, &ecx, &edx);
340
341 node_id = ecx & 0xff;
342
343 if (c->x86 == 0x15)
344 c->cu_id = ebx & 0xff;
345
346 if (c->x86 >= 0x17) {
347 c->cpu_core_id = ebx & 0xff;
348
349 if (smp_num_siblings > 1)
350 c->x86_max_cores /= smp_num_siblings;
351 }
352
353 /*
354 * We may have multiple LLCs if L3 caches exist, so check if we
355 * have an L3 cache by looking at the L3 cache CPUID leaf.
356 */
357 if (cpuid_edx(0x80000006)) {
358 if (c->x86 == 0x17) {
359 /*
360 * LLC is at the core complex level.
361 * Core complex id is ApicId[3].
362 */
363 per_cpu(cpu_llc_id, cpu) = c->apicid >> 3;
364 } else {
365 /* LLC is at the node level. */
366 per_cpu(cpu_llc_id, cpu) = node_id;
367 }
368 }
369 } else if (cpu_has(c, X86_FEATURE_NODEID_MSR)) {
370 u64 value;
371
372 rdmsrl(MSR_FAM10H_NODE_ID, value);
373 node_id = value & 7;
374
375 per_cpu(cpu_llc_id, cpu) = node_id;
376 } else
377 return;
378
379 if (nodes_per_socket > 1) {
380 set_cpu_cap(c, X86_FEATURE_AMD_DCM);
381 legacy_fixup_core_id(c);
382 }
383 }
384
385 /*
386 * On a AMD dual core setup the lower bits of the APIC id distinguish the cores.
387 * Assumes number of cores is a power of two.
388 */
amd_detect_cmp(struct cpuinfo_x86 * c)389 static void amd_detect_cmp(struct cpuinfo_x86 *c)
390 {
391 unsigned bits;
392 int cpu = smp_processor_id();
393
394 bits = c->x86_coreid_bits;
395 /* Low order bits define the core id (index of core in socket) */
396 c->cpu_core_id = c->initial_apicid & ((1 << bits)-1);
397 /* Convert the initial APIC ID into the socket ID */
398 c->phys_proc_id = c->initial_apicid >> bits;
399 /* use socket ID also for last level cache */
400 per_cpu(cpu_llc_id, cpu) = c->phys_proc_id;
401 amd_get_topology(c);
402 }
403
amd_get_nb_id(int cpu)404 u16 amd_get_nb_id(int cpu)
405 {
406 return per_cpu(cpu_llc_id, cpu);
407 }
408 EXPORT_SYMBOL_GPL(amd_get_nb_id);
409
amd_get_nodes_per_socket(void)410 u32 amd_get_nodes_per_socket(void)
411 {
412 return nodes_per_socket;
413 }
414 EXPORT_SYMBOL_GPL(amd_get_nodes_per_socket);
415
srat_detect_node(struct cpuinfo_x86 * c)416 static void srat_detect_node(struct cpuinfo_x86 *c)
417 {
418 #ifdef CONFIG_NUMA
419 int cpu = smp_processor_id();
420 int node;
421 unsigned apicid = c->apicid;
422
423 node = numa_cpu_node(cpu);
424 if (node == NUMA_NO_NODE)
425 node = per_cpu(cpu_llc_id, cpu);
426
427 /*
428 * On multi-fabric platform (e.g. Numascale NumaChip) a
429 * platform-specific handler needs to be called to fixup some
430 * IDs of the CPU.
431 */
432 if (x86_cpuinit.fixup_cpu_id)
433 x86_cpuinit.fixup_cpu_id(c, node);
434
435 if (!node_online(node)) {
436 /*
437 * Two possibilities here:
438 *
439 * - The CPU is missing memory and no node was created. In
440 * that case try picking one from a nearby CPU.
441 *
442 * - The APIC IDs differ from the HyperTransport node IDs
443 * which the K8 northbridge parsing fills in. Assume
444 * they are all increased by a constant offset, but in
445 * the same order as the HT nodeids. If that doesn't
446 * result in a usable node fall back to the path for the
447 * previous case.
448 *
449 * This workaround operates directly on the mapping between
450 * APIC ID and NUMA node, assuming certain relationship
451 * between APIC ID, HT node ID and NUMA topology. As going
452 * through CPU mapping may alter the outcome, directly
453 * access __apicid_to_node[].
454 */
455 int ht_nodeid = c->initial_apicid;
456
457 if (__apicid_to_node[ht_nodeid] != NUMA_NO_NODE)
458 node = __apicid_to_node[ht_nodeid];
459 /* Pick a nearby node */
460 if (!node_online(node))
461 node = nearby_node(apicid);
462 }
463 numa_set_node(cpu, node);
464 #endif
465 }
466
early_init_amd_mc(struct cpuinfo_x86 * c)467 static void early_init_amd_mc(struct cpuinfo_x86 *c)
468 {
469 #ifdef CONFIG_SMP
470 unsigned bits, ecx;
471
472 /* Multi core CPU? */
473 if (c->extended_cpuid_level < 0x80000008)
474 return;
475
476 ecx = cpuid_ecx(0x80000008);
477
478 c->x86_max_cores = (ecx & 0xff) + 1;
479
480 /* CPU telling us the core id bits shift? */
481 bits = (ecx >> 12) & 0xF;
482
483 /* Otherwise recompute */
484 if (bits == 0) {
485 while ((1 << bits) < c->x86_max_cores)
486 bits++;
487 }
488
489 c->x86_coreid_bits = bits;
490 #endif
491 }
492
bsp_init_amd(struct cpuinfo_x86 * c)493 static void bsp_init_amd(struct cpuinfo_x86 *c)
494 {
495
496 #ifdef CONFIG_X86_64
497 if (c->x86 >= 0xf) {
498 unsigned long long tseg;
499
500 /*
501 * Split up direct mapping around the TSEG SMM area.
502 * Don't do it for gbpages because there seems very little
503 * benefit in doing so.
504 */
505 if (!rdmsrl_safe(MSR_K8_TSEG_ADDR, &tseg)) {
506 unsigned long pfn = tseg >> PAGE_SHIFT;
507
508 pr_debug("tseg: %010llx\n", tseg);
509 if (pfn_range_is_mapped(pfn, pfn + 1))
510 set_memory_4k((unsigned long)__va(tseg), 1);
511 }
512 }
513 #endif
514
515 if (cpu_has(c, X86_FEATURE_CONSTANT_TSC)) {
516
517 if (c->x86 > 0x10 ||
518 (c->x86 == 0x10 && c->x86_model >= 0x2)) {
519 u64 val;
520
521 rdmsrl(MSR_K7_HWCR, val);
522 if (!(val & BIT(24)))
523 pr_warn(FW_BUG "TSC doesn't count with P0 frequency!\n");
524 }
525 }
526
527 if (c->x86 == 0x15) {
528 unsigned long upperbit;
529 u32 cpuid, assoc;
530
531 cpuid = cpuid_edx(0x80000005);
532 assoc = cpuid >> 16 & 0xff;
533 upperbit = ((cpuid >> 24) << 10) / assoc;
534
535 va_align.mask = (upperbit - 1) & PAGE_MASK;
536 va_align.flags = ALIGN_VA_32 | ALIGN_VA_64;
537
538 /* A random value per boot for bit slice [12:upper_bit) */
539 va_align.bits = get_random_int() & va_align.mask;
540 }
541
542 if (cpu_has(c, X86_FEATURE_MWAITX))
543 use_mwaitx_delay();
544
545 if (boot_cpu_has(X86_FEATURE_TOPOEXT)) {
546 u32 ecx;
547
548 ecx = cpuid_ecx(0x8000001e);
549 nodes_per_socket = ((ecx >> 8) & 7) + 1;
550 } else if (boot_cpu_has(X86_FEATURE_NODEID_MSR)) {
551 u64 value;
552
553 rdmsrl(MSR_FAM10H_NODE_ID, value);
554 nodes_per_socket = ((value >> 3) & 7) + 1;
555 }
556
557 if (!boot_cpu_has(X86_FEATURE_AMD_SSBD) &&
558 !boot_cpu_has(X86_FEATURE_VIRT_SSBD) &&
559 c->x86 >= 0x15 && c->x86 <= 0x17) {
560 unsigned int bit;
561
562 switch (c->x86) {
563 case 0x15: bit = 54; break;
564 case 0x16: bit = 33; break;
565 case 0x17: bit = 10; break;
566 default: return;
567 }
568 /*
569 * Try to cache the base value so further operations can
570 * avoid RMW. If that faults, do not enable SSBD.
571 */
572 if (!rdmsrl_safe(MSR_AMD64_LS_CFG, &x86_amd_ls_cfg_base)) {
573 setup_force_cpu_cap(X86_FEATURE_LS_CFG_SSBD);
574 setup_force_cpu_cap(X86_FEATURE_SSBD);
575 x86_amd_ls_cfg_ssbd_mask = 1ULL << bit;
576 }
577 }
578 }
579
early_init_amd(struct cpuinfo_x86 * c)580 static void early_init_amd(struct cpuinfo_x86 *c)
581 {
582 u64 value;
583 u32 dummy;
584
585 early_init_amd_mc(c);
586
587 rdmsr_safe(MSR_AMD64_PATCH_LEVEL, &c->microcode, &dummy);
588
589 /*
590 * c->x86_power is 8000_0007 edx. Bit 8 is TSC runs at constant rate
591 * with P/T states and does not stop in deep C-states
592 */
593 if (c->x86_power & (1 << 8)) {
594 set_cpu_cap(c, X86_FEATURE_CONSTANT_TSC);
595 set_cpu_cap(c, X86_FEATURE_NONSTOP_TSC);
596 }
597
598 /* Bit 12 of 8000_0007 edx is accumulated power mechanism. */
599 if (c->x86_power & BIT(12))
600 set_cpu_cap(c, X86_FEATURE_ACC_POWER);
601
602 #ifdef CONFIG_X86_64
603 set_cpu_cap(c, X86_FEATURE_SYSCALL32);
604 #else
605 /* Set MTRR capability flag if appropriate */
606 if (c->x86 == 5)
607 if (c->x86_model == 13 || c->x86_model == 9 ||
608 (c->x86_model == 8 && c->x86_stepping >= 8))
609 set_cpu_cap(c, X86_FEATURE_K6_MTRR);
610 #endif
611 #if defined(CONFIG_X86_LOCAL_APIC) && defined(CONFIG_PCI)
612 /*
613 * ApicID can always be treated as an 8-bit value for AMD APIC versions
614 * >= 0x10, but even old K8s came out of reset with version 0x10. So, we
615 * can safely set X86_FEATURE_EXTD_APICID unconditionally for families
616 * after 16h.
617 */
618 if (boot_cpu_has(X86_FEATURE_APIC)) {
619 if (c->x86 > 0x16)
620 set_cpu_cap(c, X86_FEATURE_EXTD_APICID);
621 else if (c->x86 >= 0xf) {
622 /* check CPU config space for extended APIC ID */
623 unsigned int val;
624
625 val = read_pci_config(0, 24, 0, 0x68);
626 if ((val >> 17 & 0x3) == 0x3)
627 set_cpu_cap(c, X86_FEATURE_EXTD_APICID);
628 }
629 }
630 #endif
631
632 /*
633 * This is only needed to tell the kernel whether to use VMCALL
634 * and VMMCALL. VMMCALL is never executed except under virt, so
635 * we can set it unconditionally.
636 */
637 set_cpu_cap(c, X86_FEATURE_VMMCALL);
638
639 /* F16h erratum 793, CVE-2013-6885 */
640 if (c->x86 == 0x16 && c->x86_model <= 0xf)
641 msr_set_bit(MSR_AMD64_LS_CFG, 15);
642
643 /*
644 * Check whether the machine is affected by erratum 400. This is
645 * used to select the proper idle routine and to enable the check
646 * whether the machine is affected in arch_post_acpi_init(), which
647 * sets the X86_BUG_AMD_APIC_C1E bug depending on the MSR check.
648 */
649 if (cpu_has_amd_erratum(c, amd_erratum_400))
650 set_cpu_bug(c, X86_BUG_AMD_E400);
651
652 /*
653 * BIOS support is required for SME. If BIOS has enabled SME then
654 * adjust x86_phys_bits by the SME physical address space reduction
655 * value. If BIOS has not enabled SME then don't advertise the
656 * feature (set in scattered.c). Also, since the SME support requires
657 * long mode, don't advertise the feature under CONFIG_X86_32.
658 */
659 if (cpu_has(c, X86_FEATURE_SME)) {
660 u64 msr;
661
662 /* Check if SME is enabled */
663 rdmsrl(MSR_K8_SYSCFG, msr);
664 if (msr & MSR_K8_SYSCFG_MEM_ENCRYPT) {
665 c->x86_phys_bits -= (cpuid_ebx(0x8000001f) >> 6) & 0x3f;
666 if (IS_ENABLED(CONFIG_X86_32))
667 clear_cpu_cap(c, X86_FEATURE_SME);
668 } else {
669 clear_cpu_cap(c, X86_FEATURE_SME);
670 }
671 }
672
673 /* Re-enable TopologyExtensions if switched off by BIOS */
674 if (c->x86 == 0x15 &&
675 (c->x86_model >= 0x10 && c->x86_model <= 0x6f) &&
676 !cpu_has(c, X86_FEATURE_TOPOEXT)) {
677
678 if (msr_set_bit(0xc0011005, 54) > 0) {
679 rdmsrl(0xc0011005, value);
680 if (value & BIT_64(54)) {
681 set_cpu_cap(c, X86_FEATURE_TOPOEXT);
682 pr_info_once(FW_INFO "CPU: Re-enabling disabled Topology Extensions Support.\n");
683 }
684 }
685 }
686
687 amd_get_topology_early(c);
688 }
689
init_amd_k8(struct cpuinfo_x86 * c)690 static void init_amd_k8(struct cpuinfo_x86 *c)
691 {
692 u32 level;
693 u64 value;
694
695 /* On C+ stepping K8 rep microcode works well for copy/memset */
696 level = cpuid_eax(1);
697 if ((level >= 0x0f48 && level < 0x0f50) || level >= 0x0f58)
698 set_cpu_cap(c, X86_FEATURE_REP_GOOD);
699
700 /*
701 * Some BIOSes incorrectly force this feature, but only K8 revision D
702 * (model = 0x14) and later actually support it.
703 * (AMD Erratum #110, docId: 25759).
704 */
705 if (c->x86_model < 0x14 && cpu_has(c, X86_FEATURE_LAHF_LM)) {
706 clear_cpu_cap(c, X86_FEATURE_LAHF_LM);
707 if (!rdmsrl_amd_safe(0xc001100d, &value)) {
708 value &= ~BIT_64(32);
709 wrmsrl_amd_safe(0xc001100d, value);
710 }
711 }
712
713 if (!c->x86_model_id[0])
714 strcpy(c->x86_model_id, "Hammer");
715
716 #ifdef CONFIG_SMP
717 /*
718 * Disable TLB flush filter by setting HWCR.FFDIS on K8
719 * bit 6 of msr C001_0015
720 *
721 * Errata 63 for SH-B3 steppings
722 * Errata 122 for all steppings (F+ have it disabled by default)
723 */
724 msr_set_bit(MSR_K7_HWCR, 6);
725 #endif
726 set_cpu_bug(c, X86_BUG_SWAPGS_FENCE);
727 }
728
init_amd_gh(struct cpuinfo_x86 * c)729 static void init_amd_gh(struct cpuinfo_x86 *c)
730 {
731 #ifdef CONFIG_X86_64
732 /* do this for boot cpu */
733 if (c == &boot_cpu_data)
734 check_enable_amd_mmconf_dmi();
735
736 fam10h_check_enable_mmcfg();
737 #endif
738
739 /*
740 * Disable GART TLB Walk Errors on Fam10h. We do this here because this
741 * is always needed when GART is enabled, even in a kernel which has no
742 * MCE support built in. BIOS should disable GartTlbWlk Errors already.
743 * If it doesn't, we do it here as suggested by the BKDG.
744 *
745 * Fixes: https://bugzilla.kernel.org/show_bug.cgi?id=33012
746 */
747 msr_set_bit(MSR_AMD64_MCx_MASK(4), 10);
748
749 /*
750 * On family 10h BIOS may not have properly enabled WC+ support, causing
751 * it to be converted to CD memtype. This may result in performance
752 * degradation for certain nested-paging guests. Prevent this conversion
753 * by clearing bit 24 in MSR_AMD64_BU_CFG2.
754 *
755 * NOTE: we want to use the _safe accessors so as not to #GP kvm
756 * guests on older kvm hosts.
757 */
758 msr_clear_bit(MSR_AMD64_BU_CFG2, 24);
759
760 if (cpu_has_amd_erratum(c, amd_erratum_383))
761 set_cpu_bug(c, X86_BUG_AMD_TLB_MMATCH);
762 }
763
764 #define MSR_AMD64_DE_CFG 0xC0011029
765
init_amd_ln(struct cpuinfo_x86 * c)766 static void init_amd_ln(struct cpuinfo_x86 *c)
767 {
768 /*
769 * Apply erratum 665 fix unconditionally so machines without a BIOS
770 * fix work.
771 */
772 msr_set_bit(MSR_AMD64_DE_CFG, 31);
773 }
774
775 static bool rdrand_force;
776
rdrand_cmdline(char * str)777 static int __init rdrand_cmdline(char *str)
778 {
779 if (!str)
780 return -EINVAL;
781
782 if (!strcmp(str, "force"))
783 rdrand_force = true;
784 else
785 return -EINVAL;
786
787 return 0;
788 }
789 early_param("rdrand", rdrand_cmdline);
790
clear_rdrand_cpuid_bit(struct cpuinfo_x86 * c)791 static void clear_rdrand_cpuid_bit(struct cpuinfo_x86 *c)
792 {
793 /*
794 * Saving of the MSR used to hide the RDRAND support during
795 * suspend/resume is done by arch/x86/power/cpu.c, which is
796 * dependent on CONFIG_PM_SLEEP.
797 */
798 if (!IS_ENABLED(CONFIG_PM_SLEEP))
799 return;
800
801 /*
802 * The nordrand option can clear X86_FEATURE_RDRAND, so check for
803 * RDRAND support using the CPUID function directly.
804 */
805 if (!(cpuid_ecx(1) & BIT(30)) || rdrand_force)
806 return;
807
808 msr_clear_bit(MSR_AMD64_CPUID_FN_1, 62);
809
810 /*
811 * Verify that the CPUID change has occurred in case the kernel is
812 * running virtualized and the hypervisor doesn't support the MSR.
813 */
814 if (cpuid_ecx(1) & BIT(30)) {
815 pr_info_once("BIOS may not properly restore RDRAND after suspend, but hypervisor does not support hiding RDRAND via CPUID.\n");
816 return;
817 }
818
819 clear_cpu_cap(c, X86_FEATURE_RDRAND);
820 pr_info_once("BIOS may not properly restore RDRAND after suspend, hiding RDRAND via CPUID. Use rdrand=force to reenable.\n");
821 }
822
init_amd_jg(struct cpuinfo_x86 * c)823 static void init_amd_jg(struct cpuinfo_x86 *c)
824 {
825 /*
826 * Some BIOS implementations do not restore proper RDRAND support
827 * across suspend and resume. Check on whether to hide the RDRAND
828 * instruction support via CPUID.
829 */
830 clear_rdrand_cpuid_bit(c);
831 }
832
init_amd_bd(struct cpuinfo_x86 * c)833 static void init_amd_bd(struct cpuinfo_x86 *c)
834 {
835 u64 value;
836
837 /*
838 * The way access filter has a performance penalty on some workloads.
839 * Disable it on the affected CPUs.
840 */
841 if ((c->x86_model >= 0x02) && (c->x86_model < 0x20)) {
842 if (!rdmsrl_safe(MSR_F15H_IC_CFG, &value) && !(value & 0x1E)) {
843 value |= 0x1E;
844 wrmsrl_safe(MSR_F15H_IC_CFG, value);
845 }
846 }
847
848 /*
849 * Some BIOS implementations do not restore proper RDRAND support
850 * across suspend and resume. Check on whether to hide the RDRAND
851 * instruction support via CPUID.
852 */
853 clear_rdrand_cpuid_bit(c);
854 }
855
init_amd_zn(struct cpuinfo_x86 * c)856 static void init_amd_zn(struct cpuinfo_x86 *c)
857 {
858 set_cpu_cap(c, X86_FEATURE_ZEN);
859
860 /*
861 * Fix erratum 1076: CPB feature bit not being set in CPUID.
862 * Always set it, except when running under a hypervisor.
863 */
864 if (!cpu_has(c, X86_FEATURE_HYPERVISOR) && !cpu_has(c, X86_FEATURE_CPB))
865 set_cpu_cap(c, X86_FEATURE_CPB);
866 }
867
init_amd(struct cpuinfo_x86 * c)868 static void init_amd(struct cpuinfo_x86 *c)
869 {
870 early_init_amd(c);
871
872 /*
873 * Bit 31 in normal CPUID used for nonstandard 3DNow ID;
874 * 3DNow is IDd by bit 31 in extended CPUID (1*32+31) anyway
875 */
876 clear_cpu_cap(c, 0*32+31);
877
878 if (c->x86 >= 0x10)
879 set_cpu_cap(c, X86_FEATURE_REP_GOOD);
880
881 /* get apicid instead of initial apic id from cpuid */
882 c->apicid = hard_smp_processor_id();
883
884 /* K6s reports MCEs but don't actually have all the MSRs */
885 if (c->x86 < 6)
886 clear_cpu_cap(c, X86_FEATURE_MCE);
887
888 switch (c->x86) {
889 case 4: init_amd_k5(c); break;
890 case 5: init_amd_k6(c); break;
891 case 6: init_amd_k7(c); break;
892 case 0xf: init_amd_k8(c); break;
893 case 0x10: init_amd_gh(c); break;
894 case 0x12: init_amd_ln(c); break;
895 case 0x15: init_amd_bd(c); break;
896 case 0x16: init_amd_jg(c); break;
897 case 0x17: init_amd_zn(c); break;
898 }
899
900 /*
901 * Enable workaround for FXSAVE leak on CPUs
902 * without a XSaveErPtr feature
903 */
904 if ((c->x86 >= 6) && (!cpu_has(c, X86_FEATURE_XSAVEERPTR)))
905 set_cpu_bug(c, X86_BUG_FXSAVE_LEAK);
906
907 cpu_detect_cache_sizes(c);
908
909 amd_detect_cmp(c);
910 srat_detect_node(c);
911
912 init_amd_cacheinfo(c);
913
914 if (c->x86 >= 0xf)
915 set_cpu_cap(c, X86_FEATURE_K8);
916
917 if (cpu_has(c, X86_FEATURE_XMM2)) {
918 unsigned long long val;
919 int ret;
920
921 /*
922 * A serializing LFENCE has less overhead than MFENCE, so
923 * use it for execution serialization. On families which
924 * don't have that MSR, LFENCE is already serializing.
925 * msr_set_bit() uses the safe accessors, too, even if the MSR
926 * is not present.
927 */
928 msr_set_bit(MSR_F10H_DECFG,
929 MSR_F10H_DECFG_LFENCE_SERIALIZE_BIT);
930
931 /*
932 * Verify that the MSR write was successful (could be running
933 * under a hypervisor) and only then assume that LFENCE is
934 * serializing.
935 */
936 ret = rdmsrl_safe(MSR_F10H_DECFG, &val);
937 if (!ret && (val & MSR_F10H_DECFG_LFENCE_SERIALIZE)) {
938 /* A serializing LFENCE stops RDTSC speculation */
939 set_cpu_cap(c, X86_FEATURE_LFENCE_RDTSC);
940 } else {
941 /* MFENCE stops RDTSC speculation */
942 set_cpu_cap(c, X86_FEATURE_MFENCE_RDTSC);
943 }
944 }
945
946 /*
947 * Family 0x12 and above processors have APIC timer
948 * running in deep C states.
949 */
950 if (c->x86 > 0x11)
951 set_cpu_cap(c, X86_FEATURE_ARAT);
952
953 /* 3DNow or LM implies PREFETCHW */
954 if (!cpu_has(c, X86_FEATURE_3DNOWPREFETCH))
955 if (cpu_has(c, X86_FEATURE_3DNOW) || cpu_has(c, X86_FEATURE_LM))
956 set_cpu_cap(c, X86_FEATURE_3DNOWPREFETCH);
957
958 /* AMD CPUs don't reset SS attributes on SYSRET, Xen does. */
959 if (!cpu_has(c, X86_FEATURE_XENPV))
960 set_cpu_bug(c, X86_BUG_SYSRET_SS_ATTRS);
961 }
962
963 #ifdef CONFIG_X86_32
amd_size_cache(struct cpuinfo_x86 * c,unsigned int size)964 static unsigned int amd_size_cache(struct cpuinfo_x86 *c, unsigned int size)
965 {
966 /* AMD errata T13 (order #21922) */
967 if ((c->x86 == 6)) {
968 /* Duron Rev A0 */
969 if (c->x86_model == 3 && c->x86_stepping == 0)
970 size = 64;
971 /* Tbird rev A1/A2 */
972 if (c->x86_model == 4 &&
973 (c->x86_stepping == 0 || c->x86_stepping == 1))
974 size = 256;
975 }
976 return size;
977 }
978 #endif
979
cpu_detect_tlb_amd(struct cpuinfo_x86 * c)980 static void cpu_detect_tlb_amd(struct cpuinfo_x86 *c)
981 {
982 u32 ebx, eax, ecx, edx;
983 u16 mask = 0xfff;
984
985 if (c->x86 < 0xf)
986 return;
987
988 if (c->extended_cpuid_level < 0x80000006)
989 return;
990
991 cpuid(0x80000006, &eax, &ebx, &ecx, &edx);
992
993 tlb_lld_4k[ENTRIES] = (ebx >> 16) & mask;
994 tlb_lli_4k[ENTRIES] = ebx & mask;
995
996 /*
997 * K8 doesn't have 2M/4M entries in the L2 TLB so read out the L1 TLB
998 * characteristics from the CPUID function 0x80000005 instead.
999 */
1000 if (c->x86 == 0xf) {
1001 cpuid(0x80000005, &eax, &ebx, &ecx, &edx);
1002 mask = 0xff;
1003 }
1004
1005 /* Handle DTLB 2M and 4M sizes, fall back to L1 if L2 is disabled */
1006 if (!((eax >> 16) & mask))
1007 tlb_lld_2m[ENTRIES] = (cpuid_eax(0x80000005) >> 16) & 0xff;
1008 else
1009 tlb_lld_2m[ENTRIES] = (eax >> 16) & mask;
1010
1011 /* a 4M entry uses two 2M entries */
1012 tlb_lld_4m[ENTRIES] = tlb_lld_2m[ENTRIES] >> 1;
1013
1014 /* Handle ITLB 2M and 4M sizes, fall back to L1 if L2 is disabled */
1015 if (!(eax & mask)) {
1016 /* Erratum 658 */
1017 if (c->x86 == 0x15 && c->x86_model <= 0x1f) {
1018 tlb_lli_2m[ENTRIES] = 1024;
1019 } else {
1020 cpuid(0x80000005, &eax, &ebx, &ecx, &edx);
1021 tlb_lli_2m[ENTRIES] = eax & 0xff;
1022 }
1023 } else
1024 tlb_lli_2m[ENTRIES] = eax & mask;
1025
1026 tlb_lli_4m[ENTRIES] = tlb_lli_2m[ENTRIES] >> 1;
1027 }
1028
1029 static const struct cpu_dev amd_cpu_dev = {
1030 .c_vendor = "AMD",
1031 .c_ident = { "AuthenticAMD" },
1032 #ifdef CONFIG_X86_32
1033 .legacy_models = {
1034 { .family = 4, .model_names =
1035 {
1036 [3] = "486 DX/2",
1037 [7] = "486 DX/2-WB",
1038 [8] = "486 DX/4",
1039 [9] = "486 DX/4-WB",
1040 [14] = "Am5x86-WT",
1041 [15] = "Am5x86-WB"
1042 }
1043 },
1044 },
1045 .legacy_cache_size = amd_size_cache,
1046 #endif
1047 .c_early_init = early_init_amd,
1048 .c_detect_tlb = cpu_detect_tlb_amd,
1049 .c_bsp_init = bsp_init_amd,
1050 .c_init = init_amd,
1051 .c_x86_vendor = X86_VENDOR_AMD,
1052 };
1053
1054 cpu_dev_register(amd_cpu_dev);
1055
1056 /*
1057 * AMD errata checking
1058 *
1059 * Errata are defined as arrays of ints using the AMD_LEGACY_ERRATUM() or
1060 * AMD_OSVW_ERRATUM() macros. The latter is intended for newer errata that
1061 * have an OSVW id assigned, which it takes as first argument. Both take a
1062 * variable number of family-specific model-stepping ranges created by
1063 * AMD_MODEL_RANGE().
1064 *
1065 * Example:
1066 *
1067 * const int amd_erratum_319[] =
1068 * AMD_LEGACY_ERRATUM(AMD_MODEL_RANGE(0x10, 0x2, 0x1, 0x4, 0x2),
1069 * AMD_MODEL_RANGE(0x10, 0x8, 0x0, 0x8, 0x0),
1070 * AMD_MODEL_RANGE(0x10, 0x9, 0x0, 0x9, 0x0));
1071 */
1072
1073 #define AMD_LEGACY_ERRATUM(...) { -1, __VA_ARGS__, 0 }
1074 #define AMD_OSVW_ERRATUM(osvw_id, ...) { osvw_id, __VA_ARGS__, 0 }
1075 #define AMD_MODEL_RANGE(f, m_start, s_start, m_end, s_end) \
1076 ((f << 24) | (m_start << 16) | (s_start << 12) | (m_end << 4) | (s_end))
1077 #define AMD_MODEL_RANGE_FAMILY(range) (((range) >> 24) & 0xff)
1078 #define AMD_MODEL_RANGE_START(range) (((range) >> 12) & 0xfff)
1079 #define AMD_MODEL_RANGE_END(range) ((range) & 0xfff)
1080
1081 static const int amd_erratum_400[] =
1082 AMD_OSVW_ERRATUM(1, AMD_MODEL_RANGE(0xf, 0x41, 0x2, 0xff, 0xf),
1083 AMD_MODEL_RANGE(0x10, 0x2, 0x1, 0xff, 0xf));
1084
1085 static const int amd_erratum_383[] =
1086 AMD_OSVW_ERRATUM(3, AMD_MODEL_RANGE(0x10, 0, 0, 0xff, 0xf));
1087
1088
cpu_has_amd_erratum(struct cpuinfo_x86 * cpu,const int * erratum)1089 static bool cpu_has_amd_erratum(struct cpuinfo_x86 *cpu, const int *erratum)
1090 {
1091 int osvw_id = *erratum++;
1092 u32 range;
1093 u32 ms;
1094
1095 if (osvw_id >= 0 && osvw_id < 65536 &&
1096 cpu_has(cpu, X86_FEATURE_OSVW)) {
1097 u64 osvw_len;
1098
1099 rdmsrl(MSR_AMD64_OSVW_ID_LENGTH, osvw_len);
1100 if (osvw_id < osvw_len) {
1101 u64 osvw_bits;
1102
1103 rdmsrl(MSR_AMD64_OSVW_STATUS + (osvw_id >> 6),
1104 osvw_bits);
1105 return osvw_bits & (1ULL << (osvw_id & 0x3f));
1106 }
1107 }
1108
1109 /* OSVW unavailable or ID unknown, match family-model-stepping range */
1110 ms = (cpu->x86_model << 4) | cpu->x86_stepping;
1111 while ((range = *erratum++))
1112 if ((cpu->x86 == AMD_MODEL_RANGE_FAMILY(range)) &&
1113 (ms >= AMD_MODEL_RANGE_START(range)) &&
1114 (ms <= AMD_MODEL_RANGE_END(range)))
1115 return true;
1116
1117 return false;
1118 }
1119
set_dr_addr_mask(unsigned long mask,int dr)1120 void set_dr_addr_mask(unsigned long mask, int dr)
1121 {
1122 if (!boot_cpu_has(X86_FEATURE_BPEXT))
1123 return;
1124
1125 switch (dr) {
1126 case 0:
1127 wrmsr(MSR_F16H_DR0_ADDR_MASK, mask, 0);
1128 break;
1129 case 1:
1130 case 2:
1131 case 3:
1132 wrmsr(MSR_F16H_DR1_ADDR_MASK - 1 + dr, mask, 0);
1133 break;
1134 default:
1135 break;
1136 }
1137 }
1138