1 #include <linux/bootmem.h> 2 #include <linux/linkage.h> 3 #include <linux/bitops.h> 4 #include <linux/kernel.h> 5 #include <linux/export.h> 6 #include <linux/percpu.h> 7 #include <linux/string.h> 8 #include <linux/ctype.h> 9 #include <linux/delay.h> 10 #include <linux/sched/mm.h> 11 #include <linux/sched/clock.h> 12 #include <linux/sched/task.h> 13 #include <linux/init.h> 14 #include <linux/kprobes.h> 15 #include <linux/kgdb.h> 16 #include <linux/smp.h> 17 #include <linux/io.h> 18 #include <linux/syscore_ops.h> 19 20 #include <asm/stackprotector.h> 21 #include <asm/perf_event.h> 22 #include <asm/mmu_context.h> 23 #include <asm/archrandom.h> 24 #include <asm/hypervisor.h> 25 #include <asm/processor.h> 26 #include <asm/tlbflush.h> 27 #include <asm/debugreg.h> 28 #include <asm/sections.h> 29 #include <asm/vsyscall.h> 30 #include <linux/topology.h> 31 #include <linux/cpumask.h> 32 #include <asm/pgtable.h> 33 #include <linux/atomic.h> 34 #include <asm/proto.h> 35 #include <asm/setup.h> 36 #include <asm/apic.h> 37 #include <asm/desc.h> 38 #include <asm/fpu/internal.h> 39 #include <asm/mtrr.h> 40 #include <asm/hwcap2.h> 41 #include <linux/numa.h> 42 #include <asm/asm.h> 43 #include <asm/bugs.h> 44 #include <asm/cpu.h> 45 #include <asm/mce.h> 46 #include <asm/msr.h> 47 #include <asm/pat.h> 48 #include <asm/microcode.h> 49 #include <asm/microcode_intel.h> 50 #include <asm/intel-family.h> 51 #include <asm/cpu_device_id.h> 52 53 #ifdef CONFIG_X86_LOCAL_APIC 54 #include <asm/uv/uv.h> 55 #endif 56 57 #include "cpu.h" 58 59 u32 elf_hwcap2 __read_mostly; 60 61 /* all of these masks are initialized in setup_cpu_local_masks() */ 62 cpumask_var_t cpu_initialized_mask; 63 cpumask_var_t cpu_callout_mask; 64 cpumask_var_t cpu_callin_mask; 65 66 /* representing cpus for which sibling maps can be computed */ 67 cpumask_var_t cpu_sibling_setup_mask; 68 69 /* Number of siblings per CPU package */ 70 int smp_num_siblings = 1; 71 EXPORT_SYMBOL(smp_num_siblings); 72 73 /* Last level cache ID of each logical CPU */ 74 DEFINE_PER_CPU_READ_MOSTLY(u16, cpu_llc_id) = BAD_APICID; 75 76 /* correctly size the local cpu masks */ setup_cpu_local_masks(void)77 void __init setup_cpu_local_masks(void) 78 { 79 alloc_bootmem_cpumask_var(&cpu_initialized_mask); 80 alloc_bootmem_cpumask_var(&cpu_callin_mask); 81 alloc_bootmem_cpumask_var(&cpu_callout_mask); 82 alloc_bootmem_cpumask_var(&cpu_sibling_setup_mask); 83 } 84 default_init(struct cpuinfo_x86 * c)85 static void default_init(struct cpuinfo_x86 *c) 86 { 87 #ifdef CONFIG_X86_64 88 cpu_detect_cache_sizes(c); 89 #else 90 /* Not much we can do here... */ 91 /* Check if at least it has cpuid */ 92 if (c->cpuid_level == -1) { 93 /* No cpuid. It must be an ancient CPU */ 94 if (c->x86 == 4) 95 strcpy(c->x86_model_id, "486"); 96 else if (c->x86 == 3) 97 strcpy(c->x86_model_id, "386"); 98 } 99 #endif 100 } 101 102 static const struct cpu_dev default_cpu = { 103 .c_init = default_init, 104 .c_vendor = "Unknown", 105 .c_x86_vendor = X86_VENDOR_UNKNOWN, 106 }; 107 108 static const struct cpu_dev *this_cpu = &default_cpu; 109 110 DEFINE_PER_CPU_PAGE_ALIGNED(struct gdt_page, gdt_page) = { .gdt = { 111 #ifdef CONFIG_X86_64 112 /* 113 * We need valid kernel segments for data and code in long mode too 114 * IRET will check the segment types kkeil 2000/10/28 115 * Also sysret mandates a special GDT layout 116 * 117 * TLS descriptors are currently at a different place compared to i386. 118 * Hopefully nobody expects them at a fixed place (Wine?) 119 */ 120 [GDT_ENTRY_KERNEL32_CS] = GDT_ENTRY_INIT(0xc09b, 0, 0xfffff), 121 [GDT_ENTRY_KERNEL_CS] = GDT_ENTRY_INIT(0xa09b, 0, 0xfffff), 122 [GDT_ENTRY_KERNEL_DS] = GDT_ENTRY_INIT(0xc093, 0, 0xfffff), 123 [GDT_ENTRY_DEFAULT_USER32_CS] = GDT_ENTRY_INIT(0xc0fb, 0, 0xfffff), 124 [GDT_ENTRY_DEFAULT_USER_DS] = GDT_ENTRY_INIT(0xc0f3, 0, 0xfffff), 125 [GDT_ENTRY_DEFAULT_USER_CS] = GDT_ENTRY_INIT(0xa0fb, 0, 0xfffff), 126 #else 127 [GDT_ENTRY_KERNEL_CS] = GDT_ENTRY_INIT(0xc09a, 0, 0xfffff), 128 [GDT_ENTRY_KERNEL_DS] = GDT_ENTRY_INIT(0xc092, 0, 0xfffff), 129 [GDT_ENTRY_DEFAULT_USER_CS] = GDT_ENTRY_INIT(0xc0fa, 0, 0xfffff), 130 [GDT_ENTRY_DEFAULT_USER_DS] = GDT_ENTRY_INIT(0xc0f2, 0, 0xfffff), 131 /* 132 * Segments used for calling PnP BIOS have byte granularity. 133 * They code segments and data segments have fixed 64k limits, 134 * the transfer segment sizes are set at run time. 135 */ 136 /* 32-bit code */ 137 [GDT_ENTRY_PNPBIOS_CS32] = GDT_ENTRY_INIT(0x409a, 0, 0xffff), 138 /* 16-bit code */ 139 [GDT_ENTRY_PNPBIOS_CS16] = GDT_ENTRY_INIT(0x009a, 0, 0xffff), 140 /* 16-bit data */ 141 [GDT_ENTRY_PNPBIOS_DS] = GDT_ENTRY_INIT(0x0092, 0, 0xffff), 142 /* 16-bit data */ 143 [GDT_ENTRY_PNPBIOS_TS1] = GDT_ENTRY_INIT(0x0092, 0, 0), 144 /* 16-bit data */ 145 [GDT_ENTRY_PNPBIOS_TS2] = GDT_ENTRY_INIT(0x0092, 0, 0), 146 /* 147 * The APM segments have byte granularity and their bases 148 * are set at run time. All have 64k limits. 149 */ 150 /* 32-bit code */ 151 [GDT_ENTRY_APMBIOS_BASE] = GDT_ENTRY_INIT(0x409a, 0, 0xffff), 152 /* 16-bit code */ 153 [GDT_ENTRY_APMBIOS_BASE+1] = GDT_ENTRY_INIT(0x009a, 0, 0xffff), 154 /* data */ 155 [GDT_ENTRY_APMBIOS_BASE+2] = GDT_ENTRY_INIT(0x4092, 0, 0xffff), 156 157 [GDT_ENTRY_ESPFIX_SS] = GDT_ENTRY_INIT(0xc092, 0, 0xfffff), 158 [GDT_ENTRY_PERCPU] = GDT_ENTRY_INIT(0xc092, 0, 0xfffff), 159 GDT_STACK_CANARY_INIT 160 #endif 161 } }; 162 EXPORT_PER_CPU_SYMBOL_GPL(gdt_page); 163 x86_mpx_setup(char * s)164 static int __init x86_mpx_setup(char *s) 165 { 166 /* require an exact match without trailing characters */ 167 if (strlen(s)) 168 return 0; 169 170 /* do not emit a message if the feature is not present */ 171 if (!boot_cpu_has(X86_FEATURE_MPX)) 172 return 1; 173 174 setup_clear_cpu_cap(X86_FEATURE_MPX); 175 pr_info("nompx: Intel Memory Protection Extensions (MPX) disabled\n"); 176 return 1; 177 } 178 __setup("nompx", x86_mpx_setup); 179 180 #ifdef CONFIG_X86_64 x86_nopcid_setup(char * s)181 static int __init x86_nopcid_setup(char *s) 182 { 183 /* nopcid doesn't accept parameters */ 184 if (s) 185 return -EINVAL; 186 187 /* do not emit a message if the feature is not present */ 188 if (!boot_cpu_has(X86_FEATURE_PCID)) 189 return 0; 190 191 setup_clear_cpu_cap(X86_FEATURE_PCID); 192 pr_info("nopcid: PCID feature disabled\n"); 193 return 0; 194 } 195 early_param("nopcid", x86_nopcid_setup); 196 #endif 197 x86_noinvpcid_setup(char * s)198 static int __init x86_noinvpcid_setup(char *s) 199 { 200 /* noinvpcid doesn't accept parameters */ 201 if (s) 202 return -EINVAL; 203 204 /* do not emit a message if the feature is not present */ 205 if (!boot_cpu_has(X86_FEATURE_INVPCID)) 206 return 0; 207 208 setup_clear_cpu_cap(X86_FEATURE_INVPCID); 209 pr_info("noinvpcid: INVPCID feature disabled\n"); 210 return 0; 211 } 212 early_param("noinvpcid", x86_noinvpcid_setup); 213 214 #ifdef CONFIG_X86_32 215 static int cachesize_override = -1; 216 static int disable_x86_serial_nr = 1; 217 cachesize_setup(char * str)218 static int __init cachesize_setup(char *str) 219 { 220 get_option(&str, &cachesize_override); 221 return 1; 222 } 223 __setup("cachesize=", cachesize_setup); 224 x86_sep_setup(char * s)225 static int __init x86_sep_setup(char *s) 226 { 227 setup_clear_cpu_cap(X86_FEATURE_SEP); 228 return 1; 229 } 230 __setup("nosep", x86_sep_setup); 231 232 /* Standard macro to see if a specific flag is changeable */ flag_is_changeable_p(u32 flag)233 static inline int flag_is_changeable_p(u32 flag) 234 { 235 u32 f1, f2; 236 237 /* 238 * Cyrix and IDT cpus allow disabling of CPUID 239 * so the code below may return different results 240 * when it is executed before and after enabling 241 * the CPUID. Add "volatile" to not allow gcc to 242 * optimize the subsequent calls to this function. 243 */ 244 asm volatile ("pushfl \n\t" 245 "pushfl \n\t" 246 "popl %0 \n\t" 247 "movl %0, %1 \n\t" 248 "xorl %2, %0 \n\t" 249 "pushl %0 \n\t" 250 "popfl \n\t" 251 "pushfl \n\t" 252 "popl %0 \n\t" 253 "popfl \n\t" 254 255 : "=&r" (f1), "=&r" (f2) 256 : "ir" (flag)); 257 258 return ((f1^f2) & flag) != 0; 259 } 260 261 /* Probe for the CPUID instruction */ have_cpuid_p(void)262 int have_cpuid_p(void) 263 { 264 return flag_is_changeable_p(X86_EFLAGS_ID); 265 } 266 squash_the_stupid_serial_number(struct cpuinfo_x86 * c)267 static void squash_the_stupid_serial_number(struct cpuinfo_x86 *c) 268 { 269 unsigned long lo, hi; 270 271 if (!cpu_has(c, X86_FEATURE_PN) || !disable_x86_serial_nr) 272 return; 273 274 /* Disable processor serial number: */ 275 276 rdmsr(MSR_IA32_BBL_CR_CTL, lo, hi); 277 lo |= 0x200000; 278 wrmsr(MSR_IA32_BBL_CR_CTL, lo, hi); 279 280 pr_notice("CPU serial number disabled.\n"); 281 clear_cpu_cap(c, X86_FEATURE_PN); 282 283 /* Disabling the serial number may affect the cpuid level */ 284 c->cpuid_level = cpuid_eax(0); 285 } 286 x86_serial_nr_setup(char * s)287 static int __init x86_serial_nr_setup(char *s) 288 { 289 disable_x86_serial_nr = 0; 290 return 1; 291 } 292 __setup("serialnumber", x86_serial_nr_setup); 293 #else flag_is_changeable_p(u32 flag)294 static inline int flag_is_changeable_p(u32 flag) 295 { 296 return 1; 297 } squash_the_stupid_serial_number(struct cpuinfo_x86 * c)298 static inline void squash_the_stupid_serial_number(struct cpuinfo_x86 *c) 299 { 300 } 301 #endif 302 setup_disable_smep(char * arg)303 static __init int setup_disable_smep(char *arg) 304 { 305 setup_clear_cpu_cap(X86_FEATURE_SMEP); 306 /* Check for things that depend on SMEP being enabled: */ 307 check_mpx_erratum(&boot_cpu_data); 308 return 1; 309 } 310 __setup("nosmep", setup_disable_smep); 311 setup_smep(struct cpuinfo_x86 * c)312 static __always_inline void setup_smep(struct cpuinfo_x86 *c) 313 { 314 if (cpu_has(c, X86_FEATURE_SMEP)) 315 cr4_set_bits(X86_CR4_SMEP); 316 } 317 setup_disable_smap(char * arg)318 static __init int setup_disable_smap(char *arg) 319 { 320 setup_clear_cpu_cap(X86_FEATURE_SMAP); 321 return 1; 322 } 323 __setup("nosmap", setup_disable_smap); 324 setup_smap(struct cpuinfo_x86 * c)325 static __always_inline void setup_smap(struct cpuinfo_x86 *c) 326 { 327 unsigned long eflags = native_save_fl(); 328 329 /* This should have been cleared long ago */ 330 BUG_ON(eflags & X86_EFLAGS_AC); 331 332 if (cpu_has(c, X86_FEATURE_SMAP)) { 333 #ifdef CONFIG_X86_SMAP 334 cr4_set_bits(X86_CR4_SMAP); 335 #else 336 cr4_clear_bits(X86_CR4_SMAP); 337 #endif 338 } 339 } 340 341 /* 342 * Protection Keys are not available in 32-bit mode. 343 */ 344 static bool pku_disabled; 345 setup_pku(struct cpuinfo_x86 * c)346 static __always_inline void setup_pku(struct cpuinfo_x86 *c) 347 { 348 /* check the boot processor, plus compile options for PKU: */ 349 if (!cpu_feature_enabled(X86_FEATURE_PKU)) 350 return; 351 /* checks the actual processor's cpuid bits: */ 352 if (!cpu_has(c, X86_FEATURE_PKU)) 353 return; 354 if (pku_disabled) 355 return; 356 357 cr4_set_bits(X86_CR4_PKE); 358 /* 359 * Seting X86_CR4_PKE will cause the X86_FEATURE_OSPKE 360 * cpuid bit to be set. We need to ensure that we 361 * update that bit in this CPU's "cpu_info". 362 */ 363 set_cpu_cap(c, X86_FEATURE_OSPKE); 364 } 365 366 #ifdef CONFIG_X86_INTEL_MEMORY_PROTECTION_KEYS setup_disable_pku(char * arg)367 static __init int setup_disable_pku(char *arg) 368 { 369 /* 370 * Do not clear the X86_FEATURE_PKU bit. All of the 371 * runtime checks are against OSPKE so clearing the 372 * bit does nothing. 373 * 374 * This way, we will see "pku" in cpuinfo, but not 375 * "ospke", which is exactly what we want. It shows 376 * that the CPU has PKU, but the OS has not enabled it. 377 * This happens to be exactly how a system would look 378 * if we disabled the config option. 379 */ 380 pr_info("x86: 'nopku' specified, disabling Memory Protection Keys\n"); 381 pku_disabled = true; 382 return 1; 383 } 384 __setup("nopku", setup_disable_pku); 385 #endif /* CONFIG_X86_64 */ 386 387 /* 388 * Some CPU features depend on higher CPUID levels, which may not always 389 * be available due to CPUID level capping or broken virtualization 390 * software. Add those features to this table to auto-disable them. 391 */ 392 struct cpuid_dependent_feature { 393 u32 feature; 394 u32 level; 395 }; 396 397 static const struct cpuid_dependent_feature 398 cpuid_dependent_features[] = { 399 { X86_FEATURE_MWAIT, 0x00000005 }, 400 { X86_FEATURE_DCA, 0x00000009 }, 401 { X86_FEATURE_XSAVE, 0x0000000d }, 402 { 0, 0 } 403 }; 404 filter_cpuid_features(struct cpuinfo_x86 * c,bool warn)405 static void filter_cpuid_features(struct cpuinfo_x86 *c, bool warn) 406 { 407 const struct cpuid_dependent_feature *df; 408 409 for (df = cpuid_dependent_features; df->feature; df++) { 410 411 if (!cpu_has(c, df->feature)) 412 continue; 413 /* 414 * Note: cpuid_level is set to -1 if unavailable, but 415 * extended_extended_level is set to 0 if unavailable 416 * and the legitimate extended levels are all negative 417 * when signed; hence the weird messing around with 418 * signs here... 419 */ 420 if (!((s32)df->level < 0 ? 421 (u32)df->level > (u32)c->extended_cpuid_level : 422 (s32)df->level > (s32)c->cpuid_level)) 423 continue; 424 425 clear_cpu_cap(c, df->feature); 426 if (!warn) 427 continue; 428 429 pr_warn("CPU: CPU feature " X86_CAP_FMT " disabled, no CPUID level 0x%x\n", 430 x86_cap_flag(df->feature), df->level); 431 } 432 } 433 434 /* 435 * Naming convention should be: <Name> [(<Codename>)] 436 * This table only is used unless init_<vendor>() below doesn't set it; 437 * in particular, if CPUID levels 0x80000002..4 are supported, this 438 * isn't used 439 */ 440 441 /* Look up CPU names by table lookup. */ table_lookup_model(struct cpuinfo_x86 * c)442 static const char *table_lookup_model(struct cpuinfo_x86 *c) 443 { 444 #ifdef CONFIG_X86_32 445 const struct legacy_cpu_model_info *info; 446 447 if (c->x86_model >= 16) 448 return NULL; /* Range check */ 449 450 if (!this_cpu) 451 return NULL; 452 453 info = this_cpu->legacy_models; 454 455 while (info->family) { 456 if (info->family == c->x86) 457 return info->model_names[c->x86_model]; 458 info++; 459 } 460 #endif 461 return NULL; /* Not found */ 462 } 463 464 __u32 cpu_caps_cleared[NCAPINTS + NBUGINTS]; 465 __u32 cpu_caps_set[NCAPINTS + NBUGINTS]; 466 load_percpu_segment(int cpu)467 void load_percpu_segment(int cpu) 468 { 469 #ifdef CONFIG_X86_32 470 loadsegment(fs, __KERNEL_PERCPU); 471 #else 472 __loadsegment_simple(gs, 0); 473 wrmsrl(MSR_GS_BASE, (unsigned long)per_cpu(irq_stack_union.gs_base, cpu)); 474 #endif 475 load_stack_canary_segment(); 476 } 477 478 #ifdef CONFIG_X86_32 479 /* The 32-bit entry code needs to find cpu_entry_area. */ 480 DEFINE_PER_CPU(struct cpu_entry_area *, cpu_entry_area); 481 #endif 482 483 #ifdef CONFIG_X86_64 484 /* 485 * Special IST stacks which the CPU switches to when it calls 486 * an IST-marked descriptor entry. Up to 7 stacks (hardware 487 * limit), all of them are 4K, except the debug stack which 488 * is 8K. 489 */ 490 static const unsigned int exception_stack_sizes[N_EXCEPTION_STACKS] = { 491 [0 ... N_EXCEPTION_STACKS - 1] = EXCEPTION_STKSZ, 492 [DEBUG_STACK - 1] = DEBUG_STKSZ 493 }; 494 #endif 495 496 /* Load the original GDT from the per-cpu structure */ load_direct_gdt(int cpu)497 void load_direct_gdt(int cpu) 498 { 499 struct desc_ptr gdt_descr; 500 501 gdt_descr.address = (long)get_cpu_gdt_rw(cpu); 502 gdt_descr.size = GDT_SIZE - 1; 503 load_gdt(&gdt_descr); 504 } 505 EXPORT_SYMBOL_GPL(load_direct_gdt); 506 507 /* Load a fixmap remapping of the per-cpu GDT */ load_fixmap_gdt(int cpu)508 void load_fixmap_gdt(int cpu) 509 { 510 struct desc_ptr gdt_descr; 511 512 gdt_descr.address = (long)get_cpu_gdt_ro(cpu); 513 gdt_descr.size = GDT_SIZE - 1; 514 load_gdt(&gdt_descr); 515 } 516 EXPORT_SYMBOL_GPL(load_fixmap_gdt); 517 518 /* 519 * Current gdt points %fs at the "master" per-cpu area: after this, 520 * it's on the real one. 521 */ switch_to_new_gdt(int cpu)522 void switch_to_new_gdt(int cpu) 523 { 524 /* Load the original GDT */ 525 load_direct_gdt(cpu); 526 /* Reload the per-cpu base */ 527 load_percpu_segment(cpu); 528 } 529 530 static const struct cpu_dev *cpu_devs[X86_VENDOR_NUM] = {}; 531 get_model_name(struct cpuinfo_x86 * c)532 static void get_model_name(struct cpuinfo_x86 *c) 533 { 534 unsigned int *v; 535 char *p, *q, *s; 536 537 if (c->extended_cpuid_level < 0x80000004) 538 return; 539 540 v = (unsigned int *)c->x86_model_id; 541 cpuid(0x80000002, &v[0], &v[1], &v[2], &v[3]); 542 cpuid(0x80000003, &v[4], &v[5], &v[6], &v[7]); 543 cpuid(0x80000004, &v[8], &v[9], &v[10], &v[11]); 544 c->x86_model_id[48] = 0; 545 546 /* Trim whitespace */ 547 p = q = s = &c->x86_model_id[0]; 548 549 while (*p == ' ') 550 p++; 551 552 while (*p) { 553 /* Note the last non-whitespace index */ 554 if (!isspace(*p)) 555 s = q; 556 557 *q++ = *p++; 558 } 559 560 *(s + 1) = '\0'; 561 } 562 cpu_detect_cache_sizes(struct cpuinfo_x86 * c)563 void cpu_detect_cache_sizes(struct cpuinfo_x86 *c) 564 { 565 unsigned int n, dummy, ebx, ecx, edx, l2size; 566 567 n = c->extended_cpuid_level; 568 569 if (n >= 0x80000005) { 570 cpuid(0x80000005, &dummy, &ebx, &ecx, &edx); 571 c->x86_cache_size = (ecx>>24) + (edx>>24); 572 #ifdef CONFIG_X86_64 573 /* On K8 L1 TLB is inclusive, so don't count it */ 574 c->x86_tlbsize = 0; 575 #endif 576 } 577 578 if (n < 0x80000006) /* Some chips just has a large L1. */ 579 return; 580 581 cpuid(0x80000006, &dummy, &ebx, &ecx, &edx); 582 l2size = ecx >> 16; 583 584 #ifdef CONFIG_X86_64 585 c->x86_tlbsize += ((ebx >> 16) & 0xfff) + (ebx & 0xfff); 586 #else 587 /* do processor-specific cache resizing */ 588 if (this_cpu->legacy_cache_size) 589 l2size = this_cpu->legacy_cache_size(c, l2size); 590 591 /* Allow user to override all this if necessary. */ 592 if (cachesize_override != -1) 593 l2size = cachesize_override; 594 595 if (l2size == 0) 596 return; /* Again, no L2 cache is possible */ 597 #endif 598 599 c->x86_cache_size = l2size; 600 } 601 602 u16 __read_mostly tlb_lli_4k[NR_INFO]; 603 u16 __read_mostly tlb_lli_2m[NR_INFO]; 604 u16 __read_mostly tlb_lli_4m[NR_INFO]; 605 u16 __read_mostly tlb_lld_4k[NR_INFO]; 606 u16 __read_mostly tlb_lld_2m[NR_INFO]; 607 u16 __read_mostly tlb_lld_4m[NR_INFO]; 608 u16 __read_mostly tlb_lld_1g[NR_INFO]; 609 cpu_detect_tlb(struct cpuinfo_x86 * c)610 static void cpu_detect_tlb(struct cpuinfo_x86 *c) 611 { 612 if (this_cpu->c_detect_tlb) 613 this_cpu->c_detect_tlb(c); 614 615 pr_info("Last level iTLB entries: 4KB %d, 2MB %d, 4MB %d\n", 616 tlb_lli_4k[ENTRIES], tlb_lli_2m[ENTRIES], 617 tlb_lli_4m[ENTRIES]); 618 619 pr_info("Last level dTLB entries: 4KB %d, 2MB %d, 4MB %d, 1GB %d\n", 620 tlb_lld_4k[ENTRIES], tlb_lld_2m[ENTRIES], 621 tlb_lld_4m[ENTRIES], tlb_lld_1g[ENTRIES]); 622 } 623 detect_ht_early(struct cpuinfo_x86 * c)624 int detect_ht_early(struct cpuinfo_x86 *c) 625 { 626 #ifdef CONFIG_SMP 627 u32 eax, ebx, ecx, edx; 628 629 if (!cpu_has(c, X86_FEATURE_HT)) 630 return -1; 631 632 if (cpu_has(c, X86_FEATURE_CMP_LEGACY)) 633 return -1; 634 635 if (cpu_has(c, X86_FEATURE_XTOPOLOGY)) 636 return -1; 637 638 cpuid(1, &eax, &ebx, &ecx, &edx); 639 640 smp_num_siblings = (ebx & 0xff0000) >> 16; 641 if (smp_num_siblings == 1) 642 pr_info_once("CPU0: Hyper-Threading is disabled\n"); 643 #endif 644 return 0; 645 } 646 detect_ht(struct cpuinfo_x86 * c)647 void detect_ht(struct cpuinfo_x86 *c) 648 { 649 #ifdef CONFIG_SMP 650 int index_msb, core_bits; 651 652 if (detect_ht_early(c) < 0) 653 return; 654 655 index_msb = get_count_order(smp_num_siblings); 656 c->phys_proc_id = apic->phys_pkg_id(c->initial_apicid, index_msb); 657 658 smp_num_siblings = smp_num_siblings / c->x86_max_cores; 659 660 index_msb = get_count_order(smp_num_siblings); 661 662 core_bits = get_count_order(c->x86_max_cores); 663 664 c->cpu_core_id = apic->phys_pkg_id(c->initial_apicid, index_msb) & 665 ((1 << core_bits) - 1); 666 #endif 667 } 668 get_cpu_vendor(struct cpuinfo_x86 * c)669 static void get_cpu_vendor(struct cpuinfo_x86 *c) 670 { 671 char *v = c->x86_vendor_id; 672 int i; 673 674 for (i = 0; i < X86_VENDOR_NUM; i++) { 675 if (!cpu_devs[i]) 676 break; 677 678 if (!strcmp(v, cpu_devs[i]->c_ident[0]) || 679 (cpu_devs[i]->c_ident[1] && 680 !strcmp(v, cpu_devs[i]->c_ident[1]))) { 681 682 this_cpu = cpu_devs[i]; 683 c->x86_vendor = this_cpu->c_x86_vendor; 684 return; 685 } 686 } 687 688 pr_err_once("CPU: vendor_id '%s' unknown, using generic init.\n" \ 689 "CPU: Your system may be unstable.\n", v); 690 691 c->x86_vendor = X86_VENDOR_UNKNOWN; 692 this_cpu = &default_cpu; 693 } 694 cpu_detect(struct cpuinfo_x86 * c)695 void cpu_detect(struct cpuinfo_x86 *c) 696 { 697 /* Get vendor name */ 698 cpuid(0x00000000, (unsigned int *)&c->cpuid_level, 699 (unsigned int *)&c->x86_vendor_id[0], 700 (unsigned int *)&c->x86_vendor_id[8], 701 (unsigned int *)&c->x86_vendor_id[4]); 702 703 c->x86 = 4; 704 /* Intel-defined flags: level 0x00000001 */ 705 if (c->cpuid_level >= 0x00000001) { 706 u32 junk, tfms, cap0, misc; 707 708 cpuid(0x00000001, &tfms, &misc, &junk, &cap0); 709 c->x86 = x86_family(tfms); 710 c->x86_model = x86_model(tfms); 711 c->x86_stepping = x86_stepping(tfms); 712 713 if (cap0 & (1<<19)) { 714 c->x86_clflush_size = ((misc >> 8) & 0xff) * 8; 715 c->x86_cache_alignment = c->x86_clflush_size; 716 } 717 } 718 } 719 apply_forced_caps(struct cpuinfo_x86 * c)720 static void apply_forced_caps(struct cpuinfo_x86 *c) 721 { 722 int i; 723 724 for (i = 0; i < NCAPINTS + NBUGINTS; i++) { 725 c->x86_capability[i] &= ~cpu_caps_cleared[i]; 726 c->x86_capability[i] |= cpu_caps_set[i]; 727 } 728 } 729 init_speculation_control(struct cpuinfo_x86 * c)730 static void init_speculation_control(struct cpuinfo_x86 *c) 731 { 732 /* 733 * The Intel SPEC_CTRL CPUID bit implies IBRS and IBPB support, 734 * and they also have a different bit for STIBP support. Also, 735 * a hypervisor might have set the individual AMD bits even on 736 * Intel CPUs, for finer-grained selection of what's available. 737 */ 738 if (cpu_has(c, X86_FEATURE_SPEC_CTRL)) { 739 set_cpu_cap(c, X86_FEATURE_IBRS); 740 set_cpu_cap(c, X86_FEATURE_IBPB); 741 set_cpu_cap(c, X86_FEATURE_MSR_SPEC_CTRL); 742 } 743 744 if (cpu_has(c, X86_FEATURE_INTEL_STIBP)) 745 set_cpu_cap(c, X86_FEATURE_STIBP); 746 747 if (cpu_has(c, X86_FEATURE_SPEC_CTRL_SSBD) || 748 cpu_has(c, X86_FEATURE_VIRT_SSBD)) 749 set_cpu_cap(c, X86_FEATURE_SSBD); 750 751 if (cpu_has(c, X86_FEATURE_AMD_IBRS)) { 752 set_cpu_cap(c, X86_FEATURE_IBRS); 753 set_cpu_cap(c, X86_FEATURE_MSR_SPEC_CTRL); 754 } 755 756 if (cpu_has(c, X86_FEATURE_AMD_IBPB)) 757 set_cpu_cap(c, X86_FEATURE_IBPB); 758 759 if (cpu_has(c, X86_FEATURE_AMD_STIBP)) { 760 set_cpu_cap(c, X86_FEATURE_STIBP); 761 set_cpu_cap(c, X86_FEATURE_MSR_SPEC_CTRL); 762 } 763 764 if (cpu_has(c, X86_FEATURE_AMD_SSBD)) { 765 set_cpu_cap(c, X86_FEATURE_SSBD); 766 set_cpu_cap(c, X86_FEATURE_MSR_SPEC_CTRL); 767 clear_cpu_cap(c, X86_FEATURE_VIRT_SSBD); 768 } 769 } 770 init_cqm(struct cpuinfo_x86 * c)771 static void init_cqm(struct cpuinfo_x86 *c) 772 { 773 if (!cpu_has(c, X86_FEATURE_CQM_LLC)) { 774 c->x86_cache_max_rmid = -1; 775 c->x86_cache_occ_scale = -1; 776 return; 777 } 778 779 /* will be overridden if occupancy monitoring exists */ 780 c->x86_cache_max_rmid = cpuid_ebx(0xf); 781 782 if (cpu_has(c, X86_FEATURE_CQM_OCCUP_LLC) || 783 cpu_has(c, X86_FEATURE_CQM_MBM_TOTAL) || 784 cpu_has(c, X86_FEATURE_CQM_MBM_LOCAL)) { 785 u32 eax, ebx, ecx, edx; 786 787 /* QoS sub-leaf, EAX=0Fh, ECX=1 */ 788 cpuid_count(0xf, 1, &eax, &ebx, &ecx, &edx); 789 790 c->x86_cache_max_rmid = ecx; 791 c->x86_cache_occ_scale = ebx; 792 } 793 } 794 get_cpu_cap(struct cpuinfo_x86 * c)795 void get_cpu_cap(struct cpuinfo_x86 *c) 796 { 797 u32 eax, ebx, ecx, edx; 798 799 /* Intel-defined flags: level 0x00000001 */ 800 if (c->cpuid_level >= 0x00000001) { 801 cpuid(0x00000001, &eax, &ebx, &ecx, &edx); 802 803 c->x86_capability[CPUID_1_ECX] = ecx; 804 c->x86_capability[CPUID_1_EDX] = edx; 805 } 806 807 /* Thermal and Power Management Leaf: level 0x00000006 (eax) */ 808 if (c->cpuid_level >= 0x00000006) 809 c->x86_capability[CPUID_6_EAX] = cpuid_eax(0x00000006); 810 811 /* Additional Intel-defined flags: level 0x00000007 */ 812 if (c->cpuid_level >= 0x00000007) { 813 cpuid_count(0x00000007, 0, &eax, &ebx, &ecx, &edx); 814 c->x86_capability[CPUID_7_0_EBX] = ebx; 815 c->x86_capability[CPUID_7_ECX] = ecx; 816 c->x86_capability[CPUID_7_EDX] = edx; 817 } 818 819 /* Extended state features: level 0x0000000d */ 820 if (c->cpuid_level >= 0x0000000d) { 821 cpuid_count(0x0000000d, 1, &eax, &ebx, &ecx, &edx); 822 823 c->x86_capability[CPUID_D_1_EAX] = eax; 824 } 825 826 /* AMD-defined flags: level 0x80000001 */ 827 eax = cpuid_eax(0x80000000); 828 c->extended_cpuid_level = eax; 829 830 if ((eax & 0xffff0000) == 0x80000000) { 831 if (eax >= 0x80000001) { 832 cpuid(0x80000001, &eax, &ebx, &ecx, &edx); 833 834 c->x86_capability[CPUID_8000_0001_ECX] = ecx; 835 c->x86_capability[CPUID_8000_0001_EDX] = edx; 836 } 837 } 838 839 if (c->extended_cpuid_level >= 0x80000007) { 840 cpuid(0x80000007, &eax, &ebx, &ecx, &edx); 841 842 c->x86_capability[CPUID_8000_0007_EBX] = ebx; 843 c->x86_power = edx; 844 } 845 846 if (c->extended_cpuid_level >= 0x80000008) { 847 cpuid(0x80000008, &eax, &ebx, &ecx, &edx); 848 849 c->x86_virt_bits = (eax >> 8) & 0xff; 850 c->x86_phys_bits = eax & 0xff; 851 c->x86_capability[CPUID_8000_0008_EBX] = ebx; 852 } 853 #ifdef CONFIG_X86_32 854 else if (cpu_has(c, X86_FEATURE_PAE) || cpu_has(c, X86_FEATURE_PSE36)) 855 c->x86_phys_bits = 36; 856 #endif 857 858 if (c->extended_cpuid_level >= 0x8000000a) 859 c->x86_capability[CPUID_8000_000A_EDX] = cpuid_edx(0x8000000a); 860 861 init_scattered_cpuid_features(c); 862 init_speculation_control(c); 863 init_cqm(c); 864 865 /* 866 * Clear/Set all flags overridden by options, after probe. 867 * This needs to happen each time we re-probe, which may happen 868 * several times during CPU initialization. 869 */ 870 apply_forced_caps(c); 871 } 872 identify_cpu_without_cpuid(struct cpuinfo_x86 * c)873 static void identify_cpu_without_cpuid(struct cpuinfo_x86 *c) 874 { 875 #ifdef CONFIG_X86_32 876 int i; 877 878 /* 879 * First of all, decide if this is a 486 or higher 880 * It's a 486 if we can modify the AC flag 881 */ 882 if (flag_is_changeable_p(X86_EFLAGS_AC)) 883 c->x86 = 4; 884 else 885 c->x86 = 3; 886 887 for (i = 0; i < X86_VENDOR_NUM; i++) 888 if (cpu_devs[i] && cpu_devs[i]->c_identify) { 889 c->x86_vendor_id[0] = 0; 890 cpu_devs[i]->c_identify(c); 891 if (c->x86_vendor_id[0]) { 892 get_cpu_vendor(c); 893 break; 894 } 895 } 896 #endif 897 c->x86_cache_bits = c->x86_phys_bits; 898 } 899 900 #define NO_SPECULATION BIT(0) 901 #define NO_MELTDOWN BIT(1) 902 #define NO_SSB BIT(2) 903 #define NO_L1TF BIT(3) 904 #define NO_MDS BIT(4) 905 #define MSBDS_ONLY BIT(5) 906 #define NO_SWAPGS BIT(6) 907 #define NO_ITLB_MULTIHIT BIT(7) 908 909 #define VULNWL(_vendor, _family, _model, _whitelist) \ 910 { X86_VENDOR_##_vendor, _family, _model, X86_FEATURE_ANY, _whitelist } 911 912 #define VULNWL_INTEL(model, whitelist) \ 913 VULNWL(INTEL, 6, INTEL_FAM6_##model, whitelist) 914 915 #define VULNWL_AMD(family, whitelist) \ 916 VULNWL(AMD, family, X86_MODEL_ANY, whitelist) 917 918 static const __initconst struct x86_cpu_id cpu_vuln_whitelist[] = { 919 VULNWL(ANY, 4, X86_MODEL_ANY, NO_SPECULATION), 920 VULNWL(CENTAUR, 5, X86_MODEL_ANY, NO_SPECULATION), 921 VULNWL(INTEL, 5, X86_MODEL_ANY, NO_SPECULATION), 922 VULNWL(NSC, 5, X86_MODEL_ANY, NO_SPECULATION), 923 924 /* Intel Family 6 */ 925 VULNWL_INTEL(ATOM_SALTWELL, NO_SPECULATION | NO_ITLB_MULTIHIT), 926 VULNWL_INTEL(ATOM_SALTWELL_TABLET, NO_SPECULATION | NO_ITLB_MULTIHIT), 927 VULNWL_INTEL(ATOM_SALTWELL_MID, NO_SPECULATION | NO_ITLB_MULTIHIT), 928 VULNWL_INTEL(ATOM_BONNELL, NO_SPECULATION | NO_ITLB_MULTIHIT), 929 VULNWL_INTEL(ATOM_BONNELL_MID, NO_SPECULATION | NO_ITLB_MULTIHIT), 930 931 VULNWL_INTEL(ATOM_SILVERMONT, NO_SSB | NO_L1TF | MSBDS_ONLY | NO_SWAPGS | NO_ITLB_MULTIHIT), 932 VULNWL_INTEL(ATOM_SILVERMONT_X, NO_SSB | NO_L1TF | MSBDS_ONLY | NO_SWAPGS | NO_ITLB_MULTIHIT), 933 VULNWL_INTEL(ATOM_SILVERMONT_MID, NO_SSB | NO_L1TF | MSBDS_ONLY | NO_SWAPGS | NO_ITLB_MULTIHIT), 934 VULNWL_INTEL(ATOM_AIRMONT, NO_SSB | NO_L1TF | MSBDS_ONLY | NO_SWAPGS | NO_ITLB_MULTIHIT), 935 VULNWL_INTEL(XEON_PHI_KNL, NO_SSB | NO_L1TF | MSBDS_ONLY | NO_SWAPGS | NO_ITLB_MULTIHIT), 936 VULNWL_INTEL(XEON_PHI_KNM, NO_SSB | NO_L1TF | MSBDS_ONLY | NO_SWAPGS | NO_ITLB_MULTIHIT), 937 938 VULNWL_INTEL(CORE_YONAH, NO_SSB), 939 940 VULNWL_INTEL(ATOM_AIRMONT_MID, NO_L1TF | MSBDS_ONLY | NO_SWAPGS | NO_ITLB_MULTIHIT), 941 942 VULNWL_INTEL(ATOM_GOLDMONT, NO_MDS | NO_L1TF | NO_SWAPGS | NO_ITLB_MULTIHIT), 943 VULNWL_INTEL(ATOM_GOLDMONT_X, NO_MDS | NO_L1TF | NO_SWAPGS | NO_ITLB_MULTIHIT), 944 VULNWL_INTEL(ATOM_GOLDMONT_PLUS, NO_MDS | NO_L1TF | NO_SWAPGS | NO_ITLB_MULTIHIT), 945 946 /* 947 * Technically, swapgs isn't serializing on AMD (despite it previously 948 * being documented as such in the APM). But according to AMD, %gs is 949 * updated non-speculatively, and the issuing of %gs-relative memory 950 * operands will be blocked until the %gs update completes, which is 951 * good enough for our purposes. 952 */ 953 954 VULNWL_INTEL(ATOM_TREMONT_X, NO_ITLB_MULTIHIT), 955 956 /* AMD Family 0xf - 0x12 */ 957 VULNWL_AMD(0x0f, NO_MELTDOWN | NO_SSB | NO_L1TF | NO_MDS | NO_SWAPGS | NO_ITLB_MULTIHIT), 958 VULNWL_AMD(0x10, NO_MELTDOWN | NO_SSB | NO_L1TF | NO_MDS | NO_SWAPGS | NO_ITLB_MULTIHIT), 959 VULNWL_AMD(0x11, NO_MELTDOWN | NO_SSB | NO_L1TF | NO_MDS | NO_SWAPGS | NO_ITLB_MULTIHIT), 960 VULNWL_AMD(0x12, NO_MELTDOWN | NO_SSB | NO_L1TF | NO_MDS | NO_SWAPGS | NO_ITLB_MULTIHIT), 961 962 /* FAMILY_ANY must be last, otherwise 0x0f - 0x12 matches won't work */ 963 VULNWL_AMD(X86_FAMILY_ANY, NO_MELTDOWN | NO_L1TF | NO_MDS | NO_SWAPGS | NO_ITLB_MULTIHIT), 964 {} 965 }; 966 cpu_matches(unsigned long which)967 static bool __init cpu_matches(unsigned long which) 968 { 969 const struct x86_cpu_id *m = x86_match_cpu(cpu_vuln_whitelist); 970 971 return m && !!(m->driver_data & which); 972 } 973 x86_read_arch_cap_msr(void)974 u64 x86_read_arch_cap_msr(void) 975 { 976 u64 ia32_cap = 0; 977 978 if (boot_cpu_has(X86_FEATURE_ARCH_CAPABILITIES)) 979 rdmsrl(MSR_IA32_ARCH_CAPABILITIES, ia32_cap); 980 981 return ia32_cap; 982 } 983 cpu_set_bug_bits(struct cpuinfo_x86 * c)984 static void __init cpu_set_bug_bits(struct cpuinfo_x86 *c) 985 { 986 u64 ia32_cap = x86_read_arch_cap_msr(); 987 988 /* Set ITLB_MULTIHIT bug if cpu is not in the whitelist and not mitigated */ 989 if (!cpu_matches(NO_ITLB_MULTIHIT) && !(ia32_cap & ARCH_CAP_PSCHANGE_MC_NO)) 990 setup_force_cpu_bug(X86_BUG_ITLB_MULTIHIT); 991 992 if (cpu_matches(NO_SPECULATION)) 993 return; 994 995 setup_force_cpu_bug(X86_BUG_SPECTRE_V1); 996 setup_force_cpu_bug(X86_BUG_SPECTRE_V2); 997 998 if (!cpu_matches(NO_SSB) && !(ia32_cap & ARCH_CAP_SSB_NO) && 999 !cpu_has(c, X86_FEATURE_AMD_SSB_NO)) 1000 setup_force_cpu_bug(X86_BUG_SPEC_STORE_BYPASS); 1001 1002 if (ia32_cap & ARCH_CAP_IBRS_ALL) 1003 setup_force_cpu_cap(X86_FEATURE_IBRS_ENHANCED); 1004 1005 if (!cpu_matches(NO_MDS) && !(ia32_cap & ARCH_CAP_MDS_NO)) { 1006 setup_force_cpu_bug(X86_BUG_MDS); 1007 if (cpu_matches(MSBDS_ONLY)) 1008 setup_force_cpu_bug(X86_BUG_MSBDS_ONLY); 1009 } 1010 1011 if (!cpu_matches(NO_SWAPGS)) 1012 setup_force_cpu_bug(X86_BUG_SWAPGS); 1013 1014 /* 1015 * When the CPU is not mitigated for TAA (TAA_NO=0) set TAA bug when: 1016 * - TSX is supported or 1017 * - TSX_CTRL is present 1018 * 1019 * TSX_CTRL check is needed for cases when TSX could be disabled before 1020 * the kernel boot e.g. kexec. 1021 * TSX_CTRL check alone is not sufficient for cases when the microcode 1022 * update is not present or running as guest that don't get TSX_CTRL. 1023 */ 1024 if (!(ia32_cap & ARCH_CAP_TAA_NO) && 1025 (cpu_has(c, X86_FEATURE_RTM) || 1026 (ia32_cap & ARCH_CAP_TSX_CTRL_MSR))) 1027 setup_force_cpu_bug(X86_BUG_TAA); 1028 1029 if (cpu_matches(NO_MELTDOWN)) 1030 return; 1031 1032 /* Rogue Data Cache Load? No! */ 1033 if (ia32_cap & ARCH_CAP_RDCL_NO) 1034 return; 1035 1036 setup_force_cpu_bug(X86_BUG_CPU_MELTDOWN); 1037 1038 if (cpu_matches(NO_L1TF)) 1039 return; 1040 1041 setup_force_cpu_bug(X86_BUG_L1TF); 1042 } 1043 1044 /* 1045 * Do minimum CPU detection early. 1046 * Fields really needed: vendor, cpuid_level, family, model, mask, 1047 * cache alignment. 1048 * The others are not touched to avoid unwanted side effects. 1049 * 1050 * WARNING: this function is only called on the BP. Don't add code here 1051 * that is supposed to run on all CPUs. 1052 */ early_identify_cpu(struct cpuinfo_x86 * c)1053 static void __init early_identify_cpu(struct cpuinfo_x86 *c) 1054 { 1055 #ifdef CONFIG_X86_64 1056 c->x86_clflush_size = 64; 1057 c->x86_phys_bits = 36; 1058 c->x86_virt_bits = 48; 1059 #else 1060 c->x86_clflush_size = 32; 1061 c->x86_phys_bits = 32; 1062 c->x86_virt_bits = 32; 1063 #endif 1064 c->x86_cache_alignment = c->x86_clflush_size; 1065 1066 memset(&c->x86_capability, 0, sizeof c->x86_capability); 1067 c->extended_cpuid_level = 0; 1068 1069 if (!have_cpuid_p()) 1070 identify_cpu_without_cpuid(c); 1071 1072 /* cyrix could have cpuid enabled via c_identify()*/ 1073 if (have_cpuid_p()) { 1074 cpu_detect(c); 1075 get_cpu_vendor(c); 1076 get_cpu_cap(c); 1077 setup_force_cpu_cap(X86_FEATURE_CPUID); 1078 1079 if (this_cpu->c_early_init) 1080 this_cpu->c_early_init(c); 1081 1082 c->cpu_index = 0; 1083 filter_cpuid_features(c, false); 1084 1085 if (this_cpu->c_bsp_init) 1086 this_cpu->c_bsp_init(c); 1087 } else { 1088 setup_clear_cpu_cap(X86_FEATURE_CPUID); 1089 } 1090 1091 setup_force_cpu_cap(X86_FEATURE_ALWAYS); 1092 1093 cpu_set_bug_bits(c); 1094 1095 fpu__init_system(c); 1096 1097 #ifdef CONFIG_X86_32 1098 /* 1099 * Regardless of whether PCID is enumerated, the SDM says 1100 * that it can't be enabled in 32-bit mode. 1101 */ 1102 setup_clear_cpu_cap(X86_FEATURE_PCID); 1103 #endif 1104 } 1105 early_cpu_init(void)1106 void __init early_cpu_init(void) 1107 { 1108 const struct cpu_dev *const *cdev; 1109 int count = 0; 1110 1111 #ifdef CONFIG_PROCESSOR_SELECT 1112 pr_info("KERNEL supported cpus:\n"); 1113 #endif 1114 1115 for (cdev = __x86_cpu_dev_start; cdev < __x86_cpu_dev_end; cdev++) { 1116 const struct cpu_dev *cpudev = *cdev; 1117 1118 if (count >= X86_VENDOR_NUM) 1119 break; 1120 cpu_devs[count] = cpudev; 1121 count++; 1122 1123 #ifdef CONFIG_PROCESSOR_SELECT 1124 { 1125 unsigned int j; 1126 1127 for (j = 0; j < 2; j++) { 1128 if (!cpudev->c_ident[j]) 1129 continue; 1130 pr_info(" %s %s\n", cpudev->c_vendor, 1131 cpudev->c_ident[j]); 1132 } 1133 } 1134 #endif 1135 } 1136 early_identify_cpu(&boot_cpu_data); 1137 } 1138 1139 /* 1140 * The NOPL instruction is supposed to exist on all CPUs of family >= 6; 1141 * unfortunately, that's not true in practice because of early VIA 1142 * chips and (more importantly) broken virtualizers that are not easy 1143 * to detect. In the latter case it doesn't even *fail* reliably, so 1144 * probing for it doesn't even work. Disable it completely on 32-bit 1145 * unless we can find a reliable way to detect all the broken cases. 1146 * Enable it explicitly on 64-bit for non-constant inputs of cpu_has(). 1147 */ detect_nopl(struct cpuinfo_x86 * c)1148 static void detect_nopl(struct cpuinfo_x86 *c) 1149 { 1150 #ifdef CONFIG_X86_32 1151 clear_cpu_cap(c, X86_FEATURE_NOPL); 1152 #else 1153 set_cpu_cap(c, X86_FEATURE_NOPL); 1154 #endif 1155 } 1156 detect_null_seg_behavior(struct cpuinfo_x86 * c)1157 static void detect_null_seg_behavior(struct cpuinfo_x86 *c) 1158 { 1159 #ifdef CONFIG_X86_64 1160 /* 1161 * Empirically, writing zero to a segment selector on AMD does 1162 * not clear the base, whereas writing zero to a segment 1163 * selector on Intel does clear the base. Intel's behavior 1164 * allows slightly faster context switches in the common case 1165 * where GS is unused by the prev and next threads. 1166 * 1167 * Since neither vendor documents this anywhere that I can see, 1168 * detect it directly instead of hardcoding the choice by 1169 * vendor. 1170 * 1171 * I've designated AMD's behavior as the "bug" because it's 1172 * counterintuitive and less friendly. 1173 */ 1174 1175 unsigned long old_base, tmp; 1176 rdmsrl(MSR_FS_BASE, old_base); 1177 wrmsrl(MSR_FS_BASE, 1); 1178 loadsegment(fs, 0); 1179 rdmsrl(MSR_FS_BASE, tmp); 1180 if (tmp != 0) 1181 set_cpu_bug(c, X86_BUG_NULL_SEG); 1182 wrmsrl(MSR_FS_BASE, old_base); 1183 #endif 1184 } 1185 generic_identify(struct cpuinfo_x86 * c)1186 static void generic_identify(struct cpuinfo_x86 *c) 1187 { 1188 c->extended_cpuid_level = 0; 1189 1190 if (!have_cpuid_p()) 1191 identify_cpu_without_cpuid(c); 1192 1193 /* cyrix could have cpuid enabled via c_identify()*/ 1194 if (!have_cpuid_p()) 1195 return; 1196 1197 cpu_detect(c); 1198 1199 get_cpu_vendor(c); 1200 1201 get_cpu_cap(c); 1202 1203 if (c->cpuid_level >= 0x00000001) { 1204 c->initial_apicid = (cpuid_ebx(1) >> 24) & 0xFF; 1205 #ifdef CONFIG_X86_32 1206 # ifdef CONFIG_SMP 1207 c->apicid = apic->phys_pkg_id(c->initial_apicid, 0); 1208 # else 1209 c->apicid = c->initial_apicid; 1210 # endif 1211 #endif 1212 c->phys_proc_id = c->initial_apicid; 1213 } 1214 1215 get_model_name(c); /* Default name */ 1216 1217 detect_nopl(c); 1218 1219 detect_null_seg_behavior(c); 1220 1221 /* 1222 * ESPFIX is a strange bug. All real CPUs have it. Paravirt 1223 * systems that run Linux at CPL > 0 may or may not have the 1224 * issue, but, even if they have the issue, there's absolutely 1225 * nothing we can do about it because we can't use the real IRET 1226 * instruction. 1227 * 1228 * NB: For the time being, only 32-bit kernels support 1229 * X86_BUG_ESPFIX as such. 64-bit kernels directly choose 1230 * whether to apply espfix using paravirt hooks. If any 1231 * non-paravirt system ever shows up that does *not* have the 1232 * ESPFIX issue, we can change this. 1233 */ 1234 #ifdef CONFIG_X86_32 1235 # ifdef CONFIG_PARAVIRT 1236 do { 1237 extern void native_iret(void); 1238 if (pv_cpu_ops.iret == native_iret) 1239 set_cpu_bug(c, X86_BUG_ESPFIX); 1240 } while (0); 1241 # else 1242 set_cpu_bug(c, X86_BUG_ESPFIX); 1243 # endif 1244 #endif 1245 } 1246 x86_init_cache_qos(struct cpuinfo_x86 * c)1247 static void x86_init_cache_qos(struct cpuinfo_x86 *c) 1248 { 1249 /* 1250 * The heavy lifting of max_rmid and cache_occ_scale are handled 1251 * in get_cpu_cap(). Here we just set the max_rmid for the boot_cpu 1252 * in case CQM bits really aren't there in this CPU. 1253 */ 1254 if (c != &boot_cpu_data) { 1255 boot_cpu_data.x86_cache_max_rmid = 1256 min(boot_cpu_data.x86_cache_max_rmid, 1257 c->x86_cache_max_rmid); 1258 } 1259 } 1260 1261 /* 1262 * Validate that ACPI/mptables have the same information about the 1263 * effective APIC id and update the package map. 1264 */ validate_apic_and_package_id(struct cpuinfo_x86 * c)1265 static void validate_apic_and_package_id(struct cpuinfo_x86 *c) 1266 { 1267 #ifdef CONFIG_SMP 1268 unsigned int apicid, cpu = smp_processor_id(); 1269 1270 apicid = apic->cpu_present_to_apicid(cpu); 1271 1272 if (apicid != c->apicid) { 1273 pr_err(FW_BUG "CPU%u: APIC id mismatch. Firmware: %x APIC: %x\n", 1274 cpu, apicid, c->initial_apicid); 1275 } 1276 BUG_ON(topology_update_package_map(c->phys_proc_id, cpu)); 1277 #else 1278 c->logical_proc_id = 0; 1279 #endif 1280 } 1281 1282 /* 1283 * This does the hard work of actually picking apart the CPU stuff... 1284 */ identify_cpu(struct cpuinfo_x86 * c)1285 static void identify_cpu(struct cpuinfo_x86 *c) 1286 { 1287 int i; 1288 1289 c->loops_per_jiffy = loops_per_jiffy; 1290 c->x86_cache_size = 0; 1291 c->x86_vendor = X86_VENDOR_UNKNOWN; 1292 c->x86_model = c->x86_stepping = 0; /* So far unknown... */ 1293 c->x86_vendor_id[0] = '\0'; /* Unset */ 1294 c->x86_model_id[0] = '\0'; /* Unset */ 1295 c->x86_max_cores = 1; 1296 c->x86_coreid_bits = 0; 1297 c->cu_id = 0xff; 1298 #ifdef CONFIG_X86_64 1299 c->x86_clflush_size = 64; 1300 c->x86_phys_bits = 36; 1301 c->x86_virt_bits = 48; 1302 #else 1303 c->cpuid_level = -1; /* CPUID not detected */ 1304 c->x86_clflush_size = 32; 1305 c->x86_phys_bits = 32; 1306 c->x86_virt_bits = 32; 1307 #endif 1308 c->x86_cache_alignment = c->x86_clflush_size; 1309 memset(&c->x86_capability, 0, sizeof c->x86_capability); 1310 1311 generic_identify(c); 1312 1313 if (this_cpu->c_identify) 1314 this_cpu->c_identify(c); 1315 1316 /* Clear/Set all flags overridden by options, after probe */ 1317 apply_forced_caps(c); 1318 1319 #ifdef CONFIG_X86_64 1320 c->apicid = apic->phys_pkg_id(c->initial_apicid, 0); 1321 #endif 1322 1323 /* 1324 * Vendor-specific initialization. In this section we 1325 * canonicalize the feature flags, meaning if there are 1326 * features a certain CPU supports which CPUID doesn't 1327 * tell us, CPUID claiming incorrect flags, or other bugs, 1328 * we handle them here. 1329 * 1330 * At the end of this section, c->x86_capability better 1331 * indicate the features this CPU genuinely supports! 1332 */ 1333 if (this_cpu->c_init) 1334 this_cpu->c_init(c); 1335 1336 /* Disable the PN if appropriate */ 1337 squash_the_stupid_serial_number(c); 1338 1339 /* Set up SMEP/SMAP */ 1340 setup_smep(c); 1341 setup_smap(c); 1342 1343 /* 1344 * The vendor-specific functions might have changed features. 1345 * Now we do "generic changes." 1346 */ 1347 1348 /* Filter out anything that depends on CPUID levels we don't have */ 1349 filter_cpuid_features(c, true); 1350 1351 /* If the model name is still unset, do table lookup. */ 1352 if (!c->x86_model_id[0]) { 1353 const char *p; 1354 p = table_lookup_model(c); 1355 if (p) 1356 strcpy(c->x86_model_id, p); 1357 else 1358 /* Last resort... */ 1359 sprintf(c->x86_model_id, "%02x/%02x", 1360 c->x86, c->x86_model); 1361 } 1362 1363 #ifdef CONFIG_X86_64 1364 detect_ht(c); 1365 #endif 1366 1367 x86_init_rdrand(c); 1368 x86_init_cache_qos(c); 1369 setup_pku(c); 1370 1371 /* 1372 * Clear/Set all flags overridden by options, need do it 1373 * before following smp all cpus cap AND. 1374 */ 1375 apply_forced_caps(c); 1376 1377 /* 1378 * On SMP, boot_cpu_data holds the common feature set between 1379 * all CPUs; so make sure that we indicate which features are 1380 * common between the CPUs. The first time this routine gets 1381 * executed, c == &boot_cpu_data. 1382 */ 1383 if (c != &boot_cpu_data) { 1384 /* AND the already accumulated flags with these */ 1385 for (i = 0; i < NCAPINTS; i++) 1386 boot_cpu_data.x86_capability[i] &= c->x86_capability[i]; 1387 1388 /* OR, i.e. replicate the bug flags */ 1389 for (i = NCAPINTS; i < NCAPINTS + NBUGINTS; i++) 1390 c->x86_capability[i] |= boot_cpu_data.x86_capability[i]; 1391 } 1392 1393 /* Init Machine Check Exception if available. */ 1394 mcheck_cpu_init(c); 1395 1396 select_idle_routine(c); 1397 1398 #ifdef CONFIG_NUMA 1399 numa_add_cpu(smp_processor_id()); 1400 #endif 1401 } 1402 1403 /* 1404 * Set up the CPU state needed to execute SYSENTER/SYSEXIT instructions 1405 * on 32-bit kernels: 1406 */ 1407 #ifdef CONFIG_X86_32 enable_sep_cpu(void)1408 void enable_sep_cpu(void) 1409 { 1410 struct tss_struct *tss; 1411 int cpu; 1412 1413 if (!boot_cpu_has(X86_FEATURE_SEP)) 1414 return; 1415 1416 cpu = get_cpu(); 1417 tss = &per_cpu(cpu_tss_rw, cpu); 1418 1419 /* 1420 * We cache MSR_IA32_SYSENTER_CS's value in the TSS's ss1 field -- 1421 * see the big comment in struct x86_hw_tss's definition. 1422 */ 1423 1424 tss->x86_tss.ss1 = __KERNEL_CS; 1425 wrmsr(MSR_IA32_SYSENTER_CS, tss->x86_tss.ss1, 0); 1426 wrmsr(MSR_IA32_SYSENTER_ESP, (unsigned long)(cpu_entry_stack(cpu) + 1), 0); 1427 wrmsr(MSR_IA32_SYSENTER_EIP, (unsigned long)entry_SYSENTER_32, 0); 1428 1429 put_cpu(); 1430 } 1431 #endif 1432 identify_boot_cpu(void)1433 void __init identify_boot_cpu(void) 1434 { 1435 identify_cpu(&boot_cpu_data); 1436 #ifdef CONFIG_X86_32 1437 sysenter_setup(); 1438 enable_sep_cpu(); 1439 #endif 1440 cpu_detect_tlb(&boot_cpu_data); 1441 tsx_init(); 1442 } 1443 identify_secondary_cpu(struct cpuinfo_x86 * c)1444 void identify_secondary_cpu(struct cpuinfo_x86 *c) 1445 { 1446 BUG_ON(c == &boot_cpu_data); 1447 identify_cpu(c); 1448 #ifdef CONFIG_X86_32 1449 enable_sep_cpu(); 1450 #endif 1451 mtrr_ap_init(); 1452 validate_apic_and_package_id(c); 1453 x86_spec_ctrl_setup_ap(); 1454 } 1455 setup_noclflush(char * arg)1456 static __init int setup_noclflush(char *arg) 1457 { 1458 setup_clear_cpu_cap(X86_FEATURE_CLFLUSH); 1459 setup_clear_cpu_cap(X86_FEATURE_CLFLUSHOPT); 1460 return 1; 1461 } 1462 __setup("noclflush", setup_noclflush); 1463 print_cpu_info(struct cpuinfo_x86 * c)1464 void print_cpu_info(struct cpuinfo_x86 *c) 1465 { 1466 const char *vendor = NULL; 1467 1468 if (c->x86_vendor < X86_VENDOR_NUM) { 1469 vendor = this_cpu->c_vendor; 1470 } else { 1471 if (c->cpuid_level >= 0) 1472 vendor = c->x86_vendor_id; 1473 } 1474 1475 if (vendor && !strstr(c->x86_model_id, vendor)) 1476 pr_cont("%s ", vendor); 1477 1478 if (c->x86_model_id[0]) 1479 pr_cont("%s", c->x86_model_id); 1480 else 1481 pr_cont("%d86", c->x86); 1482 1483 pr_cont(" (family: 0x%x, model: 0x%x", c->x86, c->x86_model); 1484 1485 if (c->x86_stepping || c->cpuid_level >= 0) 1486 pr_cont(", stepping: 0x%x)\n", c->x86_stepping); 1487 else 1488 pr_cont(")\n"); 1489 } 1490 1491 /* 1492 * clearcpuid= was already parsed in fpu__init_parse_early_param. 1493 * But we need to keep a dummy __setup around otherwise it would 1494 * show up as an environment variable for init. 1495 */ setup_clearcpuid(char * arg)1496 static __init int setup_clearcpuid(char *arg) 1497 { 1498 return 1; 1499 } 1500 __setup("clearcpuid=", setup_clearcpuid); 1501 1502 #ifdef CONFIG_X86_64 1503 DEFINE_PER_CPU_FIRST(union irq_stack_union, 1504 irq_stack_union) __aligned(PAGE_SIZE) __visible; 1505 1506 /* 1507 * The following percpu variables are hot. Align current_task to 1508 * cacheline size such that they fall in the same cacheline. 1509 */ 1510 DEFINE_PER_CPU(struct task_struct *, current_task) ____cacheline_aligned = 1511 &init_task; 1512 EXPORT_PER_CPU_SYMBOL(current_task); 1513 1514 DEFINE_PER_CPU(char *, irq_stack_ptr) = 1515 init_per_cpu_var(irq_stack_union.irq_stack) + IRQ_STACK_SIZE; 1516 1517 DEFINE_PER_CPU(unsigned int, irq_count) __visible = -1; 1518 1519 DEFINE_PER_CPU(int, __preempt_count) = INIT_PREEMPT_COUNT; 1520 EXPORT_PER_CPU_SYMBOL(__preempt_count); 1521 1522 /* May not be marked __init: used by software suspend */ syscall_init(void)1523 void syscall_init(void) 1524 { 1525 extern char _entry_trampoline[]; 1526 extern char entry_SYSCALL_64_trampoline[]; 1527 1528 int cpu = smp_processor_id(); 1529 unsigned long SYSCALL64_entry_trampoline = 1530 (unsigned long)get_cpu_entry_area(cpu)->entry_trampoline + 1531 (entry_SYSCALL_64_trampoline - _entry_trampoline); 1532 1533 wrmsr(MSR_STAR, 0, (__USER32_CS << 16) | __KERNEL_CS); 1534 if (static_cpu_has(X86_FEATURE_PTI)) 1535 wrmsrl(MSR_LSTAR, SYSCALL64_entry_trampoline); 1536 else 1537 wrmsrl(MSR_LSTAR, (unsigned long)entry_SYSCALL_64); 1538 1539 #ifdef CONFIG_IA32_EMULATION 1540 wrmsrl(MSR_CSTAR, (unsigned long)entry_SYSCALL_compat); 1541 /* 1542 * This only works on Intel CPUs. 1543 * On AMD CPUs these MSRs are 32-bit, CPU truncates MSR_IA32_SYSENTER_EIP. 1544 * This does not cause SYSENTER to jump to the wrong location, because 1545 * AMD doesn't allow SYSENTER in long mode (either 32- or 64-bit). 1546 */ 1547 wrmsrl_safe(MSR_IA32_SYSENTER_CS, (u64)__KERNEL_CS); 1548 wrmsrl_safe(MSR_IA32_SYSENTER_ESP, (unsigned long)(cpu_entry_stack(cpu) + 1)); 1549 wrmsrl_safe(MSR_IA32_SYSENTER_EIP, (u64)entry_SYSENTER_compat); 1550 #else 1551 wrmsrl(MSR_CSTAR, (unsigned long)ignore_sysret); 1552 wrmsrl_safe(MSR_IA32_SYSENTER_CS, (u64)GDT_ENTRY_INVALID_SEG); 1553 wrmsrl_safe(MSR_IA32_SYSENTER_ESP, 0ULL); 1554 wrmsrl_safe(MSR_IA32_SYSENTER_EIP, 0ULL); 1555 #endif 1556 1557 /* Flags to clear on syscall */ 1558 wrmsrl(MSR_SYSCALL_MASK, 1559 X86_EFLAGS_TF|X86_EFLAGS_DF|X86_EFLAGS_IF| 1560 X86_EFLAGS_IOPL|X86_EFLAGS_AC|X86_EFLAGS_NT); 1561 } 1562 1563 /* 1564 * Copies of the original ist values from the tss are only accessed during 1565 * debugging, no special alignment required. 1566 */ 1567 DEFINE_PER_CPU(struct orig_ist, orig_ist); 1568 1569 static DEFINE_PER_CPU(unsigned long, debug_stack_addr); 1570 DEFINE_PER_CPU(int, debug_stack_usage); 1571 is_debug_stack(unsigned long addr)1572 int is_debug_stack(unsigned long addr) 1573 { 1574 return __this_cpu_read(debug_stack_usage) || 1575 (addr <= __this_cpu_read(debug_stack_addr) && 1576 addr > (__this_cpu_read(debug_stack_addr) - DEBUG_STKSZ)); 1577 } 1578 NOKPROBE_SYMBOL(is_debug_stack); 1579 1580 DEFINE_PER_CPU(u32, debug_idt_ctr); 1581 debug_stack_set_zero(void)1582 void debug_stack_set_zero(void) 1583 { 1584 this_cpu_inc(debug_idt_ctr); 1585 load_current_idt(); 1586 } 1587 NOKPROBE_SYMBOL(debug_stack_set_zero); 1588 debug_stack_reset(void)1589 void debug_stack_reset(void) 1590 { 1591 if (WARN_ON(!this_cpu_read(debug_idt_ctr))) 1592 return; 1593 if (this_cpu_dec_return(debug_idt_ctr) == 0) 1594 load_current_idt(); 1595 } 1596 NOKPROBE_SYMBOL(debug_stack_reset); 1597 1598 #else /* CONFIG_X86_64 */ 1599 1600 DEFINE_PER_CPU(struct task_struct *, current_task) = &init_task; 1601 EXPORT_PER_CPU_SYMBOL(current_task); 1602 DEFINE_PER_CPU(int, __preempt_count) = INIT_PREEMPT_COUNT; 1603 EXPORT_PER_CPU_SYMBOL(__preempt_count); 1604 1605 /* 1606 * On x86_32, vm86 modifies tss.sp0, so sp0 isn't a reliable way to find 1607 * the top of the kernel stack. Use an extra percpu variable to track the 1608 * top of the kernel stack directly. 1609 */ 1610 DEFINE_PER_CPU(unsigned long, cpu_current_top_of_stack) = 1611 (unsigned long)&init_thread_union + THREAD_SIZE; 1612 EXPORT_PER_CPU_SYMBOL(cpu_current_top_of_stack); 1613 1614 #ifdef CONFIG_CC_STACKPROTECTOR 1615 DEFINE_PER_CPU_ALIGNED(struct stack_canary, stack_canary); 1616 #endif 1617 1618 #endif /* CONFIG_X86_64 */ 1619 1620 /* 1621 * Clear all 6 debug registers: 1622 */ clear_all_debug_regs(void)1623 static void clear_all_debug_regs(void) 1624 { 1625 int i; 1626 1627 for (i = 0; i < 8; i++) { 1628 /* Ignore db4, db5 */ 1629 if ((i == 4) || (i == 5)) 1630 continue; 1631 1632 set_debugreg(0, i); 1633 } 1634 } 1635 1636 #ifdef CONFIG_KGDB 1637 /* 1638 * Restore debug regs if using kgdbwait and you have a kernel debugger 1639 * connection established. 1640 */ dbg_restore_debug_regs(void)1641 static void dbg_restore_debug_regs(void) 1642 { 1643 if (unlikely(kgdb_connected && arch_kgdb_ops.correct_hw_break)) 1644 arch_kgdb_ops.correct_hw_break(); 1645 } 1646 #else /* ! CONFIG_KGDB */ 1647 #define dbg_restore_debug_regs() 1648 #endif /* ! CONFIG_KGDB */ 1649 wait_for_master_cpu(int cpu)1650 static void wait_for_master_cpu(int cpu) 1651 { 1652 #ifdef CONFIG_SMP 1653 /* 1654 * wait for ACK from master CPU before continuing 1655 * with AP initialization 1656 */ 1657 WARN_ON(cpumask_test_and_set_cpu(cpu, cpu_initialized_mask)); 1658 while (!cpumask_test_cpu(cpu, cpu_callout_mask)) 1659 cpu_relax(); 1660 #endif 1661 } 1662 1663 /* 1664 * cpu_init() initializes state that is per-CPU. Some data is already 1665 * initialized (naturally) in the bootstrap process, such as the GDT 1666 * and IDT. We reload them nevertheless, this function acts as a 1667 * 'CPU state barrier', nothing should get across. 1668 * A lot of state is already set up in PDA init for 64 bit 1669 */ 1670 #ifdef CONFIG_X86_64 1671 cpu_init(void)1672 void cpu_init(void) 1673 { 1674 struct orig_ist *oist; 1675 struct task_struct *me; 1676 struct tss_struct *t; 1677 unsigned long v; 1678 int cpu = raw_smp_processor_id(); 1679 int i; 1680 1681 wait_for_master_cpu(cpu); 1682 1683 /* 1684 * Initialize the CR4 shadow before doing anything that could 1685 * try to read it. 1686 */ 1687 cr4_init_shadow(); 1688 1689 if (cpu) 1690 load_ucode_ap(); 1691 1692 t = &per_cpu(cpu_tss_rw, cpu); 1693 oist = &per_cpu(orig_ist, cpu); 1694 1695 #ifdef CONFIG_NUMA 1696 if (this_cpu_read(numa_node) == 0 && 1697 early_cpu_to_node(cpu) != NUMA_NO_NODE) 1698 set_numa_node(early_cpu_to_node(cpu)); 1699 #endif 1700 1701 me = current; 1702 1703 pr_debug("Initializing CPU#%d\n", cpu); 1704 1705 cr4_clear_bits(X86_CR4_VME|X86_CR4_PVI|X86_CR4_TSD|X86_CR4_DE); 1706 1707 /* 1708 * Initialize the per-CPU GDT with the boot GDT, 1709 * and set up the GDT descriptor: 1710 */ 1711 1712 switch_to_new_gdt(cpu); 1713 loadsegment(fs, 0); 1714 1715 load_current_idt(); 1716 1717 memset(me->thread.tls_array, 0, GDT_ENTRY_TLS_ENTRIES * 8); 1718 syscall_init(); 1719 1720 wrmsrl(MSR_FS_BASE, 0); 1721 wrmsrl(MSR_KERNEL_GS_BASE, 0); 1722 barrier(); 1723 1724 x86_configure_nx(); 1725 x2apic_setup(); 1726 1727 /* 1728 * set up and load the per-CPU TSS 1729 */ 1730 if (!oist->ist[0]) { 1731 char *estacks = get_cpu_entry_area(cpu)->exception_stacks; 1732 1733 for (v = 0; v < N_EXCEPTION_STACKS; v++) { 1734 estacks += exception_stack_sizes[v]; 1735 oist->ist[v] = t->x86_tss.ist[v] = 1736 (unsigned long)estacks; 1737 if (v == DEBUG_STACK-1) 1738 per_cpu(debug_stack_addr, cpu) = (unsigned long)estacks; 1739 } 1740 } 1741 1742 t->x86_tss.io_bitmap_base = IO_BITMAP_OFFSET; 1743 1744 /* 1745 * <= is required because the CPU will access up to 1746 * 8 bits beyond the end of the IO permission bitmap. 1747 */ 1748 for (i = 0; i <= IO_BITMAP_LONGS; i++) 1749 t->io_bitmap[i] = ~0UL; 1750 1751 mmgrab(&init_mm); 1752 me->active_mm = &init_mm; 1753 BUG_ON(me->mm); 1754 initialize_tlbstate_and_flush(); 1755 enter_lazy_tlb(&init_mm, me); 1756 1757 /* 1758 * Initialize the TSS. sp0 points to the entry trampoline stack 1759 * regardless of what task is running. 1760 */ 1761 set_tss_desc(cpu, &get_cpu_entry_area(cpu)->tss.x86_tss); 1762 load_TR_desc(); 1763 load_sp0((unsigned long)(cpu_entry_stack(cpu) + 1)); 1764 1765 load_mm_ldt(&init_mm); 1766 1767 clear_all_debug_regs(); 1768 dbg_restore_debug_regs(); 1769 1770 fpu__init_cpu(); 1771 1772 if (is_uv_system()) 1773 uv_cpu_init(); 1774 1775 load_fixmap_gdt(cpu); 1776 } 1777 1778 #else 1779 cpu_init(void)1780 void cpu_init(void) 1781 { 1782 int cpu = smp_processor_id(); 1783 struct task_struct *curr = current; 1784 struct tss_struct *t = &per_cpu(cpu_tss_rw, cpu); 1785 1786 wait_for_master_cpu(cpu); 1787 1788 /* 1789 * Initialize the CR4 shadow before doing anything that could 1790 * try to read it. 1791 */ 1792 cr4_init_shadow(); 1793 1794 show_ucode_info_early(); 1795 1796 pr_info("Initializing CPU#%d\n", cpu); 1797 1798 if (cpu_feature_enabled(X86_FEATURE_VME) || 1799 boot_cpu_has(X86_FEATURE_TSC) || 1800 boot_cpu_has(X86_FEATURE_DE)) 1801 cr4_clear_bits(X86_CR4_VME|X86_CR4_PVI|X86_CR4_TSD|X86_CR4_DE); 1802 1803 load_current_idt(); 1804 switch_to_new_gdt(cpu); 1805 1806 /* 1807 * Set up and load the per-CPU TSS and LDT 1808 */ 1809 mmgrab(&init_mm); 1810 curr->active_mm = &init_mm; 1811 BUG_ON(curr->mm); 1812 initialize_tlbstate_and_flush(); 1813 enter_lazy_tlb(&init_mm, curr); 1814 1815 /* 1816 * Initialize the TSS. Don't bother initializing sp0, as the initial 1817 * task never enters user mode. 1818 */ 1819 set_tss_desc(cpu, &get_cpu_entry_area(cpu)->tss.x86_tss); 1820 load_TR_desc(); 1821 1822 load_mm_ldt(&init_mm); 1823 1824 t->x86_tss.io_bitmap_base = IO_BITMAP_OFFSET; 1825 1826 #ifdef CONFIG_DOUBLEFAULT 1827 /* Set up doublefault TSS pointer in the GDT */ 1828 __set_tss_desc(cpu, GDT_ENTRY_DOUBLEFAULT_TSS, &doublefault_tss); 1829 #endif 1830 1831 clear_all_debug_regs(); 1832 dbg_restore_debug_regs(); 1833 1834 fpu__init_cpu(); 1835 1836 load_fixmap_gdt(cpu); 1837 } 1838 #endif 1839 bsp_resume(void)1840 static void bsp_resume(void) 1841 { 1842 if (this_cpu->c_bsp_resume) 1843 this_cpu->c_bsp_resume(&boot_cpu_data); 1844 } 1845 1846 static struct syscore_ops cpu_syscore_ops = { 1847 .resume = bsp_resume, 1848 }; 1849 init_cpu_syscore(void)1850 static int __init init_cpu_syscore(void) 1851 { 1852 register_syscore_ops(&cpu_syscore_ops); 1853 return 0; 1854 } 1855 core_initcall(init_cpu_syscore); 1856 1857 /* 1858 * The microcode loader calls this upon late microcode load to recheck features, 1859 * only when microcode has been updated. Caller holds microcode_mutex and CPU 1860 * hotplug lock. 1861 */ microcode_check(void)1862 void microcode_check(void) 1863 { 1864 struct cpuinfo_x86 info; 1865 1866 perf_check_microcode(); 1867 1868 /* Reload CPUID max function as it might've changed. */ 1869 info.cpuid_level = cpuid_eax(0); 1870 1871 /* 1872 * Copy all capability leafs to pick up the synthetic ones so that 1873 * memcmp() below doesn't fail on that. The ones coming from CPUID will 1874 * get overwritten in get_cpu_cap(). 1875 */ 1876 memcpy(&info.x86_capability, &boot_cpu_data.x86_capability, sizeof(info.x86_capability)); 1877 1878 get_cpu_cap(&info); 1879 1880 if (!memcmp(&info.x86_capability, &boot_cpu_data.x86_capability, sizeof(info.x86_capability))) 1881 return; 1882 1883 pr_warn("x86/CPU: CPU features have changed after loading microcode, but might not take effect.\n"); 1884 pr_warn("x86/CPU: Please consider either early loading through initrd/built-in or a potential BIOS update.\n"); 1885 } 1886