1 /*
2 * intel_mid_sfi.c: Intel MID SFI initialization code
3 *
4 * (C) Copyright 2013 Intel Corporation
5 * Author: Sathyanarayanan Kuppuswamy <sathyanarayanan.kuppuswamy@intel.com>
6 *
7 * This program is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU General Public License
9 * as published by the Free Software Foundation; version 2
10 * of the License.
11 */
12
13 #include <linux/init.h>
14 #include <linux/kernel.h>
15 #include <linux/interrupt.h>
16 #include <linux/scatterlist.h>
17 #include <linux/sfi.h>
18 #include <linux/spi/spi.h>
19 #include <linux/i2c.h>
20 #include <linux/skbuff.h>
21 #include <linux/gpio.h>
22 #include <linux/gpio_keys.h>
23 #include <linux/input.h>
24 #include <linux/platform_device.h>
25 #include <linux/irq.h>
26 #include <linux/export.h>
27 #include <linux/notifier.h>
28 #include <linux/mmc/core.h>
29 #include <linux/mmc/card.h>
30 #include <linux/blkdev.h>
31
32 #include <asm/setup.h>
33 #include <asm/mpspec_def.h>
34 #include <asm/hw_irq.h>
35 #include <asm/apic.h>
36 #include <asm/io_apic.h>
37 #include <asm/intel-mid.h>
38 #include <asm/intel_mid_vrtc.h>
39 #include <asm/io.h>
40 #include <asm/i8259.h>
41 #include <asm/intel_scu_ipc.h>
42 #include <asm/apb_timer.h>
43 #include <asm/reboot.h>
44
45 #define SFI_SIG_OEM0 "OEM0"
46 #define MAX_IPCDEVS 24
47 #define MAX_SCU_SPI 24
48 #define MAX_SCU_I2C 24
49
50 static struct platform_device *ipc_devs[MAX_IPCDEVS];
51 static struct spi_board_info *spi_devs[MAX_SCU_SPI];
52 static struct i2c_board_info *i2c_devs[MAX_SCU_I2C];
53 static struct sfi_gpio_table_entry *gpio_table;
54 static struct sfi_timer_table_entry sfi_mtimer_array[SFI_MTMR_MAX_NUM];
55 static int ipc_next_dev;
56 static int spi_next_dev;
57 static int i2c_next_dev;
58 static int i2c_bus[MAX_SCU_I2C];
59 static int gpio_num_entry;
60 static u32 sfi_mtimer_usage[SFI_MTMR_MAX_NUM];
61 int sfi_mrtc_num;
62 int sfi_mtimer_num;
63
64 struct sfi_rtc_table_entry sfi_mrtc_array[SFI_MRTC_MAX];
65 EXPORT_SYMBOL_GPL(sfi_mrtc_array);
66
67 struct blocking_notifier_head intel_scu_notifier =
68 BLOCKING_NOTIFIER_INIT(intel_scu_notifier);
69 EXPORT_SYMBOL_GPL(intel_scu_notifier);
70
71 #define intel_mid_sfi_get_pdata(dev, priv) \
72 ((dev)->get_platform_data ? (dev)->get_platform_data(priv) : NULL)
73
74 /* parse all the mtimer info to a static mtimer array */
sfi_parse_mtmr(struct sfi_table_header * table)75 int __init sfi_parse_mtmr(struct sfi_table_header *table)
76 {
77 struct sfi_table_simple *sb;
78 struct sfi_timer_table_entry *pentry;
79 struct mpc_intsrc mp_irq;
80 int totallen;
81
82 sb = (struct sfi_table_simple *)table;
83 if (!sfi_mtimer_num) {
84 sfi_mtimer_num = SFI_GET_NUM_ENTRIES(sb,
85 struct sfi_timer_table_entry);
86 pentry = (struct sfi_timer_table_entry *) sb->pentry;
87 totallen = sfi_mtimer_num * sizeof(*pentry);
88 memcpy(sfi_mtimer_array, pentry, totallen);
89 }
90
91 pr_debug("SFI MTIMER info (num = %d):\n", sfi_mtimer_num);
92 pentry = sfi_mtimer_array;
93 for (totallen = 0; totallen < sfi_mtimer_num; totallen++, pentry++) {
94 pr_debug("timer[%d]: paddr = 0x%08x, freq = %dHz, irq = %d\n",
95 totallen, (u32)pentry->phys_addr,
96 pentry->freq_hz, pentry->irq);
97 mp_irq.type = MP_INTSRC;
98 mp_irq.irqtype = mp_INT;
99 /* triggering mode edge bit 2-3, active high polarity bit 0-1 */
100 mp_irq.irqflag = 5;
101 mp_irq.srcbus = MP_BUS_ISA;
102 mp_irq.srcbusirq = pentry->irq; /* IRQ */
103 mp_irq.dstapic = MP_APIC_ALL;
104 mp_irq.dstirq = pentry->irq;
105 mp_save_irq(&mp_irq);
106 mp_map_gsi_to_irq(pentry->irq, IOAPIC_MAP_ALLOC, NULL);
107 }
108
109 return 0;
110 }
111
sfi_get_mtmr(int hint)112 struct sfi_timer_table_entry *sfi_get_mtmr(int hint)
113 {
114 int i;
115 if (hint < sfi_mtimer_num) {
116 if (!sfi_mtimer_usage[hint]) {
117 pr_debug("hint taken for timer %d irq %d\n",
118 hint, sfi_mtimer_array[hint].irq);
119 sfi_mtimer_usage[hint] = 1;
120 return &sfi_mtimer_array[hint];
121 }
122 }
123 /* take the first timer available */
124 for (i = 0; i < sfi_mtimer_num;) {
125 if (!sfi_mtimer_usage[i]) {
126 sfi_mtimer_usage[i] = 1;
127 return &sfi_mtimer_array[i];
128 }
129 i++;
130 }
131 return NULL;
132 }
133
sfi_free_mtmr(struct sfi_timer_table_entry * mtmr)134 void sfi_free_mtmr(struct sfi_timer_table_entry *mtmr)
135 {
136 int i;
137 for (i = 0; i < sfi_mtimer_num;) {
138 if (mtmr->irq == sfi_mtimer_array[i].irq) {
139 sfi_mtimer_usage[i] = 0;
140 return;
141 }
142 i++;
143 }
144 }
145
146 /* parse all the mrtc info to a global mrtc array */
sfi_parse_mrtc(struct sfi_table_header * table)147 int __init sfi_parse_mrtc(struct sfi_table_header *table)
148 {
149 struct sfi_table_simple *sb;
150 struct sfi_rtc_table_entry *pentry;
151 struct mpc_intsrc mp_irq;
152
153 int totallen;
154
155 sb = (struct sfi_table_simple *)table;
156 if (!sfi_mrtc_num) {
157 sfi_mrtc_num = SFI_GET_NUM_ENTRIES(sb,
158 struct sfi_rtc_table_entry);
159 pentry = (struct sfi_rtc_table_entry *)sb->pentry;
160 totallen = sfi_mrtc_num * sizeof(*pentry);
161 memcpy(sfi_mrtc_array, pentry, totallen);
162 }
163
164 pr_debug("SFI RTC info (num = %d):\n", sfi_mrtc_num);
165 pentry = sfi_mrtc_array;
166 for (totallen = 0; totallen < sfi_mrtc_num; totallen++, pentry++) {
167 pr_debug("RTC[%d]: paddr = 0x%08x, irq = %d\n",
168 totallen, (u32)pentry->phys_addr, pentry->irq);
169 mp_irq.type = MP_INTSRC;
170 mp_irq.irqtype = mp_INT;
171 mp_irq.irqflag = 0xf; /* level trigger and active low */
172 mp_irq.srcbus = MP_BUS_ISA;
173 mp_irq.srcbusirq = pentry->irq; /* IRQ */
174 mp_irq.dstapic = MP_APIC_ALL;
175 mp_irq.dstirq = pentry->irq;
176 mp_save_irq(&mp_irq);
177 mp_map_gsi_to_irq(pentry->irq, IOAPIC_MAP_ALLOC, NULL);
178 }
179 return 0;
180 }
181
182
183 /*
184 * Parsing GPIO table first, since the DEVS table will need this table
185 * to map the pin name to the actual pin.
186 */
sfi_parse_gpio(struct sfi_table_header * table)187 static int __init sfi_parse_gpio(struct sfi_table_header *table)
188 {
189 struct sfi_table_simple *sb;
190 struct sfi_gpio_table_entry *pentry;
191 int num, i;
192
193 if (gpio_table)
194 return 0;
195 sb = (struct sfi_table_simple *)table;
196 num = SFI_GET_NUM_ENTRIES(sb, struct sfi_gpio_table_entry);
197 pentry = (struct sfi_gpio_table_entry *)sb->pentry;
198
199 gpio_table = kmemdup(pentry, num * sizeof(*pentry), GFP_KERNEL);
200 if (!gpio_table)
201 return -1;
202 gpio_num_entry = num;
203
204 pr_debug("GPIO pin info:\n");
205 for (i = 0; i < num; i++, pentry++)
206 pr_debug("info[%2d]: controller = %16.16s, pin_name = %16.16s,"
207 " pin = %d\n", i,
208 pentry->controller_name,
209 pentry->pin_name,
210 pentry->pin_no);
211 return 0;
212 }
213
get_gpio_by_name(const char * name)214 int get_gpio_by_name(const char *name)
215 {
216 struct sfi_gpio_table_entry *pentry = gpio_table;
217 int i;
218
219 if (!pentry)
220 return -1;
221 for (i = 0; i < gpio_num_entry; i++, pentry++) {
222 if (!strncmp(name, pentry->pin_name, SFI_NAME_LEN))
223 return pentry->pin_no;
224 }
225 return -EINVAL;
226 }
227
intel_scu_ipc_device_register(struct platform_device * pdev)228 static void __init intel_scu_ipc_device_register(struct platform_device *pdev)
229 {
230 if (ipc_next_dev == MAX_IPCDEVS)
231 pr_err("too many SCU IPC devices");
232 else
233 ipc_devs[ipc_next_dev++] = pdev;
234 }
235
intel_scu_spi_device_register(struct spi_board_info * sdev)236 static void __init intel_scu_spi_device_register(struct spi_board_info *sdev)
237 {
238 struct spi_board_info *new_dev;
239
240 if (spi_next_dev == MAX_SCU_SPI) {
241 pr_err("too many SCU SPI devices");
242 return;
243 }
244
245 new_dev = kzalloc(sizeof(*sdev), GFP_KERNEL);
246 if (!new_dev) {
247 pr_err("failed to alloc mem for delayed spi dev %s\n",
248 sdev->modalias);
249 return;
250 }
251 *new_dev = *sdev;
252
253 spi_devs[spi_next_dev++] = new_dev;
254 }
255
intel_scu_i2c_device_register(int bus,struct i2c_board_info * idev)256 static void __init intel_scu_i2c_device_register(int bus,
257 struct i2c_board_info *idev)
258 {
259 struct i2c_board_info *new_dev;
260
261 if (i2c_next_dev == MAX_SCU_I2C) {
262 pr_err("too many SCU I2C devices");
263 return;
264 }
265
266 new_dev = kzalloc(sizeof(*idev), GFP_KERNEL);
267 if (!new_dev) {
268 pr_err("failed to alloc mem for delayed i2c dev %s\n",
269 idev->type);
270 return;
271 }
272 *new_dev = *idev;
273
274 i2c_bus[i2c_next_dev] = bus;
275 i2c_devs[i2c_next_dev++] = new_dev;
276 }
277
278 /* Called by IPC driver */
intel_scu_devices_create(void)279 void intel_scu_devices_create(void)
280 {
281 int i;
282
283 for (i = 0; i < ipc_next_dev; i++)
284 platform_device_add(ipc_devs[i]);
285
286 for (i = 0; i < spi_next_dev; i++)
287 spi_register_board_info(spi_devs[i], 1);
288
289 for (i = 0; i < i2c_next_dev; i++) {
290 struct i2c_adapter *adapter;
291 struct i2c_client *client;
292
293 adapter = i2c_get_adapter(i2c_bus[i]);
294 if (adapter) {
295 client = i2c_new_device(adapter, i2c_devs[i]);
296 if (!client)
297 pr_err("can't create i2c device %s\n",
298 i2c_devs[i]->type);
299 } else
300 i2c_register_board_info(i2c_bus[i], i2c_devs[i], 1);
301 }
302 intel_scu_notifier_post(SCU_AVAILABLE, NULL);
303 }
304 EXPORT_SYMBOL_GPL(intel_scu_devices_create);
305
306 /* Called by IPC driver */
intel_scu_devices_destroy(void)307 void intel_scu_devices_destroy(void)
308 {
309 int i;
310
311 intel_scu_notifier_post(SCU_DOWN, NULL);
312
313 for (i = 0; i < ipc_next_dev; i++)
314 platform_device_del(ipc_devs[i]);
315 }
316 EXPORT_SYMBOL_GPL(intel_scu_devices_destroy);
317
install_irq_resource(struct platform_device * pdev,int irq)318 static void __init install_irq_resource(struct platform_device *pdev, int irq)
319 {
320 /* Single threaded */
321 static struct resource res __initdata = {
322 .name = "IRQ",
323 .flags = IORESOURCE_IRQ,
324 };
325 res.start = irq;
326 platform_device_add_resources(pdev, &res, 1);
327 }
328
sfi_handle_ipc_dev(struct sfi_device_table_entry * pentry,struct devs_id * dev)329 static void __init sfi_handle_ipc_dev(struct sfi_device_table_entry *pentry,
330 struct devs_id *dev)
331 {
332 struct platform_device *pdev;
333 void *pdata = NULL;
334
335 pr_debug("IPC bus, name = %16.16s, irq = 0x%2x\n",
336 pentry->name, pentry->irq);
337
338 /*
339 * We need to call platform init of IPC devices to fill misc_pdata
340 * structure. It will be used in msic_init for initialization.
341 */
342 pdata = intel_mid_sfi_get_pdata(dev, pentry);
343 if (IS_ERR(pdata))
344 return;
345
346 /*
347 * On Medfield the platform device creation is handled by the MSIC
348 * MFD driver so we don't need to do it here.
349 */
350 if (dev->msic && intel_mid_has_msic())
351 return;
352
353 pdev = platform_device_alloc(pentry->name, 0);
354 if (pdev == NULL) {
355 pr_err("out of memory for SFI platform device '%s'.\n",
356 pentry->name);
357 return;
358 }
359 install_irq_resource(pdev, pentry->irq);
360
361 pdev->dev.platform_data = pdata;
362 if (dev->delay)
363 intel_scu_ipc_device_register(pdev);
364 else
365 platform_device_add(pdev);
366 }
367
sfi_handle_spi_dev(struct sfi_device_table_entry * pentry,struct devs_id * dev)368 static void __init sfi_handle_spi_dev(struct sfi_device_table_entry *pentry,
369 struct devs_id *dev)
370 {
371 struct spi_board_info spi_info;
372 void *pdata = NULL;
373
374 memset(&spi_info, 0, sizeof(spi_info));
375 strncpy(spi_info.modalias, pentry->name, SFI_NAME_LEN);
376 spi_info.irq = ((pentry->irq == (u8)0xff) ? 0 : pentry->irq);
377 spi_info.bus_num = pentry->host_num;
378 spi_info.chip_select = pentry->addr;
379 spi_info.max_speed_hz = pentry->max_freq;
380 pr_debug("SPI bus=%d, name=%16.16s, irq=0x%2x, max_freq=%d, cs=%d\n",
381 spi_info.bus_num,
382 spi_info.modalias,
383 spi_info.irq,
384 spi_info.max_speed_hz,
385 spi_info.chip_select);
386
387 pdata = intel_mid_sfi_get_pdata(dev, &spi_info);
388 if (IS_ERR(pdata))
389 return;
390
391 spi_info.platform_data = pdata;
392 if (dev->delay)
393 intel_scu_spi_device_register(&spi_info);
394 else
395 spi_register_board_info(&spi_info, 1);
396 }
397
sfi_handle_i2c_dev(struct sfi_device_table_entry * pentry,struct devs_id * dev)398 static void __init sfi_handle_i2c_dev(struct sfi_device_table_entry *pentry,
399 struct devs_id *dev)
400 {
401 struct i2c_board_info i2c_info;
402 void *pdata = NULL;
403
404 memset(&i2c_info, 0, sizeof(i2c_info));
405 strncpy(i2c_info.type, pentry->name, SFI_NAME_LEN);
406 i2c_info.irq = ((pentry->irq == (u8)0xff) ? 0 : pentry->irq);
407 i2c_info.addr = pentry->addr;
408 pr_debug("I2C bus = %d, name = %16.16s, irq = 0x%2x, addr = 0x%x\n",
409 pentry->host_num,
410 i2c_info.type,
411 i2c_info.irq,
412 i2c_info.addr);
413 pdata = intel_mid_sfi_get_pdata(dev, &i2c_info);
414 i2c_info.platform_data = pdata;
415 if (IS_ERR(pdata))
416 return;
417
418 if (dev->delay)
419 intel_scu_i2c_device_register(pentry->host_num, &i2c_info);
420 else
421 i2c_register_board_info(pentry->host_num, &i2c_info, 1);
422 }
423
sfi_handle_sd_dev(struct sfi_device_table_entry * pentry,struct devs_id * dev)424 static void __init sfi_handle_sd_dev(struct sfi_device_table_entry *pentry,
425 struct devs_id *dev)
426 {
427 struct mid_sd_board_info sd_info;
428 void *pdata;
429
430 memset(&sd_info, 0, sizeof(sd_info));
431 strncpy(sd_info.name, pentry->name, SFI_NAME_LEN);
432 sd_info.bus_num = pentry->host_num;
433 sd_info.max_clk = pentry->max_freq;
434 sd_info.addr = pentry->addr;
435 pr_debug("SD bus = %d, name = %16.16s, max_clk = %d, addr = 0x%x\n",
436 sd_info.bus_num,
437 sd_info.name,
438 sd_info.max_clk,
439 sd_info.addr);
440 pdata = intel_mid_sfi_get_pdata(dev, &sd_info);
441 if (IS_ERR(pdata))
442 return;
443
444 /* Nothing we can do with this for now */
445 sd_info.platform_data = pdata;
446
447 pr_debug("Successfully registered %16.16s", sd_info.name);
448 }
449
450 extern struct devs_id *const __x86_intel_mid_dev_start[],
451 *const __x86_intel_mid_dev_end[];
452
get_device_id(u8 type,char * name)453 static struct devs_id __init *get_device_id(u8 type, char *name)
454 {
455 struct devs_id *const *dev_table;
456
457 for (dev_table = __x86_intel_mid_dev_start;
458 dev_table < __x86_intel_mid_dev_end; dev_table++) {
459 struct devs_id *dev = *dev_table;
460 if (dev->type == type &&
461 !strncmp(dev->name, name, SFI_NAME_LEN)) {
462 return dev;
463 }
464 }
465
466 return NULL;
467 }
468
sfi_parse_devs(struct sfi_table_header * table)469 static int __init sfi_parse_devs(struct sfi_table_header *table)
470 {
471 struct sfi_table_simple *sb;
472 struct sfi_device_table_entry *pentry;
473 struct devs_id *dev = NULL;
474 int num, i, ret;
475 int polarity;
476 struct irq_alloc_info info;
477
478 sb = (struct sfi_table_simple *)table;
479 num = SFI_GET_NUM_ENTRIES(sb, struct sfi_device_table_entry);
480 pentry = (struct sfi_device_table_entry *)sb->pentry;
481
482 for (i = 0; i < num; i++, pentry++) {
483 int irq = pentry->irq;
484
485 if (irq != (u8)0xff) { /* native RTE case */
486 /* these SPI2 devices are not exposed to system as PCI
487 * devices, but they have separate RTE entry in IOAPIC
488 * so we have to enable them one by one here
489 */
490 if (intel_mid_identify_cpu() ==
491 INTEL_MID_CPU_CHIP_TANGIER) {
492 if (!strncmp(pentry->name, "r69001-ts-i2c", 13))
493 /* active low */
494 polarity = 1;
495 else if (!strncmp(pentry->name,
496 "synaptics_3202", 14))
497 /* active low */
498 polarity = 1;
499 else if (irq == 41)
500 /* fast_int_1 */
501 polarity = 1;
502 else
503 /* active high */
504 polarity = 0;
505 } else {
506 /* PNW and CLV go with active low */
507 polarity = 1;
508 }
509
510 ioapic_set_alloc_attr(&info, NUMA_NO_NODE, 1, polarity);
511 ret = mp_map_gsi_to_irq(irq, IOAPIC_MAP_ALLOC, &info);
512 WARN_ON(ret < 0);
513 }
514
515 dev = get_device_id(pentry->type, pentry->name);
516
517 if (!dev)
518 continue;
519
520 switch (pentry->type) {
521 case SFI_DEV_TYPE_IPC:
522 sfi_handle_ipc_dev(pentry, dev);
523 break;
524 case SFI_DEV_TYPE_SPI:
525 sfi_handle_spi_dev(pentry, dev);
526 break;
527 case SFI_DEV_TYPE_I2C:
528 sfi_handle_i2c_dev(pentry, dev);
529 break;
530 case SFI_DEV_TYPE_SD:
531 sfi_handle_sd_dev(pentry, dev);
532 break;
533 case SFI_DEV_TYPE_UART:
534 case SFI_DEV_TYPE_HSI:
535 default:
536 break;
537 }
538 }
539 return 0;
540 }
541
intel_mid_platform_init(void)542 static int __init intel_mid_platform_init(void)
543 {
544 sfi_table_parse(SFI_SIG_GPIO, NULL, NULL, sfi_parse_gpio);
545 sfi_table_parse(SFI_SIG_DEVS, NULL, NULL, sfi_parse_devs);
546 return 0;
547 }
548 arch_initcall(intel_mid_platform_init);
549