• Home
  • Line#
  • Scopes#
  • Navigate#
  • Raw
  • Download
1 /*
2  * Suspend support specific for i386/x86-64.
3  *
4  * Distribute under GPLv2
5  *
6  * Copyright (c) 2007 Rafael J. Wysocki <rjw@sisk.pl>
7  * Copyright (c) 2002 Pavel Machek <pavel@ucw.cz>
8  * Copyright (c) 2001 Patrick Mochel <mochel@osdl.org>
9  */
10 
11 #include <linux/suspend.h>
12 #include <linux/export.h>
13 #include <linux/smp.h>
14 #include <linux/perf_event.h>
15 #include <linux/tboot.h>
16 #include <linux/dmi.h>
17 
18 #include <asm/pgtable.h>
19 #include <asm/proto.h>
20 #include <asm/mtrr.h>
21 #include <asm/page.h>
22 #include <asm/mce.h>
23 #include <asm/suspend.h>
24 #include <asm/fpu/internal.h>
25 #include <asm/debugreg.h>
26 #include <asm/cpu.h>
27 #include <asm/mmu_context.h>
28 #include <asm/cpu_device_id.h>
29 
30 #ifdef CONFIG_X86_32
31 __visible unsigned long saved_context_ebx;
32 __visible unsigned long saved_context_esp, saved_context_ebp;
33 __visible unsigned long saved_context_esi, saved_context_edi;
34 __visible unsigned long saved_context_eflags;
35 #endif
36 struct saved_context saved_context;
37 
msr_save_context(struct saved_context * ctxt)38 static void msr_save_context(struct saved_context *ctxt)
39 {
40 	struct saved_msr *msr = ctxt->saved_msrs.array;
41 	struct saved_msr *end = msr + ctxt->saved_msrs.num;
42 
43 	while (msr < end) {
44 		msr->valid = !rdmsrl_safe(msr->info.msr_no, &msr->info.reg.q);
45 		msr++;
46 	}
47 }
48 
msr_restore_context(struct saved_context * ctxt)49 static void msr_restore_context(struct saved_context *ctxt)
50 {
51 	struct saved_msr *msr = ctxt->saved_msrs.array;
52 	struct saved_msr *end = msr + ctxt->saved_msrs.num;
53 
54 	while (msr < end) {
55 		if (msr->valid)
56 			wrmsrl(msr->info.msr_no, msr->info.reg.q);
57 		msr++;
58 	}
59 }
60 
61 /**
62  *	__save_processor_state - save CPU registers before creating a
63  *		hibernation image and before restoring the memory state from it
64  *	@ctxt - structure to store the registers contents in
65  *
66  *	NOTE: If there is a CPU register the modification of which by the
67  *	boot kernel (ie. the kernel used for loading the hibernation image)
68  *	might affect the operations of the restored target kernel (ie. the one
69  *	saved in the hibernation image), then its contents must be saved by this
70  *	function.  In other words, if kernel A is hibernated and different
71  *	kernel B is used for loading the hibernation image into memory, the
72  *	kernel A's __save_processor_state() function must save all registers
73  *	needed by kernel A, so that it can operate correctly after the resume
74  *	regardless of what kernel B does in the meantime.
75  */
__save_processor_state(struct saved_context * ctxt)76 static void __save_processor_state(struct saved_context *ctxt)
77 {
78 #ifdef CONFIG_X86_32
79 	mtrr_save_fixed_ranges(NULL);
80 #endif
81 	kernel_fpu_begin();
82 
83 	/*
84 	 * descriptor tables
85 	 */
86 	store_idt(&ctxt->idt);
87 
88 	/*
89 	 * We save it here, but restore it only in the hibernate case.
90 	 * For ACPI S3 resume, this is loaded via 'early_gdt_desc' in 64-bit
91 	 * mode in "secondary_startup_64". In 32-bit mode it is done via
92 	 * 'pmode_gdt' in wakeup_start.
93 	 */
94 	ctxt->gdt_desc.size = GDT_SIZE - 1;
95 	ctxt->gdt_desc.address = (unsigned long)get_cpu_gdt_rw(smp_processor_id());
96 
97 	store_tr(ctxt->tr);
98 
99 	/* XMM0..XMM15 should be handled by kernel_fpu_begin(). */
100 	/*
101 	 * segment registers
102 	 */
103 #ifdef CONFIG_X86_32_LAZY_GS
104 	savesegment(gs, ctxt->gs);
105 #endif
106 #ifdef CONFIG_X86_64
107 	savesegment(gs, ctxt->gs);
108 	savesegment(fs, ctxt->fs);
109 	savesegment(ds, ctxt->ds);
110 	savesegment(es, ctxt->es);
111 
112 	rdmsrl(MSR_FS_BASE, ctxt->fs_base);
113 	rdmsrl(MSR_GS_BASE, ctxt->kernelmode_gs_base);
114 	rdmsrl(MSR_KERNEL_GS_BASE, ctxt->usermode_gs_base);
115 	mtrr_save_fixed_ranges(NULL);
116 
117 	rdmsrl(MSR_EFER, ctxt->efer);
118 #endif
119 
120 	/*
121 	 * control registers
122 	 */
123 	ctxt->cr0 = read_cr0();
124 	ctxt->cr2 = read_cr2();
125 	ctxt->cr3 = __read_cr3();
126 	ctxt->cr4 = __read_cr4();
127 #ifdef CONFIG_X86_64
128 	ctxt->cr8 = read_cr8();
129 #endif
130 	ctxt->misc_enable_saved = !rdmsrl_safe(MSR_IA32_MISC_ENABLE,
131 					       &ctxt->misc_enable);
132 	msr_save_context(ctxt);
133 }
134 
135 /* Needed by apm.c */
save_processor_state(void)136 void save_processor_state(void)
137 {
138 	__save_processor_state(&saved_context);
139 	x86_platform.save_sched_clock_state();
140 }
141 #ifdef CONFIG_X86_32
142 EXPORT_SYMBOL(save_processor_state);
143 #endif
144 
do_fpu_end(void)145 static void do_fpu_end(void)
146 {
147 	/*
148 	 * Restore FPU regs if necessary.
149 	 */
150 	kernel_fpu_end();
151 }
152 
fix_processor_context(void)153 static void fix_processor_context(void)
154 {
155 	int cpu = smp_processor_id();
156 #ifdef CONFIG_X86_64
157 	struct desc_struct *desc = get_cpu_gdt_rw(cpu);
158 	tss_desc tss;
159 #endif
160 
161 	/*
162 	 * We need to reload TR, which requires that we change the
163 	 * GDT entry to indicate "available" first.
164 	 *
165 	 * XXX: This could probably all be replaced by a call to
166 	 * force_reload_TR().
167 	 */
168 	set_tss_desc(cpu, &get_cpu_entry_area(cpu)->tss.x86_tss);
169 
170 #ifdef CONFIG_X86_64
171 	memcpy(&tss, &desc[GDT_ENTRY_TSS], sizeof(tss_desc));
172 	tss.type = 0x9; /* The available 64-bit TSS (see AMD vol 2, pg 91 */
173 	write_gdt_entry(desc, GDT_ENTRY_TSS, &tss, DESC_TSS);
174 
175 	syscall_init();				/* This sets MSR_*STAR and related */
176 #else
177 	if (boot_cpu_has(X86_FEATURE_SEP))
178 		enable_sep_cpu();
179 #endif
180 	load_TR_desc();				/* This does ltr */
181 	load_mm_ldt(current->active_mm);	/* This does lldt */
182 	initialize_tlbstate_and_flush();
183 
184 	fpu__resume_cpu();
185 
186 	/* The processor is back on the direct GDT, load back the fixmap */
187 	load_fixmap_gdt(cpu);
188 }
189 
190 /**
191  * __restore_processor_state - restore the contents of CPU registers saved
192  *                             by __save_processor_state()
193  * @ctxt - structure to load the registers contents from
194  *
195  * The asm code that gets us here will have restored a usable GDT, although
196  * it will be pointing to the wrong alias.
197  */
__restore_processor_state(struct saved_context * ctxt)198 static void notrace __restore_processor_state(struct saved_context *ctxt)
199 {
200 	if (ctxt->misc_enable_saved)
201 		wrmsrl(MSR_IA32_MISC_ENABLE, ctxt->misc_enable);
202 	/*
203 	 * control registers
204 	 */
205 	/* cr4 was introduced in the Pentium CPU */
206 #ifdef CONFIG_X86_32
207 	if (ctxt->cr4)
208 		__write_cr4(ctxt->cr4);
209 #else
210 /* CONFIG X86_64 */
211 	wrmsrl(MSR_EFER, ctxt->efer);
212 	write_cr8(ctxt->cr8);
213 	__write_cr4(ctxt->cr4);
214 #endif
215 	write_cr3(ctxt->cr3);
216 	write_cr2(ctxt->cr2);
217 	write_cr0(ctxt->cr0);
218 
219 	/* Restore the IDT. */
220 	load_idt(&ctxt->idt);
221 
222 	/*
223 	 * Just in case the asm code got us here with the SS, DS, or ES
224 	 * out of sync with the GDT, update them.
225 	 */
226 	loadsegment(ss, __KERNEL_DS);
227 	loadsegment(ds, __USER_DS);
228 	loadsegment(es, __USER_DS);
229 
230 	/*
231 	 * Restore percpu access.  Percpu access can happen in exception
232 	 * handlers or in complicated helpers like load_gs_index().
233 	 */
234 #ifdef CONFIG_X86_64
235 	wrmsrl(MSR_GS_BASE, ctxt->kernelmode_gs_base);
236 #else
237 	loadsegment(fs, __KERNEL_PERCPU);
238 	loadsegment(gs, __KERNEL_STACK_CANARY);
239 #endif
240 
241 	/* Restore the TSS, RO GDT, LDT, and usermode-relevant MSRs. */
242 	fix_processor_context();
243 
244 	/*
245 	 * Now that we have descriptor tables fully restored and working
246 	 * exception handling, restore the usermode segments.
247 	 */
248 #ifdef CONFIG_X86_64
249 	loadsegment(ds, ctxt->es);
250 	loadsegment(es, ctxt->es);
251 	loadsegment(fs, ctxt->fs);
252 	load_gs_index(ctxt->gs);
253 
254 	/*
255 	 * Restore FSBASE and GSBASE after restoring the selectors, since
256 	 * restoring the selectors clobbers the bases.  Keep in mind
257 	 * that MSR_KERNEL_GS_BASE is horribly misnamed.
258 	 */
259 	wrmsrl(MSR_FS_BASE, ctxt->fs_base);
260 	wrmsrl(MSR_KERNEL_GS_BASE, ctxt->usermode_gs_base);
261 #elif defined(CONFIG_X86_32_LAZY_GS)
262 	loadsegment(gs, ctxt->gs);
263 #endif
264 
265 	do_fpu_end();
266 	tsc_verify_tsc_adjust(true);
267 	x86_platform.restore_sched_clock_state();
268 	mtrr_bp_restore();
269 	perf_restore_debug_store();
270 	msr_restore_context(ctxt);
271 }
272 
273 /* Needed by apm.c */
restore_processor_state(void)274 void notrace restore_processor_state(void)
275 {
276 	__restore_processor_state(&saved_context);
277 }
278 #ifdef CONFIG_X86_32
279 EXPORT_SYMBOL(restore_processor_state);
280 #endif
281 
282 #if defined(CONFIG_HIBERNATION) && defined(CONFIG_HOTPLUG_CPU)
resume_play_dead(void)283 static void resume_play_dead(void)
284 {
285 	play_dead_common();
286 	tboot_shutdown(TB_SHUTDOWN_WFS);
287 	hlt_play_dead();
288 }
289 
hibernate_resume_nonboot_cpu_disable(void)290 int hibernate_resume_nonboot_cpu_disable(void)
291 {
292 	void (*play_dead)(void) = smp_ops.play_dead;
293 	int ret;
294 
295 	/*
296 	 * Ensure that MONITOR/MWAIT will not be used in the "play dead" loop
297 	 * during hibernate image restoration, because it is likely that the
298 	 * monitored address will be actually written to at that time and then
299 	 * the "dead" CPU will attempt to execute instructions again, but the
300 	 * address in its instruction pointer may not be possible to resolve
301 	 * any more at that point (the page tables used by it previously may
302 	 * have been overwritten by hibernate image data).
303 	 *
304 	 * First, make sure that we wake up all the potentially disabled SMT
305 	 * threads which have been initially brought up and then put into
306 	 * mwait/cpuidle sleep.
307 	 * Those will be put to proper (not interfering with hibernation
308 	 * resume) sleep afterwards, and the resumed kernel will decide itself
309 	 * what to do with them.
310 	 */
311 	ret = cpuhp_smt_enable();
312 	if (ret)
313 		return ret;
314 	smp_ops.play_dead = resume_play_dead;
315 	ret = disable_nonboot_cpus();
316 	smp_ops.play_dead = play_dead;
317 	return ret;
318 }
319 #endif
320 
321 /*
322  * When bsp_check() is called in hibernate and suspend, cpu hotplug
323  * is disabled already. So it's unnessary to handle race condition between
324  * cpumask query and cpu hotplug.
325  */
bsp_check(void)326 static int bsp_check(void)
327 {
328 	if (cpumask_first(cpu_online_mask) != 0) {
329 		pr_warn("CPU0 is offline.\n");
330 		return -ENODEV;
331 	}
332 
333 	return 0;
334 }
335 
bsp_pm_callback(struct notifier_block * nb,unsigned long action,void * ptr)336 static int bsp_pm_callback(struct notifier_block *nb, unsigned long action,
337 			   void *ptr)
338 {
339 	int ret = 0;
340 
341 	switch (action) {
342 	case PM_SUSPEND_PREPARE:
343 	case PM_HIBERNATION_PREPARE:
344 		ret = bsp_check();
345 		break;
346 #ifdef CONFIG_DEBUG_HOTPLUG_CPU0
347 	case PM_RESTORE_PREPARE:
348 		/*
349 		 * When system resumes from hibernation, online CPU0 because
350 		 * 1. it's required for resume and
351 		 * 2. the CPU was online before hibernation
352 		 */
353 		if (!cpu_online(0))
354 			_debug_hotplug_cpu(0, 1);
355 		break;
356 	case PM_POST_RESTORE:
357 		/*
358 		 * When a resume really happens, this code won't be called.
359 		 *
360 		 * This code is called only when user space hibernation software
361 		 * prepares for snapshot device during boot time. So we just
362 		 * call _debug_hotplug_cpu() to restore to CPU0's state prior to
363 		 * preparing the snapshot device.
364 		 *
365 		 * This works for normal boot case in our CPU0 hotplug debug
366 		 * mode, i.e. CPU0 is offline and user mode hibernation
367 		 * software initializes during boot time.
368 		 *
369 		 * If CPU0 is online and user application accesses snapshot
370 		 * device after boot time, this will offline CPU0 and user may
371 		 * see different CPU0 state before and after accessing
372 		 * the snapshot device. But hopefully this is not a case when
373 		 * user debugging CPU0 hotplug. Even if users hit this case,
374 		 * they can easily online CPU0 back.
375 		 *
376 		 * To simplify this debug code, we only consider normal boot
377 		 * case. Otherwise we need to remember CPU0's state and restore
378 		 * to that state and resolve racy conditions etc.
379 		 */
380 		_debug_hotplug_cpu(0, 0);
381 		break;
382 #endif
383 	default:
384 		break;
385 	}
386 	return notifier_from_errno(ret);
387 }
388 
bsp_pm_check_init(void)389 static int __init bsp_pm_check_init(void)
390 {
391 	/*
392 	 * Set this bsp_pm_callback as lower priority than
393 	 * cpu_hotplug_pm_callback. So cpu_hotplug_pm_callback will be called
394 	 * earlier to disable cpu hotplug before bsp online check.
395 	 */
396 	pm_notifier(bsp_pm_callback, -INT_MAX);
397 	return 0;
398 }
399 
400 core_initcall(bsp_pm_check_init);
401 
msr_build_context(const u32 * msr_id,const int num)402 static int msr_build_context(const u32 *msr_id, const int num)
403 {
404 	struct saved_msrs *saved_msrs = &saved_context.saved_msrs;
405 	struct saved_msr *msr_array;
406 	int total_num;
407 	int i, j;
408 
409 	total_num = saved_msrs->num + num;
410 
411 	msr_array = kmalloc_array(total_num, sizeof(struct saved_msr), GFP_KERNEL);
412 	if (!msr_array) {
413 		pr_err("x86/pm: Can not allocate memory to save/restore MSRs during suspend.\n");
414 		return -ENOMEM;
415 	}
416 
417 	if (saved_msrs->array) {
418 		/*
419 		 * Multiple callbacks can invoke this function, so copy any
420 		 * MSR save requests from previous invocations.
421 		 */
422 		memcpy(msr_array, saved_msrs->array,
423 		       sizeof(struct saved_msr) * saved_msrs->num);
424 
425 		kfree(saved_msrs->array);
426 	}
427 
428 	for (i = saved_msrs->num, j = 0; i < total_num; i++, j++) {
429 		msr_array[i].info.msr_no	= msr_id[j];
430 		msr_array[i].valid		= false;
431 		msr_array[i].info.reg.q		= 0;
432 	}
433 	saved_msrs->num   = total_num;
434 	saved_msrs->array = msr_array;
435 
436 	return 0;
437 }
438 
439 /*
440  * The following sections are a quirk framework for problematic BIOSen:
441  * Sometimes MSRs are modified by the BIOSen after suspended to
442  * RAM, this might cause unexpected behavior after wakeup.
443  * Thus we save/restore these specified MSRs across suspend/resume
444  * in order to work around it.
445  *
446  * For any further problematic BIOSen/platforms,
447  * please add your own function similar to msr_initialize_bdw.
448  */
msr_initialize_bdw(const struct dmi_system_id * d)449 static int msr_initialize_bdw(const struct dmi_system_id *d)
450 {
451 	/* Add any extra MSR ids into this array. */
452 	u32 bdw_msr_id[] = { MSR_IA32_THERM_CONTROL };
453 
454 	pr_info("x86/pm: %s detected, MSR saving is needed during suspending.\n", d->ident);
455 	return msr_build_context(bdw_msr_id, ARRAY_SIZE(bdw_msr_id));
456 }
457 
458 static const struct dmi_system_id msr_save_dmi_table[] = {
459 	{
460 	 .callback = msr_initialize_bdw,
461 	 .ident = "BROADWELL BDX_EP",
462 	 .matches = {
463 		DMI_MATCH(DMI_PRODUCT_NAME, "GRANTLEY"),
464 		DMI_MATCH(DMI_PRODUCT_VERSION, "E63448-400"),
465 		},
466 	},
467 	{}
468 };
469 
msr_save_cpuid_features(const struct x86_cpu_id * c)470 static int msr_save_cpuid_features(const struct x86_cpu_id *c)
471 {
472 	u32 cpuid_msr_id[] = {
473 		MSR_AMD64_CPUID_FN_1,
474 	};
475 
476 	pr_info("x86/pm: family %#hx cpu detected, MSR saving is needed during suspending.\n",
477 		c->family);
478 
479 	return msr_build_context(cpuid_msr_id, ARRAY_SIZE(cpuid_msr_id));
480 }
481 
482 static const struct x86_cpu_id msr_save_cpu_table[] = {
483 	{
484 		.vendor = X86_VENDOR_AMD,
485 		.family = 0x15,
486 		.model = X86_MODEL_ANY,
487 		.feature = X86_FEATURE_ANY,
488 		.driver_data = (kernel_ulong_t)msr_save_cpuid_features,
489 	},
490 	{
491 		.vendor = X86_VENDOR_AMD,
492 		.family = 0x16,
493 		.model = X86_MODEL_ANY,
494 		.feature = X86_FEATURE_ANY,
495 		.driver_data = (kernel_ulong_t)msr_save_cpuid_features,
496 	},
497 	{}
498 };
499 
500 typedef int (*pm_cpu_match_t)(const struct x86_cpu_id *);
pm_cpu_check(const struct x86_cpu_id * c)501 static int pm_cpu_check(const struct x86_cpu_id *c)
502 {
503 	const struct x86_cpu_id *m;
504 	int ret = 0;
505 
506 	m = x86_match_cpu(msr_save_cpu_table);
507 	if (m) {
508 		pm_cpu_match_t fn;
509 
510 		fn = (pm_cpu_match_t)m->driver_data;
511 		ret = fn(m);
512 	}
513 
514 	return ret;
515 }
516 
pm_check_save_msr(void)517 static int pm_check_save_msr(void)
518 {
519 	dmi_check_system(msr_save_dmi_table);
520 	pm_cpu_check(msr_save_cpu_table);
521 
522 	return 0;
523 }
524 
525 device_initcall(pm_check_save_msr);
526