1 /*
2 * Copyright (C) 2005, 2006 IBM Corporation
3 * Copyright (C) 2014, 2015 Intel Corporation
4 *
5 * Authors:
6 * Leendert van Doorn <leendert@watson.ibm.com>
7 * Kylene Hall <kjhall@us.ibm.com>
8 *
9 * Maintained by: <tpmdd-devel@lists.sourceforge.net>
10 *
11 * Device driver for TCG/TCPA TPM (trusted platform module).
12 * Specifications at www.trustedcomputinggroup.org
13 *
14 * This device driver implements the TPM interface as defined in
15 * the TCG TPM Interface Spec version 1.2, revision 1.0.
16 *
17 * This program is free software; you can redistribute it and/or
18 * modify it under the terms of the GNU General Public License as
19 * published by the Free Software Foundation, version 2 of the
20 * License.
21 */
22 #include <linux/init.h>
23 #include <linux/module.h>
24 #include <linux/moduleparam.h>
25 #include <linux/pnp.h>
26 #include <linux/slab.h>
27 #include <linux/interrupt.h>
28 #include <linux/wait.h>
29 #include <linux/acpi.h>
30 #include <linux/freezer.h>
31 #include "tpm.h"
32 #include "tpm_tis_core.h"
33
34 static void tpm_tis_clkrun_enable(struct tpm_chip *chip, bool value);
35
36 /* Before we attempt to access the TPM we must see that the valid bit is set.
37 * The specification says that this bit is 0 at reset and remains 0 until the
38 * 'TPM has gone through its self test and initialization and has established
39 * correct values in the other bits.'
40 */
wait_startup(struct tpm_chip * chip,int l)41 static int wait_startup(struct tpm_chip *chip, int l)
42 {
43 struct tpm_tis_data *priv = dev_get_drvdata(&chip->dev);
44 unsigned long stop = jiffies + chip->timeout_a;
45
46 do {
47 int rc;
48 u8 access;
49
50 rc = tpm_tis_read8(priv, TPM_ACCESS(l), &access);
51 if (rc < 0)
52 return rc;
53
54 if (access & TPM_ACCESS_VALID)
55 return 0;
56 tpm_msleep(TPM_TIMEOUT);
57 } while (time_before(jiffies, stop));
58 return -1;
59 }
60
check_locality(struct tpm_chip * chip,int l)61 static bool check_locality(struct tpm_chip *chip, int l)
62 {
63 struct tpm_tis_data *priv = dev_get_drvdata(&chip->dev);
64 int rc;
65 u8 access;
66
67 rc = tpm_tis_read8(priv, TPM_ACCESS(l), &access);
68 if (rc < 0)
69 return false;
70
71 if ((access & (TPM_ACCESS_ACTIVE_LOCALITY | TPM_ACCESS_VALID)) ==
72 (TPM_ACCESS_ACTIVE_LOCALITY | TPM_ACCESS_VALID)) {
73 priv->locality = l;
74 return true;
75 }
76
77 return false;
78 }
79
release_locality(struct tpm_chip * chip,int l)80 static int release_locality(struct tpm_chip *chip, int l)
81 {
82 struct tpm_tis_data *priv = dev_get_drvdata(&chip->dev);
83
84 tpm_tis_write8(priv, TPM_ACCESS(l), TPM_ACCESS_ACTIVE_LOCALITY);
85
86 return 0;
87 }
88
request_locality(struct tpm_chip * chip,int l)89 static int request_locality(struct tpm_chip *chip, int l)
90 {
91 struct tpm_tis_data *priv = dev_get_drvdata(&chip->dev);
92 unsigned long stop, timeout;
93 long rc;
94
95 if (check_locality(chip, l))
96 return l;
97
98 rc = tpm_tis_write8(priv, TPM_ACCESS(l), TPM_ACCESS_REQUEST_USE);
99 if (rc < 0)
100 return rc;
101
102 stop = jiffies + chip->timeout_a;
103
104 if (chip->flags & TPM_CHIP_FLAG_IRQ) {
105 again:
106 timeout = stop - jiffies;
107 if ((long)timeout <= 0)
108 return -1;
109 rc = wait_event_interruptible_timeout(priv->int_queue,
110 (check_locality
111 (chip, l)),
112 timeout);
113 if (rc > 0)
114 return l;
115 if (rc == -ERESTARTSYS && freezing(current)) {
116 clear_thread_flag(TIF_SIGPENDING);
117 goto again;
118 }
119 } else {
120 /* wait for burstcount */
121 do {
122 if (check_locality(chip, l))
123 return l;
124 tpm_msleep(TPM_TIMEOUT);
125 } while (time_before(jiffies, stop));
126 }
127 return -1;
128 }
129
tpm_tis_status(struct tpm_chip * chip)130 static u8 tpm_tis_status(struct tpm_chip *chip)
131 {
132 struct tpm_tis_data *priv = dev_get_drvdata(&chip->dev);
133 int rc;
134 u8 status;
135
136 rc = tpm_tis_read8(priv, TPM_STS(priv->locality), &status);
137 if (rc < 0)
138 return 0;
139
140 return status;
141 }
142
tpm_tis_ready(struct tpm_chip * chip)143 static void tpm_tis_ready(struct tpm_chip *chip)
144 {
145 struct tpm_tis_data *priv = dev_get_drvdata(&chip->dev);
146
147 /* this causes the current command to be aborted */
148 tpm_tis_write8(priv, TPM_STS(priv->locality), TPM_STS_COMMAND_READY);
149 }
150
get_burstcount(struct tpm_chip * chip)151 static int get_burstcount(struct tpm_chip *chip)
152 {
153 struct tpm_tis_data *priv = dev_get_drvdata(&chip->dev);
154 unsigned long stop;
155 int burstcnt, rc;
156 u32 value;
157
158 /* wait for burstcount */
159 if (chip->flags & TPM_CHIP_FLAG_TPM2)
160 stop = jiffies + chip->timeout_a;
161 else
162 stop = jiffies + chip->timeout_d;
163 do {
164 rc = tpm_tis_read32(priv, TPM_STS(priv->locality), &value);
165 if (rc < 0)
166 return rc;
167
168 burstcnt = (value >> 8) & 0xFFFF;
169 if (burstcnt)
170 return burstcnt;
171 tpm_msleep(TPM_TIMEOUT);
172 } while (time_before(jiffies, stop));
173 return -EBUSY;
174 }
175
recv_data(struct tpm_chip * chip,u8 * buf,size_t count)176 static int recv_data(struct tpm_chip *chip, u8 *buf, size_t count)
177 {
178 struct tpm_tis_data *priv = dev_get_drvdata(&chip->dev);
179 int size = 0, burstcnt, rc;
180
181 while (size < count) {
182 rc = wait_for_tpm_stat(chip,
183 TPM_STS_DATA_AVAIL | TPM_STS_VALID,
184 chip->timeout_c,
185 &priv->read_queue, true);
186 if (rc < 0)
187 return rc;
188 burstcnt = get_burstcount(chip);
189 if (burstcnt < 0) {
190 dev_err(&chip->dev, "Unable to read burstcount\n");
191 return burstcnt;
192 }
193 burstcnt = min_t(int, burstcnt, count - size);
194
195 rc = tpm_tis_read_bytes(priv, TPM_DATA_FIFO(priv->locality),
196 burstcnt, buf + size);
197 if (rc < 0)
198 return rc;
199
200 size += burstcnt;
201 }
202 return size;
203 }
204
tpm_tis_recv(struct tpm_chip * chip,u8 * buf,size_t count)205 static int tpm_tis_recv(struct tpm_chip *chip, u8 *buf, size_t count)
206 {
207 struct tpm_tis_data *priv = dev_get_drvdata(&chip->dev);
208 int size = 0;
209 int status;
210 u32 expected;
211
212 if (count < TPM_HEADER_SIZE) {
213 size = -EIO;
214 goto out;
215 }
216
217 size = recv_data(chip, buf, TPM_HEADER_SIZE);
218 /* read first 10 bytes, including tag, paramsize, and result */
219 if (size < TPM_HEADER_SIZE) {
220 dev_err(&chip->dev, "Unable to read header\n");
221 goto out;
222 }
223
224 expected = be32_to_cpu(*(__be32 *) (buf + 2));
225 if (expected > count || expected < TPM_HEADER_SIZE) {
226 size = -EIO;
227 goto out;
228 }
229
230 size += recv_data(chip, &buf[TPM_HEADER_SIZE],
231 expected - TPM_HEADER_SIZE);
232 if (size < expected) {
233 dev_err(&chip->dev, "Unable to read remainder of result\n");
234 size = -ETIME;
235 goto out;
236 }
237
238 if (wait_for_tpm_stat(chip, TPM_STS_VALID, chip->timeout_c,
239 &priv->int_queue, false) < 0) {
240 size = -ETIME;
241 goto out;
242 }
243 status = tpm_tis_status(chip);
244 if (status & TPM_STS_DATA_AVAIL) { /* retry? */
245 dev_err(&chip->dev, "Error left over data\n");
246 size = -EIO;
247 goto out;
248 }
249
250 out:
251 tpm_tis_ready(chip);
252 return size;
253 }
254
255 /*
256 * If interrupts are used (signaled by an irq set in the vendor structure)
257 * tpm.c can skip polling for the data to be available as the interrupt is
258 * waited for here
259 */
tpm_tis_send_data(struct tpm_chip * chip,const u8 * buf,size_t len)260 static int tpm_tis_send_data(struct tpm_chip *chip, const u8 *buf, size_t len)
261 {
262 struct tpm_tis_data *priv = dev_get_drvdata(&chip->dev);
263 int rc, status, burstcnt;
264 size_t count = 0;
265 bool itpm = priv->flags & TPM_TIS_ITPM_WORKAROUND;
266
267 status = tpm_tis_status(chip);
268 if ((status & TPM_STS_COMMAND_READY) == 0) {
269 tpm_tis_ready(chip);
270 if (wait_for_tpm_stat
271 (chip, TPM_STS_COMMAND_READY, chip->timeout_b,
272 &priv->int_queue, false) < 0) {
273 rc = -ETIME;
274 goto out_err;
275 }
276 }
277
278 while (count < len - 1) {
279 burstcnt = get_burstcount(chip);
280 if (burstcnt < 0) {
281 dev_err(&chip->dev, "Unable to read burstcount\n");
282 rc = burstcnt;
283 goto out_err;
284 }
285 burstcnt = min_t(int, burstcnt, len - count - 1);
286 rc = tpm_tis_write_bytes(priv, TPM_DATA_FIFO(priv->locality),
287 burstcnt, buf + count);
288 if (rc < 0)
289 goto out_err;
290
291 count += burstcnt;
292
293 if (wait_for_tpm_stat(chip, TPM_STS_VALID, chip->timeout_c,
294 &priv->int_queue, false) < 0) {
295 rc = -ETIME;
296 goto out_err;
297 }
298 status = tpm_tis_status(chip);
299 if (!itpm && (status & TPM_STS_DATA_EXPECT) == 0) {
300 rc = -EIO;
301 goto out_err;
302 }
303 }
304
305 /* write last byte */
306 rc = tpm_tis_write8(priv, TPM_DATA_FIFO(priv->locality), buf[count]);
307 if (rc < 0)
308 goto out_err;
309
310 if (wait_for_tpm_stat(chip, TPM_STS_VALID, chip->timeout_c,
311 &priv->int_queue, false) < 0) {
312 rc = -ETIME;
313 goto out_err;
314 }
315 status = tpm_tis_status(chip);
316 if (!itpm && (status & TPM_STS_DATA_EXPECT) != 0) {
317 rc = -EIO;
318 goto out_err;
319 }
320
321 return 0;
322
323 out_err:
324 tpm_tis_ready(chip);
325 return rc;
326 }
327
disable_interrupts(struct tpm_chip * chip)328 static void disable_interrupts(struct tpm_chip *chip)
329 {
330 struct tpm_tis_data *priv = dev_get_drvdata(&chip->dev);
331 u32 intmask;
332 int rc;
333
334 rc = tpm_tis_read32(priv, TPM_INT_ENABLE(priv->locality), &intmask);
335 if (rc < 0)
336 intmask = 0;
337
338 intmask &= ~TPM_GLOBAL_INT_ENABLE;
339 rc = tpm_tis_write32(priv, TPM_INT_ENABLE(priv->locality), intmask);
340
341 devm_free_irq(chip->dev.parent, priv->irq, chip);
342 priv->irq = 0;
343 chip->flags &= ~TPM_CHIP_FLAG_IRQ;
344 }
345
346 /*
347 * If interrupts are used (signaled by an irq set in the vendor structure)
348 * tpm.c can skip polling for the data to be available as the interrupt is
349 * waited for here
350 */
tpm_tis_send_main(struct tpm_chip * chip,const u8 * buf,size_t len)351 static int tpm_tis_send_main(struct tpm_chip *chip, const u8 *buf, size_t len)
352 {
353 struct tpm_tis_data *priv = dev_get_drvdata(&chip->dev);
354 int rc;
355 u32 ordinal;
356 unsigned long dur;
357
358 rc = tpm_tis_send_data(chip, buf, len);
359 if (rc < 0)
360 return rc;
361
362 /* go and do it */
363 rc = tpm_tis_write8(priv, TPM_STS(priv->locality), TPM_STS_GO);
364 if (rc < 0)
365 goto out_err;
366
367 if (chip->flags & TPM_CHIP_FLAG_IRQ) {
368 ordinal = be32_to_cpu(*((__be32 *) (buf + 6)));
369
370 if (chip->flags & TPM_CHIP_FLAG_TPM2)
371 dur = tpm2_calc_ordinal_duration(chip, ordinal);
372 else
373 dur = tpm_calc_ordinal_duration(chip, ordinal);
374
375 if (wait_for_tpm_stat
376 (chip, TPM_STS_DATA_AVAIL | TPM_STS_VALID, dur,
377 &priv->read_queue, false) < 0) {
378 rc = -ETIME;
379 goto out_err;
380 }
381 }
382 return 0;
383 out_err:
384 tpm_tis_ready(chip);
385 return rc;
386 }
387
tpm_tis_send(struct tpm_chip * chip,u8 * buf,size_t len)388 static int tpm_tis_send(struct tpm_chip *chip, u8 *buf, size_t len)
389 {
390 int rc, irq;
391 struct tpm_tis_data *priv = dev_get_drvdata(&chip->dev);
392
393 if (!(chip->flags & TPM_CHIP_FLAG_IRQ) || priv->irq_tested)
394 return tpm_tis_send_main(chip, buf, len);
395
396 /* Verify receipt of the expected IRQ */
397 irq = priv->irq;
398 priv->irq = 0;
399 chip->flags &= ~TPM_CHIP_FLAG_IRQ;
400 rc = tpm_tis_send_main(chip, buf, len);
401 priv->irq = irq;
402 chip->flags |= TPM_CHIP_FLAG_IRQ;
403 if (!priv->irq_tested)
404 tpm_msleep(1);
405 if (!priv->irq_tested)
406 disable_interrupts(chip);
407 priv->irq_tested = true;
408 return rc;
409 }
410
411 struct tis_vendor_timeout_override {
412 u32 did_vid;
413 unsigned long timeout_us[4];
414 };
415
416 static const struct tis_vendor_timeout_override vendor_timeout_overrides[] = {
417 /* Atmel 3204 */
418 { 0x32041114, { (TIS_SHORT_TIMEOUT*1000), (TIS_LONG_TIMEOUT*1000),
419 (TIS_SHORT_TIMEOUT*1000), (TIS_SHORT_TIMEOUT*1000) } },
420 };
421
tpm_tis_update_timeouts(struct tpm_chip * chip,unsigned long * timeout_cap)422 static bool tpm_tis_update_timeouts(struct tpm_chip *chip,
423 unsigned long *timeout_cap)
424 {
425 struct tpm_tis_data *priv = dev_get_drvdata(&chip->dev);
426 int i, rc;
427 u32 did_vid;
428
429 if (chip->ops->clk_enable != NULL)
430 chip->ops->clk_enable(chip, true);
431
432 rc = tpm_tis_read32(priv, TPM_DID_VID(0), &did_vid);
433 if (rc < 0)
434 goto out;
435
436 for (i = 0; i != ARRAY_SIZE(vendor_timeout_overrides); i++) {
437 if (vendor_timeout_overrides[i].did_vid != did_vid)
438 continue;
439 memcpy(timeout_cap, vendor_timeout_overrides[i].timeout_us,
440 sizeof(vendor_timeout_overrides[i].timeout_us));
441 rc = true;
442 }
443
444 rc = false;
445
446 out:
447 if (chip->ops->clk_enable != NULL)
448 chip->ops->clk_enable(chip, false);
449
450 return rc;
451 }
452
453 /*
454 * Early probing for iTPM with STS_DATA_EXPECT flaw.
455 * Try sending command without itpm flag set and if that
456 * fails, repeat with itpm flag set.
457 */
probe_itpm(struct tpm_chip * chip)458 static int probe_itpm(struct tpm_chip *chip)
459 {
460 struct tpm_tis_data *priv = dev_get_drvdata(&chip->dev);
461 int rc = 0;
462 u8 cmd_getticks[] = {
463 0x00, 0xc1, 0x00, 0x00, 0x00, 0x0a,
464 0x00, 0x00, 0x00, 0xf1
465 };
466 size_t len = sizeof(cmd_getticks);
467 u16 vendor;
468
469 if (priv->flags & TPM_TIS_ITPM_WORKAROUND)
470 return 0;
471
472 rc = tpm_tis_read16(priv, TPM_DID_VID(0), &vendor);
473 if (rc < 0)
474 return rc;
475
476 /* probe only iTPMS */
477 if (vendor != TPM_VID_INTEL)
478 return 0;
479
480 if (request_locality(chip, 0) != 0)
481 return -EBUSY;
482
483 rc = tpm_tis_send_data(chip, cmd_getticks, len);
484 if (rc == 0)
485 goto out;
486
487 tpm_tis_ready(chip);
488
489 priv->flags |= TPM_TIS_ITPM_WORKAROUND;
490
491 rc = tpm_tis_send_data(chip, cmd_getticks, len);
492 if (rc == 0)
493 dev_info(&chip->dev, "Detected an iTPM.\n");
494 else {
495 priv->flags &= ~TPM_TIS_ITPM_WORKAROUND;
496 rc = -EFAULT;
497 }
498
499 out:
500 tpm_tis_ready(chip);
501 release_locality(chip, priv->locality);
502
503 return rc;
504 }
505
tpm_tis_req_canceled(struct tpm_chip * chip,u8 status)506 static bool tpm_tis_req_canceled(struct tpm_chip *chip, u8 status)
507 {
508 struct tpm_tis_data *priv = dev_get_drvdata(&chip->dev);
509
510 switch (priv->manufacturer_id) {
511 case TPM_VID_WINBOND:
512 return ((status == TPM_STS_VALID) ||
513 (status == (TPM_STS_VALID | TPM_STS_COMMAND_READY)));
514 case TPM_VID_STM:
515 return (status == (TPM_STS_VALID | TPM_STS_COMMAND_READY));
516 default:
517 return (status == TPM_STS_COMMAND_READY);
518 }
519 }
520
tis_int_handler(int dummy,void * dev_id)521 static irqreturn_t tis_int_handler(int dummy, void *dev_id)
522 {
523 struct tpm_chip *chip = dev_id;
524 struct tpm_tis_data *priv = dev_get_drvdata(&chip->dev);
525 u32 interrupt;
526 int i, rc;
527
528 rc = tpm_tis_read32(priv, TPM_INT_STATUS(priv->locality), &interrupt);
529 if (rc < 0)
530 return IRQ_NONE;
531
532 if (interrupt == 0)
533 return IRQ_NONE;
534
535 priv->irq_tested = true;
536 if (interrupt & TPM_INTF_DATA_AVAIL_INT)
537 wake_up_interruptible(&priv->read_queue);
538 if (interrupt & TPM_INTF_LOCALITY_CHANGE_INT)
539 for (i = 0; i < 5; i++)
540 if (check_locality(chip, i))
541 break;
542 if (interrupt &
543 (TPM_INTF_LOCALITY_CHANGE_INT | TPM_INTF_STS_VALID_INT |
544 TPM_INTF_CMD_READY_INT))
545 wake_up_interruptible(&priv->int_queue);
546
547 /* Clear interrupts handled with TPM_EOI */
548 rc = tpm_tis_write32(priv, TPM_INT_STATUS(priv->locality), interrupt);
549 if (rc < 0)
550 return IRQ_NONE;
551
552 tpm_tis_read32(priv, TPM_INT_STATUS(priv->locality), &interrupt);
553 return IRQ_HANDLED;
554 }
555
tpm_tis_gen_interrupt(struct tpm_chip * chip)556 static int tpm_tis_gen_interrupt(struct tpm_chip *chip)
557 {
558 const char *desc = "attempting to generate an interrupt";
559 u32 cap2;
560 cap_t cap;
561
562 if (chip->flags & TPM_CHIP_FLAG_TPM2)
563 return tpm2_get_tpm_pt(chip, 0x100, &cap2, desc);
564 else
565 return tpm_getcap(chip, TPM_CAP_PROP_TIS_TIMEOUT, &cap, desc,
566 0);
567 }
568
569 /* Register the IRQ and issue a command that will cause an interrupt. If an
570 * irq is seen then leave the chip setup for IRQ operation, otherwise reverse
571 * everything and leave in polling mode. Returns 0 on success.
572 */
tpm_tis_probe_irq_single(struct tpm_chip * chip,u32 intmask,int flags,int irq)573 static int tpm_tis_probe_irq_single(struct tpm_chip *chip, u32 intmask,
574 int flags, int irq)
575 {
576 struct tpm_tis_data *priv = dev_get_drvdata(&chip->dev);
577 u8 original_int_vec;
578 int rc;
579 u32 int_status;
580
581 if (devm_request_irq(chip->dev.parent, irq, tis_int_handler, flags,
582 dev_name(&chip->dev), chip) != 0) {
583 dev_info(&chip->dev, "Unable to request irq: %d for probe\n",
584 irq);
585 return -1;
586 }
587 priv->irq = irq;
588
589 rc = tpm_tis_read8(priv, TPM_INT_VECTOR(priv->locality),
590 &original_int_vec);
591 if (rc < 0)
592 return rc;
593
594 rc = tpm_tis_write8(priv, TPM_INT_VECTOR(priv->locality), irq);
595 if (rc < 0)
596 return rc;
597
598 rc = tpm_tis_read32(priv, TPM_INT_STATUS(priv->locality), &int_status);
599 if (rc < 0)
600 return rc;
601
602 /* Clear all existing */
603 rc = tpm_tis_write32(priv, TPM_INT_STATUS(priv->locality), int_status);
604 if (rc < 0)
605 return rc;
606
607 /* Turn on */
608 rc = tpm_tis_write32(priv, TPM_INT_ENABLE(priv->locality),
609 intmask | TPM_GLOBAL_INT_ENABLE);
610 if (rc < 0)
611 return rc;
612
613 priv->irq_tested = false;
614
615 /* Generate an interrupt by having the core call through to
616 * tpm_tis_send
617 */
618 rc = tpm_tis_gen_interrupt(chip);
619 if (rc < 0)
620 return rc;
621
622 /* tpm_tis_send will either confirm the interrupt is working or it
623 * will call disable_irq which undoes all of the above.
624 */
625 if (!(chip->flags & TPM_CHIP_FLAG_IRQ)) {
626 rc = tpm_tis_write8(priv, original_int_vec,
627 TPM_INT_VECTOR(priv->locality));
628 if (rc < 0)
629 return rc;
630
631 return 1;
632 }
633
634 return 0;
635 }
636
637 /* Try to find the IRQ the TPM is using. This is for legacy x86 systems that
638 * do not have ACPI/etc. We typically expect the interrupt to be declared if
639 * present.
640 */
tpm_tis_probe_irq(struct tpm_chip * chip,u32 intmask)641 static void tpm_tis_probe_irq(struct tpm_chip *chip, u32 intmask)
642 {
643 struct tpm_tis_data *priv = dev_get_drvdata(&chip->dev);
644 u8 original_int_vec;
645 int i, rc;
646
647 rc = tpm_tis_read8(priv, TPM_INT_VECTOR(priv->locality),
648 &original_int_vec);
649 if (rc < 0)
650 return;
651
652 if (!original_int_vec) {
653 if (IS_ENABLED(CONFIG_X86))
654 for (i = 3; i <= 15; i++)
655 if (!tpm_tis_probe_irq_single(chip, intmask, 0,
656 i))
657 return;
658 } else if (!tpm_tis_probe_irq_single(chip, intmask, 0,
659 original_int_vec))
660 return;
661 }
662
tpm_tis_remove(struct tpm_chip * chip)663 void tpm_tis_remove(struct tpm_chip *chip)
664 {
665 struct tpm_tis_data *priv = dev_get_drvdata(&chip->dev);
666 u32 reg = TPM_INT_ENABLE(priv->locality);
667 u32 interrupt;
668 int rc;
669
670 tpm_tis_clkrun_enable(chip, true);
671
672 rc = tpm_tis_read32(priv, reg, &interrupt);
673 if (rc < 0)
674 interrupt = 0;
675
676 tpm_tis_write32(priv, reg, ~TPM_GLOBAL_INT_ENABLE & interrupt);
677
678 tpm_tis_clkrun_enable(chip, false);
679
680 if (priv->ilb_base_addr)
681 iounmap(priv->ilb_base_addr);
682 }
683 EXPORT_SYMBOL_GPL(tpm_tis_remove);
684
685 /**
686 * tpm_tis_clkrun_enable() - Keep clkrun protocol disabled for entire duration
687 * of a single TPM command
688 * @chip: TPM chip to use
689 * @value: 1 - Disable CLKRUN protocol, so that clocks are free running
690 * 0 - Enable CLKRUN protocol
691 * Call this function directly in tpm_tis_remove() in error or driver removal
692 * path, since the chip->ops is set to NULL in tpm_chip_unregister().
693 */
tpm_tis_clkrun_enable(struct tpm_chip * chip,bool value)694 static void tpm_tis_clkrun_enable(struct tpm_chip *chip, bool value)
695 {
696 struct tpm_tis_data *data = dev_get_drvdata(&chip->dev);
697 u32 clkrun_val;
698
699 if (!IS_ENABLED(CONFIG_X86) || !is_bsw() ||
700 !data->ilb_base_addr)
701 return;
702
703 if (value) {
704 data->clkrun_enabled++;
705 if (data->clkrun_enabled > 1)
706 return;
707 clkrun_val = ioread32(data->ilb_base_addr + LPC_CNTRL_OFFSET);
708
709 /* Disable LPC CLKRUN# */
710 clkrun_val &= ~LPC_CLKRUN_EN;
711 iowrite32(clkrun_val, data->ilb_base_addr + LPC_CNTRL_OFFSET);
712
713 /*
714 * Write any random value on port 0x80 which is on LPC, to make
715 * sure LPC clock is running before sending any TPM command.
716 */
717 outb(0xCC, 0x80);
718 } else {
719 data->clkrun_enabled--;
720 if (data->clkrun_enabled)
721 return;
722
723 clkrun_val = ioread32(data->ilb_base_addr + LPC_CNTRL_OFFSET);
724
725 /* Enable LPC CLKRUN# */
726 clkrun_val |= LPC_CLKRUN_EN;
727 iowrite32(clkrun_val, data->ilb_base_addr + LPC_CNTRL_OFFSET);
728
729 /*
730 * Write any random value on port 0x80 which is on LPC, to make
731 * sure LPC clock is running before sending any TPM command.
732 */
733 outb(0xCC, 0x80);
734 }
735 }
736
737 static const struct tpm_class_ops tpm_tis = {
738 .flags = TPM_OPS_AUTO_STARTUP,
739 .status = tpm_tis_status,
740 .recv = tpm_tis_recv,
741 .send = tpm_tis_send,
742 .cancel = tpm_tis_ready,
743 .update_timeouts = tpm_tis_update_timeouts,
744 .req_complete_mask = TPM_STS_DATA_AVAIL | TPM_STS_VALID,
745 .req_complete_val = TPM_STS_DATA_AVAIL | TPM_STS_VALID,
746 .req_canceled = tpm_tis_req_canceled,
747 .request_locality = request_locality,
748 .relinquish_locality = release_locality,
749 .clk_enable = tpm_tis_clkrun_enable,
750 };
751
tpm_tis_core_init(struct device * dev,struct tpm_tis_data * priv,int irq,const struct tpm_tis_phy_ops * phy_ops,acpi_handle acpi_dev_handle)752 int tpm_tis_core_init(struct device *dev, struct tpm_tis_data *priv, int irq,
753 const struct tpm_tis_phy_ops *phy_ops,
754 acpi_handle acpi_dev_handle)
755 {
756 u32 vendor, intfcaps, intmask;
757 u32 clkrun_val;
758 u8 rid;
759 int rc, probe;
760 struct tpm_chip *chip;
761
762 chip = tpmm_chip_alloc(dev, &tpm_tis);
763 if (IS_ERR(chip))
764 return PTR_ERR(chip);
765
766 #ifdef CONFIG_ACPI
767 chip->acpi_dev_handle = acpi_dev_handle;
768 #endif
769
770 /* Maximum timeouts */
771 chip->timeout_a = msecs_to_jiffies(TIS_TIMEOUT_A_MAX);
772 chip->timeout_b = msecs_to_jiffies(TIS_TIMEOUT_B_MAX);
773 chip->timeout_c = msecs_to_jiffies(TIS_TIMEOUT_C_MAX);
774 chip->timeout_d = msecs_to_jiffies(TIS_TIMEOUT_D_MAX);
775 priv->phy_ops = phy_ops;
776 dev_set_drvdata(&chip->dev, priv);
777
778 if (is_bsw()) {
779 priv->ilb_base_addr = ioremap(INTEL_LEGACY_BLK_BASE_ADDR,
780 ILB_REMAP_SIZE);
781 if (!priv->ilb_base_addr)
782 return -ENOMEM;
783
784 clkrun_val = ioread32(priv->ilb_base_addr + LPC_CNTRL_OFFSET);
785 /* Check if CLKRUN# is already not enabled in the LPC bus */
786 if (!(clkrun_val & LPC_CLKRUN_EN)) {
787 iounmap(priv->ilb_base_addr);
788 priv->ilb_base_addr = NULL;
789 }
790 }
791
792 if (chip->ops->clk_enable != NULL)
793 chip->ops->clk_enable(chip, true);
794
795 if (wait_startup(chip, 0) != 0) {
796 rc = -ENODEV;
797 goto out_err;
798 }
799
800 /* Take control of the TPM's interrupt hardware and shut it off */
801 rc = tpm_tis_read32(priv, TPM_INT_ENABLE(priv->locality), &intmask);
802 if (rc < 0)
803 goto out_err;
804
805 intmask |= TPM_INTF_CMD_READY_INT | TPM_INTF_LOCALITY_CHANGE_INT |
806 TPM_INTF_DATA_AVAIL_INT | TPM_INTF_STS_VALID_INT;
807 intmask &= ~TPM_GLOBAL_INT_ENABLE;
808 tpm_tis_write32(priv, TPM_INT_ENABLE(priv->locality), intmask);
809
810 rc = tpm2_probe(chip);
811 if (rc)
812 goto out_err;
813
814 rc = tpm_tis_read32(priv, TPM_DID_VID(0), &vendor);
815 if (rc < 0)
816 goto out_err;
817
818 priv->manufacturer_id = vendor;
819
820 rc = tpm_tis_read8(priv, TPM_RID(0), &rid);
821 if (rc < 0)
822 goto out_err;
823
824 dev_info(dev, "%s TPM (device-id 0x%X, rev-id %d)\n",
825 (chip->flags & TPM_CHIP_FLAG_TPM2) ? "2.0" : "1.2",
826 vendor >> 16, rid);
827
828 probe = probe_itpm(chip);
829 if (probe < 0) {
830 rc = -ENODEV;
831 goto out_err;
832 }
833
834 /* Figure out the capabilities */
835 rc = tpm_tis_read32(priv, TPM_INTF_CAPS(priv->locality), &intfcaps);
836 if (rc < 0)
837 goto out_err;
838
839 dev_dbg(dev, "TPM interface capabilities (0x%x):\n",
840 intfcaps);
841 if (intfcaps & TPM_INTF_BURST_COUNT_STATIC)
842 dev_dbg(dev, "\tBurst Count Static\n");
843 if (intfcaps & TPM_INTF_CMD_READY_INT)
844 dev_dbg(dev, "\tCommand Ready Int Support\n");
845 if (intfcaps & TPM_INTF_INT_EDGE_FALLING)
846 dev_dbg(dev, "\tInterrupt Edge Falling\n");
847 if (intfcaps & TPM_INTF_INT_EDGE_RISING)
848 dev_dbg(dev, "\tInterrupt Edge Rising\n");
849 if (intfcaps & TPM_INTF_INT_LEVEL_LOW)
850 dev_dbg(dev, "\tInterrupt Level Low\n");
851 if (intfcaps & TPM_INTF_INT_LEVEL_HIGH)
852 dev_dbg(dev, "\tInterrupt Level High\n");
853 if (intfcaps & TPM_INTF_LOCALITY_CHANGE_INT)
854 dev_dbg(dev, "\tLocality Change Int Support\n");
855 if (intfcaps & TPM_INTF_STS_VALID_INT)
856 dev_dbg(dev, "\tSts Valid Int Support\n");
857 if (intfcaps & TPM_INTF_DATA_AVAIL_INT)
858 dev_dbg(dev, "\tData Avail Int Support\n");
859
860 /* INTERRUPT Setup */
861 init_waitqueue_head(&priv->read_queue);
862 init_waitqueue_head(&priv->int_queue);
863 if (irq != -1) {
864 /* Before doing irq testing issue a command to the TPM in polling mode
865 * to make sure it works. May as well use that command to set the
866 * proper timeouts for the driver.
867 */
868 if (tpm_get_timeouts(chip)) {
869 dev_err(dev, "Could not get TPM timeouts and durations\n");
870 rc = -ENODEV;
871 goto out_err;
872 }
873
874 if (irq) {
875 tpm_tis_probe_irq_single(chip, intmask, IRQF_SHARED,
876 irq);
877 if (!(chip->flags & TPM_CHIP_FLAG_IRQ))
878 dev_err(&chip->dev, FW_BUG
879 "TPM interrupt not working, polling instead\n");
880 } else {
881 tpm_tis_probe_irq(chip, intmask);
882 }
883 }
884
885 rc = tpm_chip_register(chip);
886 if (rc)
887 goto out_err;
888
889 if (chip->ops->clk_enable != NULL)
890 chip->ops->clk_enable(chip, false);
891
892 return 0;
893 out_err:
894 if ((chip->ops != NULL) && (chip->ops->clk_enable != NULL))
895 chip->ops->clk_enable(chip, false);
896
897 tpm_tis_remove(chip);
898
899 return rc;
900 }
901 EXPORT_SYMBOL_GPL(tpm_tis_core_init);
902
903 #ifdef CONFIG_PM_SLEEP
tpm_tis_reenable_interrupts(struct tpm_chip * chip)904 static void tpm_tis_reenable_interrupts(struct tpm_chip *chip)
905 {
906 struct tpm_tis_data *priv = dev_get_drvdata(&chip->dev);
907 u32 intmask;
908 int rc;
909
910 if (chip->ops->clk_enable != NULL)
911 chip->ops->clk_enable(chip, true);
912
913 /* reenable interrupts that device may have lost or
914 * BIOS/firmware may have disabled
915 */
916 rc = tpm_tis_write8(priv, TPM_INT_VECTOR(priv->locality), priv->irq);
917 if (rc < 0)
918 goto out;
919
920 rc = tpm_tis_read32(priv, TPM_INT_ENABLE(priv->locality), &intmask);
921 if (rc < 0)
922 goto out;
923
924 intmask |= TPM_INTF_CMD_READY_INT
925 | TPM_INTF_LOCALITY_CHANGE_INT | TPM_INTF_DATA_AVAIL_INT
926 | TPM_INTF_STS_VALID_INT | TPM_GLOBAL_INT_ENABLE;
927
928 tpm_tis_write32(priv, TPM_INT_ENABLE(priv->locality), intmask);
929
930 out:
931 if (chip->ops->clk_enable != NULL)
932 chip->ops->clk_enable(chip, false);
933
934 return;
935 }
936
tpm_tis_resume(struct device * dev)937 int tpm_tis_resume(struct device *dev)
938 {
939 struct tpm_chip *chip = dev_get_drvdata(dev);
940 int ret;
941
942 if (chip->flags & TPM_CHIP_FLAG_IRQ)
943 tpm_tis_reenable_interrupts(chip);
944
945 ret = tpm_pm_resume(dev);
946 if (ret)
947 return ret;
948
949 /* TPM 1.2 requires self-test on resume. This function actually returns
950 * an error code but for unknown reason it isn't handled.
951 */
952 if (!(chip->flags & TPM_CHIP_FLAG_TPM2))
953 tpm_do_selftest(chip);
954
955 return 0;
956 }
957 EXPORT_SYMBOL_GPL(tpm_tis_resume);
958 #endif
959
960 MODULE_AUTHOR("Leendert van Doorn (leendert@watson.ibm.com)");
961 MODULE_DESCRIPTION("TPM Driver");
962 MODULE_VERSION("2.0");
963 MODULE_LICENSE("GPL");
964