1 /*
2 * Copyright (c) 2014 MediaTek Inc.
3 * Author: Shunli Wang <shunli.wang@mediatek.com>
4 *
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License version 2 as
7 * published by the Free Software Foundation.
8 *
9 * This program is distributed in the hope that it will be useful,
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 * GNU General Public License for more details.
13 */
14
15 #include <linux/clk-provider.h>
16 #include <linux/of.h>
17 #include <linux/of_address.h>
18 #include <linux/of_device.h>
19 #include <linux/platform_device.h>
20
21 #include "clk-mtk.h"
22 #include "clk-gate.h"
23 #include "clk-cpumux.h"
24
25 #include <dt-bindings/clock/mt2701-clk.h>
26
27 /*
28 * For some clocks, we don't care what their actual rates are. And these
29 * clocks may change their rate on different products or different scenarios.
30 * So we model these clocks' rate as 0, to denote it's not an actual rate.
31 */
32 #define DUMMY_RATE 0
33
34 static DEFINE_SPINLOCK(mt2701_clk_lock);
35
36 static const struct mtk_fixed_clk top_fixed_clks[] = {
37 FIXED_CLK(CLK_TOP_DPI, "dpi_ck", "clk26m",
38 108 * MHZ),
39 FIXED_CLK(CLK_TOP_DMPLL, "dmpll_ck", "clk26m",
40 400 * MHZ),
41 FIXED_CLK(CLK_TOP_VENCPLL, "vencpll_ck", "clk26m",
42 295750000),
43 FIXED_CLK(CLK_TOP_HDMI_0_PIX340M, "hdmi_0_pix340m", "clk26m",
44 340 * MHZ),
45 FIXED_CLK(CLK_TOP_HDMI_0_DEEP340M, "hdmi_0_deep340m", "clk26m",
46 340 * MHZ),
47 FIXED_CLK(CLK_TOP_HDMI_0_PLL340M, "hdmi_0_pll340m", "clk26m",
48 340 * MHZ),
49 FIXED_CLK(CLK_TOP_HDMITX_CLKDIG_CTS, "hdmitx_dig_cts", "clk26m",
50 300 * MHZ),
51 FIXED_CLK(CLK_TOP_HADDS2_FB, "hadds2_fbclk", "clk26m",
52 27 * MHZ),
53 FIXED_CLK(CLK_TOP_WBG_DIG_416M, "wbg_dig_ck_416m", "clk26m",
54 416 * MHZ),
55 FIXED_CLK(CLK_TOP_DSI0_LNTC_DSI, "dsi0_lntc_dsi", "clk26m",
56 143 * MHZ),
57 FIXED_CLK(CLK_TOP_HDMI_SCL_RX, "hdmi_scl_rx", "clk26m",
58 27 * MHZ),
59 FIXED_CLK(CLK_TOP_AUD_EXT1, "aud_ext1", "clk26m",
60 DUMMY_RATE),
61 FIXED_CLK(CLK_TOP_AUD_EXT2, "aud_ext2", "clk26m",
62 DUMMY_RATE),
63 FIXED_CLK(CLK_TOP_NFI1X_PAD, "nfi1x_pad", "clk26m",
64 DUMMY_RATE),
65 };
66
67 static const struct mtk_fixed_factor top_fixed_divs[] = {
68 FACTOR(CLK_TOP_SYSPLL, "syspll_ck", "mainpll", 1, 1),
69 FACTOR(CLK_TOP_SYSPLL_D2, "syspll_d2", "mainpll", 1, 2),
70 FACTOR(CLK_TOP_SYSPLL_D3, "syspll_d3", "mainpll", 1, 3),
71 FACTOR(CLK_TOP_SYSPLL_D5, "syspll_d5", "mainpll", 1, 5),
72 FACTOR(CLK_TOP_SYSPLL_D7, "syspll_d7", "mainpll", 1, 7),
73 FACTOR(CLK_TOP_SYSPLL1_D2, "syspll1_d2", "syspll_d2", 1, 2),
74 FACTOR(CLK_TOP_SYSPLL1_D4, "syspll1_d4", "syspll_d2", 1, 4),
75 FACTOR(CLK_TOP_SYSPLL1_D8, "syspll1_d8", "syspll_d2", 1, 8),
76 FACTOR(CLK_TOP_SYSPLL1_D16, "syspll1_d16", "syspll_d2", 1, 16),
77 FACTOR(CLK_TOP_SYSPLL2_D2, "syspll2_d2", "syspll_d3", 1, 2),
78 FACTOR(CLK_TOP_SYSPLL2_D4, "syspll2_d4", "syspll_d3", 1, 4),
79 FACTOR(CLK_TOP_SYSPLL2_D8, "syspll2_d8", "syspll_d3", 1, 8),
80 FACTOR(CLK_TOP_SYSPLL3_D2, "syspll3_d2", "syspll_d5", 1, 2),
81 FACTOR(CLK_TOP_SYSPLL3_D4, "syspll3_d4", "syspll_d5", 1, 4),
82 FACTOR(CLK_TOP_SYSPLL4_D2, "syspll4_d2", "syspll_d7", 1, 2),
83 FACTOR(CLK_TOP_SYSPLL4_D4, "syspll4_d4", "syspll_d7", 1, 4),
84
85 FACTOR(CLK_TOP_UNIVPLL, "univpll_ck", "univpll", 1, 1),
86 FACTOR(CLK_TOP_UNIVPLL_D2, "univpll_d2", "univpll", 1, 2),
87 FACTOR(CLK_TOP_UNIVPLL_D3, "univpll_d3", "univpll", 1, 3),
88 FACTOR(CLK_TOP_UNIVPLL_D5, "univpll_d5", "univpll", 1, 5),
89 FACTOR(CLK_TOP_UNIVPLL_D7, "univpll_d7", "univpll", 1, 7),
90 FACTOR(CLK_TOP_UNIVPLL_D26, "univpll_d26", "univpll", 1, 26),
91 FACTOR(CLK_TOP_UNIVPLL_D52, "univpll_d52", "univpll", 1, 52),
92 FACTOR(CLK_TOP_UNIVPLL_D108, "univpll_d108", "univpll", 1, 108),
93 FACTOR(CLK_TOP_USB_PHY48M, "usb_phy48m_ck", "univpll", 1, 26),
94 FACTOR(CLK_TOP_UNIVPLL1_D2, "univpll1_d2", "univpll_d2", 1, 2),
95 FACTOR(CLK_TOP_UNIVPLL1_D4, "univpll1_d4", "univpll_d2", 1, 4),
96 FACTOR(CLK_TOP_UNIVPLL1_D8, "univpll1_d8", "univpll_d2", 1, 8),
97 FACTOR(CLK_TOP_8BDAC, "8bdac_ck", "univpll_d2", 1, 1),
98 FACTOR(CLK_TOP_UNIVPLL2_D2, "univpll2_d2", "univpll_d3", 1, 2),
99 FACTOR(CLK_TOP_UNIVPLL2_D4, "univpll2_d4", "univpll_d3", 1, 4),
100 FACTOR(CLK_TOP_UNIVPLL2_D8, "univpll2_d8", "univpll_d3", 1, 8),
101 FACTOR(CLK_TOP_UNIVPLL2_D16, "univpll2_d16", "univpll_d3", 1, 16),
102 FACTOR(CLK_TOP_UNIVPLL2_D32, "univpll2_d32", "univpll_d3", 1, 32),
103 FACTOR(CLK_TOP_UNIVPLL3_D2, "univpll3_d2", "univpll_d5", 1, 2),
104 FACTOR(CLK_TOP_UNIVPLL3_D4, "univpll3_d4", "univpll_d5", 1, 4),
105 FACTOR(CLK_TOP_UNIVPLL3_D8, "univpll3_d8", "univpll_d5", 1, 8),
106
107 FACTOR(CLK_TOP_MSDCPLL, "msdcpll_ck", "msdcpll", 1, 1),
108 FACTOR(CLK_TOP_MSDCPLL_D2, "msdcpll_d2", "msdcpll", 1, 2),
109 FACTOR(CLK_TOP_MSDCPLL_D4, "msdcpll_d4", "msdcpll", 1, 4),
110 FACTOR(CLK_TOP_MSDCPLL_D8, "msdcpll_d8", "msdcpll", 1, 8),
111
112 FACTOR(CLK_TOP_MMPLL, "mmpll_ck", "mmpll", 1, 1),
113 FACTOR(CLK_TOP_MMPLL_D2, "mmpll_d2", "mmpll", 1, 2),
114
115 FACTOR(CLK_TOP_DMPLL_D2, "dmpll_d2", "dmpll_ck", 1, 2),
116 FACTOR(CLK_TOP_DMPLL_D4, "dmpll_d4", "dmpll_ck", 1, 4),
117 FACTOR(CLK_TOP_DMPLL_X2, "dmpll_x2", "dmpll_ck", 1, 1),
118
119 FACTOR(CLK_TOP_TVDPLL, "tvdpll_ck", "tvdpll", 1, 1),
120 FACTOR(CLK_TOP_TVDPLL_D2, "tvdpll_d2", "tvdpll", 1, 2),
121 FACTOR(CLK_TOP_TVDPLL_D4, "tvdpll_d4", "tvdpll", 1, 4),
122
123 FACTOR(CLK_TOP_VDECPLL, "vdecpll_ck", "vdecpll", 1, 1),
124 FACTOR(CLK_TOP_TVD2PLL, "tvd2pll_ck", "tvd2pll", 1, 1),
125 FACTOR(CLK_TOP_TVD2PLL_D2, "tvd2pll_d2", "tvd2pll", 1, 2),
126
127 FACTOR(CLK_TOP_MIPIPLL, "mipipll", "dpi_ck", 1, 1),
128 FACTOR(CLK_TOP_MIPIPLL_D2, "mipipll_d2", "dpi_ck", 1, 2),
129 FACTOR(CLK_TOP_MIPIPLL_D4, "mipipll_d4", "dpi_ck", 1, 4),
130
131 FACTOR(CLK_TOP_HDMIPLL, "hdmipll_ck", "hdmitx_dig_cts", 1, 1),
132 FACTOR(CLK_TOP_HDMIPLL_D2, "hdmipll_d2", "hdmitx_dig_cts", 1, 2),
133 FACTOR(CLK_TOP_HDMIPLL_D3, "hdmipll_d3", "hdmitx_dig_cts", 1, 3),
134
135 FACTOR(CLK_TOP_ARMPLL_1P3G, "armpll_1p3g_ck", "armpll", 1, 1),
136
137 FACTOR(CLK_TOP_AUDPLL, "audpll", "audpll_sel", 1, 1),
138 FACTOR(CLK_TOP_AUDPLL_D4, "audpll_d4", "audpll_sel", 1, 4),
139 FACTOR(CLK_TOP_AUDPLL_D8, "audpll_d8", "audpll_sel", 1, 8),
140 FACTOR(CLK_TOP_AUDPLL_D16, "audpll_d16", "audpll_sel", 1, 16),
141 FACTOR(CLK_TOP_AUDPLL_D24, "audpll_d24", "audpll_sel", 1, 24),
142
143 FACTOR(CLK_TOP_AUD1PLL_98M, "aud1pll_98m_ck", "aud1pll", 1, 3),
144 FACTOR(CLK_TOP_AUD2PLL_90M, "aud2pll_90m_ck", "aud2pll", 1, 3),
145 FACTOR(CLK_TOP_HADDS2PLL_98M, "hadds2pll_98m", "hadds2pll", 1, 3),
146 FACTOR(CLK_TOP_HADDS2PLL_294M, "hadds2pll_294m", "hadds2pll", 1, 1),
147 FACTOR(CLK_TOP_ETHPLL_500M, "ethpll_500m_ck", "ethpll", 1, 1),
148 FACTOR(CLK_TOP_CLK26M_D8, "clk26m_d8", "clk26m", 1, 8),
149 FACTOR(CLK_TOP_32K_INTERNAL, "32k_internal", "clk26m", 1, 793),
150 FACTOR(CLK_TOP_32K_EXTERNAL, "32k_external", "rtc32k", 1, 1),
151 FACTOR(CLK_TOP_AXISEL_D4, "axisel_d4", "axi_sel", 1, 4),
152 };
153
154 static const char * const axi_parents[] = {
155 "clk26m",
156 "syspll1_d2",
157 "syspll_d5",
158 "syspll1_d4",
159 "univpll_d5",
160 "univpll2_d2",
161 "mmpll_d2",
162 "dmpll_d2"
163 };
164
165 static const char * const mem_parents[] = {
166 "clk26m",
167 "dmpll_ck"
168 };
169
170 static const char * const ddrphycfg_parents[] = {
171 "clk26m",
172 "syspll1_d8"
173 };
174
175 static const char * const mm_parents[] = {
176 "clk26m",
177 "vencpll_ck",
178 "syspll1_d2",
179 "syspll1_d4",
180 "univpll_d5",
181 "univpll1_d2",
182 "univpll2_d2",
183 "dmpll_ck"
184 };
185
186 static const char * const pwm_parents[] = {
187 "clk26m",
188 "univpll2_d4",
189 "univpll3_d2",
190 "univpll1_d4",
191 };
192
193 static const char * const vdec_parents[] = {
194 "clk26m",
195 "vdecpll_ck",
196 "syspll_d5",
197 "syspll1_d4",
198 "univpll_d5",
199 "univpll2_d2",
200 "vencpll_ck",
201 "msdcpll_d2",
202 "mmpll_d2"
203 };
204
205 static const char * const mfg_parents[] = {
206 "clk26m",
207 "mmpll_ck",
208 "dmpll_x2_ck",
209 "msdcpll_ck",
210 "clk26m",
211 "syspll_d3",
212 "univpll_d3",
213 "univpll1_d2"
214 };
215
216 static const char * const camtg_parents[] = {
217 "clk26m",
218 "univpll_d26",
219 "univpll2_d2",
220 "syspll3_d2",
221 "syspll3_d4",
222 "msdcpll_d2",
223 "mmpll_d2"
224 };
225
226 static const char * const uart_parents[] = {
227 "clk26m",
228 "univpll2_d8"
229 };
230
231 static const char * const spi_parents[] = {
232 "clk26m",
233 "syspll3_d2",
234 "syspll4_d2",
235 "univpll2_d4",
236 "univpll1_d8"
237 };
238
239 static const char * const usb20_parents[] = {
240 "clk26m",
241 "univpll1_d8",
242 "univpll3_d4"
243 };
244
245 static const char * const msdc30_parents[] = {
246 "clk26m",
247 "msdcpll_d2",
248 "syspll2_d2",
249 "syspll1_d4",
250 "univpll1_d4",
251 "univpll2_d4"
252 };
253
254 static const char * const audio_parents[] = {
255 "clk26m",
256 "syspll1_d16"
257 };
258
259 static const char * const aud_intbus_parents[] = {
260 "clk26m",
261 "syspll1_d4",
262 "syspll3_d2",
263 "syspll4_d2",
264 "univpll3_d2",
265 "univpll2_d4"
266 };
267
268 static const char * const pmicspi_parents[] = {
269 "clk26m",
270 "syspll1_d8",
271 "syspll2_d4",
272 "syspll4_d2",
273 "syspll3_d4",
274 "syspll2_d8",
275 "syspll1_d16",
276 "univpll3_d4",
277 "univpll_d26",
278 "dmpll_d2",
279 "dmpll_d4"
280 };
281
282 static const char * const scp_parents[] = {
283 "clk26m",
284 "syspll1_d8",
285 "dmpll_d2",
286 "dmpll_d4"
287 };
288
289 static const char * const dpi0_parents[] = {
290 "clk26m",
291 "mipipll",
292 "mipipll_d2",
293 "mipipll_d4",
294 "clk26m",
295 "tvdpll_ck",
296 "tvdpll_d2",
297 "tvdpll_d4"
298 };
299
300 static const char * const dpi1_parents[] = {
301 "clk26m",
302 "tvdpll_ck",
303 "tvdpll_d2",
304 "tvdpll_d4"
305 };
306
307 static const char * const tve_parents[] = {
308 "clk26m",
309 "mipipll",
310 "mipipll_d2",
311 "mipipll_d4",
312 "clk26m",
313 "tvdpll_ck",
314 "tvdpll_d2",
315 "tvdpll_d4"
316 };
317
318 static const char * const hdmi_parents[] = {
319 "clk26m",
320 "hdmipll_ck",
321 "hdmipll_d2",
322 "hdmipll_d3"
323 };
324
325 static const char * const apll_parents[] = {
326 "clk26m",
327 "audpll",
328 "audpll_d4",
329 "audpll_d8",
330 "audpll_d16",
331 "audpll_d24",
332 "clk26m",
333 "clk26m"
334 };
335
336 static const char * const rtc_parents[] = {
337 "32k_internal",
338 "32k_external",
339 "clk26m",
340 "univpll3_d8"
341 };
342
343 static const char * const nfi2x_parents[] = {
344 "clk26m",
345 "syspll2_d2",
346 "syspll_d7",
347 "univpll3_d2",
348 "syspll2_d4",
349 "univpll3_d4",
350 "syspll4_d4",
351 "clk26m"
352 };
353
354 static const char * const emmc_hclk_parents[] = {
355 "clk26m",
356 "syspll1_d2",
357 "syspll1_d4",
358 "syspll2_d2"
359 };
360
361 static const char * const flash_parents[] = {
362 "clk26m_d8",
363 "clk26m",
364 "syspll2_d8",
365 "syspll3_d4",
366 "univpll3_d4",
367 "syspll4_d2",
368 "syspll2_d4",
369 "univpll2_d4"
370 };
371
372 static const char * const di_parents[] = {
373 "clk26m",
374 "tvd2pll_ck",
375 "tvd2pll_d2",
376 "clk26m"
377 };
378
379 static const char * const nr_osd_parents[] = {
380 "clk26m",
381 "vencpll_ck",
382 "syspll1_d2",
383 "syspll1_d4",
384 "univpll_d5",
385 "univpll1_d2",
386 "univpll2_d2",
387 "dmpll_ck"
388 };
389
390 static const char * const hdmirx_bist_parents[] = {
391 "clk26m",
392 "syspll_d3",
393 "clk26m",
394 "syspll1_d16",
395 "syspll4_d2",
396 "syspll1_d4",
397 "vencpll_ck",
398 "clk26m"
399 };
400
401 static const char * const intdir_parents[] = {
402 "clk26m",
403 "mmpll_ck",
404 "syspll_d2",
405 "univpll_d2"
406 };
407
408 static const char * const asm_parents[] = {
409 "clk26m",
410 "univpll2_d4",
411 "univpll2_d2",
412 "syspll_d5"
413 };
414
415 static const char * const ms_card_parents[] = {
416 "clk26m",
417 "univpll3_d8",
418 "syspll4_d4"
419 };
420
421 static const char * const ethif_parents[] = {
422 "clk26m",
423 "syspll1_d2",
424 "syspll_d5",
425 "syspll1_d4",
426 "univpll_d5",
427 "univpll1_d2",
428 "dmpll_ck",
429 "dmpll_d2"
430 };
431
432 static const char * const hdmirx_parents[] = {
433 "clk26m",
434 "univpll_d52"
435 };
436
437 static const char * const cmsys_parents[] = {
438 "clk26m",
439 "syspll1_d2",
440 "univpll1_d2",
441 "univpll_d5",
442 "syspll_d5",
443 "syspll2_d2",
444 "syspll1_d4",
445 "syspll3_d2",
446 "syspll2_d4",
447 "syspll1_d8",
448 "clk26m",
449 "clk26m",
450 "clk26m",
451 "clk26m",
452 "clk26m"
453 };
454
455 static const char * const clk_8bdac_parents[] = {
456 "32k_internal",
457 "8bdac_ck",
458 "clk26m",
459 "clk26m"
460 };
461
462 static const char * const aud2dvd_parents[] = {
463 "a1sys_hp_ck",
464 "a2sys_hp_ck"
465 };
466
467 static const char * const padmclk_parents[] = {
468 "clk26m",
469 "univpll_d26",
470 "univpll_d52",
471 "univpll_d108",
472 "univpll2_d8",
473 "univpll2_d16",
474 "univpll2_d32"
475 };
476
477 static const char * const aud_mux_parents[] = {
478 "clk26m",
479 "aud1pll_98m_ck",
480 "aud2pll_90m_ck",
481 "hadds2pll_98m",
482 "audio_ext1_ck",
483 "audio_ext2_ck"
484 };
485
486 static const char * const aud_src_parents[] = {
487 "aud_mux1_sel",
488 "aud_mux2_sel"
489 };
490
491 static const char * const cpu_parents[] = {
492 "clk26m",
493 "armpll",
494 "mainpll",
495 "mmpll"
496 };
497
498 static const struct mtk_composite cpu_muxes[] __initconst = {
499 MUX(CLK_INFRA_CPUSEL, "infra_cpu_sel", cpu_parents, 0x0000, 2, 2),
500 };
501
502 static const struct mtk_composite top_muxes[] = {
503 MUX_GATE_FLAGS(CLK_TOP_AXI_SEL, "axi_sel", axi_parents,
504 0x0040, 0, 3, 7, CLK_IS_CRITICAL),
505 MUX_GATE_FLAGS(CLK_TOP_MEM_SEL, "mem_sel", mem_parents,
506 0x0040, 8, 1, 15, CLK_IS_CRITICAL),
507 MUX_GATE_FLAGS(CLK_TOP_DDRPHYCFG_SEL, "ddrphycfg_sel",
508 ddrphycfg_parents, 0x0040, 16, 1, 23, CLK_IS_CRITICAL),
509 MUX_GATE(CLK_TOP_MM_SEL, "mm_sel", mm_parents,
510 0x0040, 24, 3, 31),
511
512 MUX_GATE(CLK_TOP_PWM_SEL, "pwm_sel", pwm_parents,
513 0x0050, 0, 2, 7),
514 MUX_GATE(CLK_TOP_VDEC_SEL, "vdec_sel", vdec_parents,
515 0x0050, 8, 4, 15),
516 MUX_GATE(CLK_TOP_MFG_SEL, "mfg_sel", mfg_parents,
517 0x0050, 16, 3, 23),
518 MUX_GATE(CLK_TOP_CAMTG_SEL, "camtg_sel", camtg_parents,
519 0x0050, 24, 3, 31),
520 MUX_GATE(CLK_TOP_UART_SEL, "uart_sel", uart_parents,
521 0x0060, 0, 1, 7),
522
523 MUX_GATE(CLK_TOP_SPI0_SEL, "spi0_sel", spi_parents,
524 0x0060, 8, 3, 15),
525 MUX_GATE(CLK_TOP_USB20_SEL, "usb20_sel", usb20_parents,
526 0x0060, 16, 2, 23),
527 MUX_GATE(CLK_TOP_MSDC30_0_SEL, "msdc30_0_sel", msdc30_parents,
528 0x0060, 24, 3, 31),
529
530 MUX_GATE(CLK_TOP_MSDC30_1_SEL, "msdc30_1_sel", msdc30_parents,
531 0x0070, 0, 3, 7),
532 MUX_GATE(CLK_TOP_MSDC30_2_SEL, "msdc30_2_sel", msdc30_parents,
533 0x0070, 8, 3, 15),
534 MUX_GATE(CLK_TOP_AUDIO_SEL, "audio_sel", msdc30_parents,
535 0x0070, 16, 1, 23),
536 MUX_GATE(CLK_TOP_AUDINTBUS_SEL, "aud_intbus_sel", aud_intbus_parents,
537 0x0070, 24, 3, 31),
538
539 MUX_GATE(CLK_TOP_PMICSPI_SEL, "pmicspi_sel", pmicspi_parents,
540 0x0080, 0, 4, 7),
541 MUX_GATE(CLK_TOP_SCP_SEL, "scp_sel", scp_parents,
542 0x0080, 8, 2, 15),
543 MUX_GATE(CLK_TOP_DPI0_SEL, "dpi0_sel", dpi0_parents,
544 0x0080, 16, 3, 23),
545 MUX_GATE(CLK_TOP_DPI1_SEL, "dpi1_sel", dpi1_parents,
546 0x0080, 24, 2, 31),
547
548 MUX_GATE(CLK_TOP_TVE_SEL, "tve_sel", tve_parents,
549 0x0090, 0, 3, 7),
550 MUX_GATE(CLK_TOP_HDMI_SEL, "hdmi_sel", hdmi_parents,
551 0x0090, 8, 2, 15),
552 MUX_GATE(CLK_TOP_APLL_SEL, "apll_sel", apll_parents,
553 0x0090, 16, 3, 23),
554
555 MUX_GATE_FLAGS(CLK_TOP_RTC_SEL, "rtc_sel", rtc_parents,
556 0x00A0, 0, 2, 7, CLK_IS_CRITICAL),
557 MUX_GATE(CLK_TOP_NFI2X_SEL, "nfi2x_sel", nfi2x_parents,
558 0x00A0, 8, 3, 15),
559 MUX_GATE(CLK_TOP_EMMC_HCLK_SEL, "emmc_hclk_sel", emmc_hclk_parents,
560 0x00A0, 24, 2, 31),
561
562 MUX_GATE(CLK_TOP_FLASH_SEL, "flash_sel", flash_parents,
563 0x00B0, 0, 3, 7),
564 MUX_GATE(CLK_TOP_DI_SEL, "di_sel", di_parents,
565 0x00B0, 8, 2, 15),
566 MUX_GATE(CLK_TOP_NR_SEL, "nr_sel", nr_osd_parents,
567 0x00B0, 16, 3, 23),
568 MUX_GATE(CLK_TOP_OSD_SEL, "osd_sel", nr_osd_parents,
569 0x00B0, 24, 3, 31),
570
571 MUX_GATE(CLK_TOP_HDMIRX_BIST_SEL, "hdmirx_bist_sel",
572 hdmirx_bist_parents, 0x00C0, 0, 3, 7),
573 MUX_GATE(CLK_TOP_INTDIR_SEL, "intdir_sel", intdir_parents,
574 0x00C0, 8, 2, 15),
575 MUX_GATE(CLK_TOP_ASM_I_SEL, "asm_i_sel", asm_parents,
576 0x00C0, 16, 2, 23),
577 MUX_GATE(CLK_TOP_ASM_M_SEL, "asm_m_sel", asm_parents,
578 0x00C0, 24, 3, 31),
579
580 MUX_GATE(CLK_TOP_ASM_H_SEL, "asm_h_sel", asm_parents,
581 0x00D0, 0, 2, 7),
582 MUX_GATE(CLK_TOP_MS_CARD_SEL, "ms_card_sel", ms_card_parents,
583 0x00D0, 16, 2, 23),
584 MUX_GATE(CLK_TOP_ETHIF_SEL, "ethif_sel", ethif_parents,
585 0x00D0, 24, 3, 31),
586
587 MUX_GATE(CLK_TOP_HDMIRX26_24_SEL, "hdmirx26_24_sel", hdmirx_parents,
588 0x00E0, 0, 1, 7),
589 MUX_GATE(CLK_TOP_MSDC30_3_SEL, "msdc30_3_sel", msdc30_parents,
590 0x00E0, 8, 3, 15),
591 MUX_GATE(CLK_TOP_CMSYS_SEL, "cmsys_sel", cmsys_parents,
592 0x00E0, 16, 4, 23),
593
594 MUX_GATE(CLK_TOP_SPI1_SEL, "spi2_sel", spi_parents,
595 0x00E0, 24, 3, 31),
596 MUX_GATE(CLK_TOP_SPI2_SEL, "spi1_sel", spi_parents,
597 0x00F0, 0, 3, 7),
598 MUX_GATE(CLK_TOP_8BDAC_SEL, "8bdac_sel", clk_8bdac_parents,
599 0x00F0, 8, 2, 15),
600 MUX_GATE(CLK_TOP_AUD2DVD_SEL, "aud2dvd_sel", aud2dvd_parents,
601 0x00F0, 16, 1, 23),
602
603 MUX(CLK_TOP_PADMCLK_SEL, "padmclk_sel", padmclk_parents,
604 0x0100, 0, 3),
605
606 MUX(CLK_TOP_AUD_MUX1_SEL, "aud_mux1_sel", aud_mux_parents,
607 0x012c, 0, 3),
608 MUX(CLK_TOP_AUD_MUX2_SEL, "aud_mux2_sel", aud_mux_parents,
609 0x012c, 3, 3),
610 MUX(CLK_TOP_AUDPLL_MUX_SEL, "audpll_sel", aud_mux_parents,
611 0x012c, 6, 3),
612 MUX_GATE(CLK_TOP_AUD_K1_SRC_SEL, "aud_k1_src_sel", aud_src_parents,
613 0x012c, 15, 1, 23),
614 MUX_GATE(CLK_TOP_AUD_K2_SRC_SEL, "aud_k2_src_sel", aud_src_parents,
615 0x012c, 16, 1, 24),
616 MUX_GATE(CLK_TOP_AUD_K3_SRC_SEL, "aud_k3_src_sel", aud_src_parents,
617 0x012c, 17, 1, 25),
618 MUX_GATE(CLK_TOP_AUD_K4_SRC_SEL, "aud_k4_src_sel", aud_src_parents,
619 0x012c, 18, 1, 26),
620 MUX_GATE(CLK_TOP_AUD_K5_SRC_SEL, "aud_k5_src_sel", aud_src_parents,
621 0x012c, 19, 1, 27),
622 MUX_GATE(CLK_TOP_AUD_K6_SRC_SEL, "aud_k6_src_sel", aud_src_parents,
623 0x012c, 20, 1, 28),
624 };
625
626 static const struct mtk_clk_divider top_adj_divs[] = {
627 DIV_ADJ(CLK_TOP_AUD_EXTCK1_DIV, "audio_ext1_ck", "aud_ext1",
628 0x0120, 0, 8),
629 DIV_ADJ(CLK_TOP_AUD_EXTCK2_DIV, "audio_ext2_ck", "aud_ext2",
630 0x0120, 8, 8),
631 DIV_ADJ(CLK_TOP_AUD_MUX1_DIV, "aud_mux1_div", "aud_mux1_sel",
632 0x0120, 16, 8),
633 DIV_ADJ(CLK_TOP_AUD_MUX2_DIV, "aud_mux2_div", "aud_mux2_sel",
634 0x0120, 24, 8),
635 DIV_ADJ(CLK_TOP_AUD_K1_SRC_DIV, "aud_k1_src_div", "aud_k1_src_sel",
636 0x0124, 0, 8),
637 DIV_ADJ(CLK_TOP_AUD_K2_SRC_DIV, "aud_k2_src_div", "aud_k2_src_sel",
638 0x0124, 8, 8),
639 DIV_ADJ(CLK_TOP_AUD_K3_SRC_DIV, "aud_k3_src_div", "aud_k3_src_sel",
640 0x0124, 16, 8),
641 DIV_ADJ(CLK_TOP_AUD_K4_SRC_DIV, "aud_k4_src_div", "aud_k4_src_sel",
642 0x0124, 24, 8),
643 DIV_ADJ(CLK_TOP_AUD_K5_SRC_DIV, "aud_k5_src_div", "aud_k5_src_sel",
644 0x0128, 0, 8),
645 DIV_ADJ(CLK_TOP_AUD_K6_SRC_DIV, "aud_k6_src_div", "aud_k6_src_sel",
646 0x0128, 8, 8),
647 };
648
649 static const struct mtk_gate_regs top_aud_cg_regs = {
650 .sta_ofs = 0x012C,
651 };
652
653 #define GATE_TOP_AUD(_id, _name, _parent, _shift) { \
654 .id = _id, \
655 .name = _name, \
656 .parent_name = _parent, \
657 .regs = &top_aud_cg_regs, \
658 .shift = _shift, \
659 .ops = &mtk_clk_gate_ops_no_setclr, \
660 }
661
662 static const struct mtk_gate top_clks[] = {
663 GATE_TOP_AUD(CLK_TOP_AUD_48K_TIMING, "a1sys_hp_ck", "aud_mux1_div",
664 21),
665 GATE_TOP_AUD(CLK_TOP_AUD_44K_TIMING, "a2sys_hp_ck", "aud_mux2_div",
666 22),
667 GATE_TOP_AUD(CLK_TOP_AUD_I2S1_MCLK, "aud_i2s1_mclk", "aud_k1_src_div",
668 23),
669 GATE_TOP_AUD(CLK_TOP_AUD_I2S2_MCLK, "aud_i2s2_mclk", "aud_k2_src_div",
670 24),
671 GATE_TOP_AUD(CLK_TOP_AUD_I2S3_MCLK, "aud_i2s3_mclk", "aud_k3_src_div",
672 25),
673 GATE_TOP_AUD(CLK_TOP_AUD_I2S4_MCLK, "aud_i2s4_mclk", "aud_k4_src_div",
674 26),
675 GATE_TOP_AUD(CLK_TOP_AUD_I2S5_MCLK, "aud_i2s5_mclk", "aud_k5_src_div",
676 27),
677 GATE_TOP_AUD(CLK_TOP_AUD_I2S6_MCLK, "aud_i2s6_mclk", "aud_k6_src_div",
678 28),
679 };
680
mtk_topckgen_init(struct platform_device * pdev)681 static int mtk_topckgen_init(struct platform_device *pdev)
682 {
683 struct clk_onecell_data *clk_data;
684 void __iomem *base;
685 struct device_node *node = pdev->dev.of_node;
686 struct resource *res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
687
688 base = devm_ioremap_resource(&pdev->dev, res);
689 if (IS_ERR(base))
690 return PTR_ERR(base);
691
692 clk_data = mtk_alloc_clk_data(CLK_TOP_NR);
693
694 mtk_clk_register_fixed_clks(top_fixed_clks, ARRAY_SIZE(top_fixed_clks),
695 clk_data);
696
697 mtk_clk_register_factors(top_fixed_divs, ARRAY_SIZE(top_fixed_divs),
698 clk_data);
699
700 mtk_clk_register_composites(top_muxes, ARRAY_SIZE(top_muxes),
701 base, &mt2701_clk_lock, clk_data);
702
703 mtk_clk_register_dividers(top_adj_divs, ARRAY_SIZE(top_adj_divs),
704 base, &mt2701_clk_lock, clk_data);
705
706 mtk_clk_register_gates(node, top_clks, ARRAY_SIZE(top_clks),
707 clk_data);
708
709 return of_clk_add_provider(node, of_clk_src_onecell_get, clk_data);
710 }
711
712 static const struct mtk_gate_regs infra_cg_regs = {
713 .set_ofs = 0x0040,
714 .clr_ofs = 0x0044,
715 .sta_ofs = 0x0048,
716 };
717
718 #define GATE_ICG(_id, _name, _parent, _shift) { \
719 .id = _id, \
720 .name = _name, \
721 .parent_name = _parent, \
722 .regs = &infra_cg_regs, \
723 .shift = _shift, \
724 .ops = &mtk_clk_gate_ops_setclr, \
725 }
726
727 static const struct mtk_gate infra_clks[] = {
728 GATE_ICG(CLK_INFRA_DBG, "dbgclk", "axi_sel", 0),
729 GATE_ICG(CLK_INFRA_SMI, "smi_ck", "mm_sel", 1),
730 GATE_ICG(CLK_INFRA_QAXI_CM4, "cm4_ck", "axi_sel", 2),
731 GATE_ICG(CLK_INFRA_AUD_SPLIN_B, "audio_splin_bck", "hadds2pll_294m", 4),
732 GATE_ICG(CLK_INFRA_AUDIO, "audio_ck", "clk26m", 5),
733 GATE_ICG(CLK_INFRA_EFUSE, "efuse_ck", "clk26m", 6),
734 GATE_ICG(CLK_INFRA_L2C_SRAM, "l2c_sram_ck", "mm_sel", 7),
735 GATE_ICG(CLK_INFRA_M4U, "m4u_ck", "mem_sel", 8),
736 GATE_ICG(CLK_INFRA_CONNMCU, "connsys_bus", "wbg_dig_ck_416m", 12),
737 GATE_ICG(CLK_INFRA_TRNG, "trng_ck", "axi_sel", 13),
738 GATE_ICG(CLK_INFRA_RAMBUFIF, "rambufif_ck", "mem_sel", 14),
739 GATE_ICG(CLK_INFRA_CPUM, "cpum_ck", "mem_sel", 15),
740 GATE_ICG(CLK_INFRA_KP, "kp_ck", "axi_sel", 16),
741 GATE_ICG(CLK_INFRA_CEC, "cec_ck", "rtc_sel", 18),
742 GATE_ICG(CLK_INFRA_IRRX, "irrx_ck", "axi_sel", 19),
743 GATE_ICG(CLK_INFRA_PMICSPI, "pmicspi_ck", "pmicspi_sel", 22),
744 GATE_ICG(CLK_INFRA_PMICWRAP, "pmicwrap_ck", "axi_sel", 23),
745 GATE_ICG(CLK_INFRA_DDCCI, "ddcci_ck", "axi_sel", 24),
746 };
747
748 static const struct mtk_fixed_factor infra_fixed_divs[] = {
749 FACTOR(CLK_INFRA_CLK_13M, "clk13m", "clk26m", 1, 2),
750 };
751
752 static struct clk_onecell_data *infra_clk_data;
753
mtk_infrasys_init_early(struct device_node * node)754 static void mtk_infrasys_init_early(struct device_node *node)
755 {
756 int r, i;
757
758 if (!infra_clk_data) {
759 infra_clk_data = mtk_alloc_clk_data(CLK_INFRA_NR);
760
761 for (i = 0; i < CLK_INFRA_NR; i++)
762 infra_clk_data->clks[i] = ERR_PTR(-EPROBE_DEFER);
763 }
764
765 mtk_clk_register_factors(infra_fixed_divs, ARRAY_SIZE(infra_fixed_divs),
766 infra_clk_data);
767
768 mtk_clk_register_cpumuxes(node, cpu_muxes, ARRAY_SIZE(cpu_muxes),
769 infra_clk_data);
770
771 r = of_clk_add_provider(node, of_clk_src_onecell_get, infra_clk_data);
772 if (r)
773 pr_err("%s(): could not register clock provider: %d\n",
774 __func__, r);
775 }
776 CLK_OF_DECLARE_DRIVER(mtk_infra, "mediatek,mt2701-infracfg",
777 mtk_infrasys_init_early);
778
mtk_infrasys_init(struct platform_device * pdev)779 static int mtk_infrasys_init(struct platform_device *pdev)
780 {
781 int r, i;
782 struct device_node *node = pdev->dev.of_node;
783
784 if (!infra_clk_data) {
785 infra_clk_data = mtk_alloc_clk_data(CLK_INFRA_NR);
786 } else {
787 for (i = 0; i < CLK_INFRA_NR; i++) {
788 if (infra_clk_data->clks[i] == ERR_PTR(-EPROBE_DEFER))
789 infra_clk_data->clks[i] = ERR_PTR(-ENOENT);
790 }
791 }
792
793 mtk_clk_register_gates(node, infra_clks, ARRAY_SIZE(infra_clks),
794 infra_clk_data);
795 mtk_clk_register_factors(infra_fixed_divs, ARRAY_SIZE(infra_fixed_divs),
796 infra_clk_data);
797
798 r = of_clk_add_provider(node, of_clk_src_onecell_get, infra_clk_data);
799 if (r)
800 return r;
801
802 mtk_register_reset_controller(node, 2, 0x30);
803
804 return 0;
805 }
806
807 static const struct mtk_gate_regs peri0_cg_regs = {
808 .set_ofs = 0x0008,
809 .clr_ofs = 0x0010,
810 .sta_ofs = 0x0018,
811 };
812
813 static const struct mtk_gate_regs peri1_cg_regs = {
814 .set_ofs = 0x000c,
815 .clr_ofs = 0x0014,
816 .sta_ofs = 0x001c,
817 };
818
819 #define GATE_PERI0(_id, _name, _parent, _shift) { \
820 .id = _id, \
821 .name = _name, \
822 .parent_name = _parent, \
823 .regs = &peri0_cg_regs, \
824 .shift = _shift, \
825 .ops = &mtk_clk_gate_ops_setclr, \
826 }
827
828 #define GATE_PERI1(_id, _name, _parent, _shift) { \
829 .id = _id, \
830 .name = _name, \
831 .parent_name = _parent, \
832 .regs = &peri1_cg_regs, \
833 .shift = _shift, \
834 .ops = &mtk_clk_gate_ops_setclr, \
835 }
836
837 static const struct mtk_gate peri_clks[] = {
838 GATE_PERI0(CLK_PERI_USB0_MCU, "usb0_mcu_ck", "axi_sel", 31),
839 GATE_PERI0(CLK_PERI_ETH, "eth_ck", "clk26m", 30),
840 GATE_PERI0(CLK_PERI_SPI0, "spi0_ck", "spi0_sel", 29),
841 GATE_PERI0(CLK_PERI_AUXADC, "auxadc_ck", "clk26m", 28),
842 GATE_PERI0(CLK_PERI_I2C3, "i2c3_ck", "clk26m", 27),
843 GATE_PERI0(CLK_PERI_I2C2, "i2c2_ck", "axi_sel", 26),
844 GATE_PERI0(CLK_PERI_I2C1, "i2c1_ck", "axi_sel", 25),
845 GATE_PERI0(CLK_PERI_I2C0, "i2c0_ck", "axi_sel", 24),
846 GATE_PERI0(CLK_PERI_BTIF, "bitif_ck", "axi_sel", 23),
847 GATE_PERI0(CLK_PERI_UART3, "uart3_ck", "axi_sel", 22),
848 GATE_PERI0(CLK_PERI_UART2, "uart2_ck", "axi_sel", 21),
849 GATE_PERI0(CLK_PERI_UART1, "uart1_ck", "axi_sel", 20),
850 GATE_PERI0(CLK_PERI_UART0, "uart0_ck", "axi_sel", 19),
851 GATE_PERI0(CLK_PERI_NLI, "nli_ck", "axi_sel", 18),
852 GATE_PERI0(CLK_PERI_MSDC50_3, "msdc50_3_ck", "emmc_hclk_sel", 17),
853 GATE_PERI0(CLK_PERI_MSDC30_3, "msdc30_3_ck", "msdc30_3_sel", 16),
854 GATE_PERI0(CLK_PERI_MSDC30_2, "msdc30_2_ck", "msdc30_2_sel", 15),
855 GATE_PERI0(CLK_PERI_MSDC30_1, "msdc30_1_ck", "msdc30_1_sel", 14),
856 GATE_PERI0(CLK_PERI_MSDC30_0, "msdc30_0_ck", "msdc30_0_sel", 13),
857 GATE_PERI0(CLK_PERI_AP_DMA, "ap_dma_ck", "axi_sel", 12),
858 GATE_PERI0(CLK_PERI_USB1, "usb1_ck", "usb20_sel", 11),
859 GATE_PERI0(CLK_PERI_USB0, "usb0_ck", "usb20_sel", 10),
860 GATE_PERI0(CLK_PERI_PWM, "pwm_ck", "axi_sel", 9),
861 GATE_PERI0(CLK_PERI_PWM7, "pwm7_ck", "axisel_d4", 8),
862 GATE_PERI0(CLK_PERI_PWM6, "pwm6_ck", "axisel_d4", 7),
863 GATE_PERI0(CLK_PERI_PWM5, "pwm5_ck", "axisel_d4", 6),
864 GATE_PERI0(CLK_PERI_PWM4, "pwm4_ck", "axisel_d4", 5),
865 GATE_PERI0(CLK_PERI_PWM3, "pwm3_ck", "axisel_d4", 4),
866 GATE_PERI0(CLK_PERI_PWM2, "pwm2_ck", "axisel_d4", 3),
867 GATE_PERI0(CLK_PERI_PWM1, "pwm1_ck", "axisel_d4", 2),
868 GATE_PERI0(CLK_PERI_THERM, "therm_ck", "axi_sel", 1),
869 GATE_PERI0(CLK_PERI_NFI, "nfi_ck", "nfi2x_sel", 0),
870
871 GATE_PERI1(CLK_PERI_FCI, "fci_ck", "ms_card_sel", 11),
872 GATE_PERI1(CLK_PERI_SPI2, "spi2_ck", "spi2_sel", 10),
873 GATE_PERI1(CLK_PERI_SPI1, "spi1_ck", "spi1_sel", 9),
874 GATE_PERI1(CLK_PERI_HOST89_DVD, "host89_dvd_ck", "aud2dvd_sel", 8),
875 GATE_PERI1(CLK_PERI_HOST89_SPI, "host89_spi_ck", "spi0_sel", 7),
876 GATE_PERI1(CLK_PERI_HOST89_INT, "host89_int_ck", "axi_sel", 6),
877 GATE_PERI1(CLK_PERI_FLASH, "flash_ck", "nfi2x_sel", 5),
878 GATE_PERI1(CLK_PERI_NFI_PAD, "nfi_pad_ck", "nfi1x_pad", 4),
879 GATE_PERI1(CLK_PERI_NFI_ECC, "nfi_ecc_ck", "nfi1x_pad", 3),
880 GATE_PERI1(CLK_PERI_GCPU, "gcpu_ck", "axi_sel", 2),
881 GATE_PERI1(CLK_PERI_USB_SLV, "usbslv_ck", "axi_sel", 1),
882 GATE_PERI1(CLK_PERI_USB1_MCU, "usb1_mcu_ck", "axi_sel", 0),
883 };
884
885 static const char * const uart_ck_sel_parents[] = {
886 "clk26m",
887 "uart_sel",
888 };
889
890 static const struct mtk_composite peri_muxs[] = {
891 MUX(CLK_PERI_UART0_SEL, "uart0_ck_sel", uart_ck_sel_parents,
892 0x40c, 0, 1),
893 MUX(CLK_PERI_UART1_SEL, "uart1_ck_sel", uart_ck_sel_parents,
894 0x40c, 1, 1),
895 MUX(CLK_PERI_UART2_SEL, "uart2_ck_sel", uart_ck_sel_parents,
896 0x40c, 2, 1),
897 MUX(CLK_PERI_UART3_SEL, "uart3_ck_sel", uart_ck_sel_parents,
898 0x40c, 3, 1),
899 };
900
mtk_pericfg_init(struct platform_device * pdev)901 static int mtk_pericfg_init(struct platform_device *pdev)
902 {
903 struct clk_onecell_data *clk_data;
904 void __iomem *base;
905 int r;
906 struct device_node *node = pdev->dev.of_node;
907 struct resource *res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
908
909 base = devm_ioremap_resource(&pdev->dev, res);
910 if (IS_ERR(base))
911 return PTR_ERR(base);
912
913 clk_data = mtk_alloc_clk_data(CLK_PERI_NR);
914
915 mtk_clk_register_gates(node, peri_clks, ARRAY_SIZE(peri_clks),
916 clk_data);
917
918 mtk_clk_register_composites(peri_muxs, ARRAY_SIZE(peri_muxs), base,
919 &mt2701_clk_lock, clk_data);
920
921 r = of_clk_add_provider(node, of_clk_src_onecell_get, clk_data);
922 if (r)
923 return r;
924
925 mtk_register_reset_controller(node, 2, 0x0);
926
927 return 0;
928 }
929
930 #define MT8590_PLL_FMAX (2000 * MHZ)
931 #define CON0_MT8590_RST_BAR BIT(27)
932
933 #define PLL(_id, _name, _reg, _pwr_reg, _en_mask, _flags, _pcwbits, _pd_reg, \
934 _pd_shift, _tuner_reg, _pcw_reg, _pcw_shift) { \
935 .id = _id, \
936 .name = _name, \
937 .reg = _reg, \
938 .pwr_reg = _pwr_reg, \
939 .en_mask = _en_mask, \
940 .flags = _flags, \
941 .rst_bar_mask = CON0_MT8590_RST_BAR, \
942 .fmax = MT8590_PLL_FMAX, \
943 .pcwbits = _pcwbits, \
944 .pd_reg = _pd_reg, \
945 .pd_shift = _pd_shift, \
946 .tuner_reg = _tuner_reg, \
947 .pcw_reg = _pcw_reg, \
948 .pcw_shift = _pcw_shift, \
949 }
950
951 static const struct mtk_pll_data apmixed_plls[] = {
952 PLL(CLK_APMIXED_ARMPLL, "armpll", 0x200, 0x20c, 0x80000001,
953 PLL_AO, 21, 0x204, 24, 0x0, 0x204, 0),
954 PLL(CLK_APMIXED_MAINPLL, "mainpll", 0x210, 0x21c, 0xf0000001,
955 HAVE_RST_BAR, 21, 0x210, 4, 0x0, 0x214, 0),
956 PLL(CLK_APMIXED_UNIVPLL, "univpll", 0x220, 0x22c, 0xf3000001,
957 HAVE_RST_BAR, 7, 0x220, 4, 0x0, 0x224, 14),
958 PLL(CLK_APMIXED_MMPLL, "mmpll", 0x230, 0x23c, 0x00000001, 0,
959 21, 0x230, 4, 0x0, 0x234, 0),
960 PLL(CLK_APMIXED_MSDCPLL, "msdcpll", 0x240, 0x24c, 0x00000001, 0,
961 21, 0x240, 4, 0x0, 0x244, 0),
962 PLL(CLK_APMIXED_TVDPLL, "tvdpll", 0x250, 0x25c, 0x00000001, 0,
963 21, 0x250, 4, 0x0, 0x254, 0),
964 PLL(CLK_APMIXED_AUD1PLL, "aud1pll", 0x270, 0x27c, 0x00000001, 0,
965 31, 0x270, 4, 0x0, 0x274, 0),
966 PLL(CLK_APMIXED_TRGPLL, "trgpll", 0x280, 0x28c, 0x00000001, 0,
967 31, 0x280, 4, 0x0, 0x284, 0),
968 PLL(CLK_APMIXED_ETHPLL, "ethpll", 0x290, 0x29c, 0x00000001, 0,
969 31, 0x290, 4, 0x0, 0x294, 0),
970 PLL(CLK_APMIXED_VDECPLL, "vdecpll", 0x2a0, 0x2ac, 0x00000001, 0,
971 31, 0x2a0, 4, 0x0, 0x2a4, 0),
972 PLL(CLK_APMIXED_HADDS2PLL, "hadds2pll", 0x2b0, 0x2bc, 0x00000001, 0,
973 31, 0x2b0, 4, 0x0, 0x2b4, 0),
974 PLL(CLK_APMIXED_AUD2PLL, "aud2pll", 0x2c0, 0x2cc, 0x00000001, 0,
975 31, 0x2c0, 4, 0x0, 0x2c4, 0),
976 PLL(CLK_APMIXED_TVD2PLL, "tvd2pll", 0x2d0, 0x2dc, 0x00000001, 0,
977 21, 0x2d0, 4, 0x0, 0x2d4, 0),
978 };
979
mtk_apmixedsys_init(struct platform_device * pdev)980 static int mtk_apmixedsys_init(struct platform_device *pdev)
981 {
982 struct clk_onecell_data *clk_data;
983 struct device_node *node = pdev->dev.of_node;
984
985 clk_data = mtk_alloc_clk_data(CLK_APMIXED_NR);
986 if (!clk_data)
987 return -ENOMEM;
988
989 mtk_clk_register_plls(node, apmixed_plls, ARRAY_SIZE(apmixed_plls),
990 clk_data);
991
992 return of_clk_add_provider(node, of_clk_src_onecell_get, clk_data);
993 }
994
995 static const struct of_device_id of_match_clk_mt2701[] = {
996 {
997 .compatible = "mediatek,mt2701-topckgen",
998 .data = mtk_topckgen_init,
999 }, {
1000 .compatible = "mediatek,mt2701-infracfg",
1001 .data = mtk_infrasys_init,
1002 }, {
1003 .compatible = "mediatek,mt2701-pericfg",
1004 .data = mtk_pericfg_init,
1005 }, {
1006 .compatible = "mediatek,mt2701-apmixedsys",
1007 .data = mtk_apmixedsys_init,
1008 }, {
1009 /* sentinel */
1010 }
1011 };
1012
clk_mt2701_probe(struct platform_device * pdev)1013 static int clk_mt2701_probe(struct platform_device *pdev)
1014 {
1015 int (*clk_init)(struct platform_device *);
1016 int r;
1017
1018 clk_init = of_device_get_match_data(&pdev->dev);
1019 if (!clk_init)
1020 return -EINVAL;
1021
1022 r = clk_init(pdev);
1023 if (r)
1024 dev_err(&pdev->dev,
1025 "could not register clock provider: %s: %d\n",
1026 pdev->name, r);
1027
1028 return r;
1029 }
1030
1031 static struct platform_driver clk_mt2701_drv = {
1032 .probe = clk_mt2701_probe,
1033 .driver = {
1034 .name = "clk-mt2701",
1035 .of_match_table = of_match_clk_mt2701,
1036 },
1037 };
1038
clk_mt2701_init(void)1039 static int __init clk_mt2701_init(void)
1040 {
1041 return platform_driver_register(&clk_mt2701_drv);
1042 }
1043
1044 arch_initcall(clk_mt2701_init);
1045