1 /*
2 * Cryptographic API.
3 *
4 * Support for ATMEL AES HW acceleration.
5 *
6 * Copyright (c) 2012 Eukréa Electromatique - ATMEL
7 * Author: Nicolas Royer <nicolas@eukrea.com>
8 *
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License version 2 as published
11 * by the Free Software Foundation.
12 *
13 * Some ideas are from omap-aes.c driver.
14 */
15
16
17 #include <linux/kernel.h>
18 #include <linux/module.h>
19 #include <linux/slab.h>
20 #include <linux/err.h>
21 #include <linux/clk.h>
22 #include <linux/io.h>
23 #include <linux/hw_random.h>
24 #include <linux/platform_device.h>
25
26 #include <linux/device.h>
27 #include <linux/init.h>
28 #include <linux/errno.h>
29 #include <linux/interrupt.h>
30 #include <linux/irq.h>
31 #include <linux/scatterlist.h>
32 #include <linux/dma-mapping.h>
33 #include <linux/of_device.h>
34 #include <linux/delay.h>
35 #include <linux/crypto.h>
36 #include <crypto/scatterwalk.h>
37 #include <crypto/algapi.h>
38 #include <crypto/aes.h>
39 #include <crypto/xts.h>
40 #include <crypto/internal/aead.h>
41 #include <linux/platform_data/crypto-atmel.h>
42 #include <dt-bindings/dma/at91.h>
43 #include "atmel-aes-regs.h"
44 #include "atmel-authenc.h"
45
46 #define ATMEL_AES_PRIORITY 300
47
48 #define ATMEL_AES_BUFFER_ORDER 2
49 #define ATMEL_AES_BUFFER_SIZE (PAGE_SIZE << ATMEL_AES_BUFFER_ORDER)
50
51 #define CFB8_BLOCK_SIZE 1
52 #define CFB16_BLOCK_SIZE 2
53 #define CFB32_BLOCK_SIZE 4
54 #define CFB64_BLOCK_SIZE 8
55
56 #define SIZE_IN_WORDS(x) ((x) >> 2)
57
58 /* AES flags */
59 /* Reserve bits [18:16] [14:12] [1:0] for mode (same as for AES_MR) */
60 #define AES_FLAGS_ENCRYPT AES_MR_CYPHER_ENC
61 #define AES_FLAGS_GTAGEN AES_MR_GTAGEN
62 #define AES_FLAGS_OPMODE_MASK (AES_MR_OPMOD_MASK | AES_MR_CFBS_MASK)
63 #define AES_FLAGS_ECB AES_MR_OPMOD_ECB
64 #define AES_FLAGS_CBC AES_MR_OPMOD_CBC
65 #define AES_FLAGS_OFB AES_MR_OPMOD_OFB
66 #define AES_FLAGS_CFB128 (AES_MR_OPMOD_CFB | AES_MR_CFBS_128b)
67 #define AES_FLAGS_CFB64 (AES_MR_OPMOD_CFB | AES_MR_CFBS_64b)
68 #define AES_FLAGS_CFB32 (AES_MR_OPMOD_CFB | AES_MR_CFBS_32b)
69 #define AES_FLAGS_CFB16 (AES_MR_OPMOD_CFB | AES_MR_CFBS_16b)
70 #define AES_FLAGS_CFB8 (AES_MR_OPMOD_CFB | AES_MR_CFBS_8b)
71 #define AES_FLAGS_CTR AES_MR_OPMOD_CTR
72 #define AES_FLAGS_GCM AES_MR_OPMOD_GCM
73 #define AES_FLAGS_XTS AES_MR_OPMOD_XTS
74
75 #define AES_FLAGS_MODE_MASK (AES_FLAGS_OPMODE_MASK | \
76 AES_FLAGS_ENCRYPT | \
77 AES_FLAGS_GTAGEN)
78
79 #define AES_FLAGS_INIT BIT(2)
80 #define AES_FLAGS_BUSY BIT(3)
81 #define AES_FLAGS_DUMP_REG BIT(4)
82 #define AES_FLAGS_OWN_SHA BIT(5)
83
84 #define AES_FLAGS_PERSISTENT (AES_FLAGS_INIT | AES_FLAGS_BUSY)
85
86 #define ATMEL_AES_QUEUE_LENGTH 50
87
88 #define ATMEL_AES_DMA_THRESHOLD 256
89
90
91 struct atmel_aes_caps {
92 bool has_dualbuff;
93 bool has_cfb64;
94 bool has_gcm;
95 bool has_xts;
96 bool has_authenc;
97 u32 max_burst_size;
98 };
99
100 struct atmel_aes_dev;
101
102
103 typedef int (*atmel_aes_fn_t)(struct atmel_aes_dev *);
104
105
106 struct atmel_aes_base_ctx {
107 struct atmel_aes_dev *dd;
108 atmel_aes_fn_t start;
109 int keylen;
110 u32 key[AES_KEYSIZE_256 / sizeof(u32)];
111 u16 block_size;
112 };
113
114 struct atmel_aes_ctx {
115 struct atmel_aes_base_ctx base;
116 };
117
118 struct atmel_aes_ctr_ctx {
119 struct atmel_aes_base_ctx base;
120
121 u32 iv[AES_BLOCK_SIZE / sizeof(u32)];
122 size_t offset;
123 struct scatterlist src[2];
124 struct scatterlist dst[2];
125 };
126
127 struct atmel_aes_gcm_ctx {
128 struct atmel_aes_base_ctx base;
129
130 struct scatterlist src[2];
131 struct scatterlist dst[2];
132
133 u32 j0[AES_BLOCK_SIZE / sizeof(u32)];
134 u32 tag[AES_BLOCK_SIZE / sizeof(u32)];
135 u32 ghash[AES_BLOCK_SIZE / sizeof(u32)];
136 size_t textlen;
137
138 const u32 *ghash_in;
139 u32 *ghash_out;
140 atmel_aes_fn_t ghash_resume;
141 };
142
143 struct atmel_aes_xts_ctx {
144 struct atmel_aes_base_ctx base;
145
146 u32 key2[AES_KEYSIZE_256 / sizeof(u32)];
147 };
148
149 #ifdef CONFIG_CRYPTO_DEV_ATMEL_AUTHENC
150 struct atmel_aes_authenc_ctx {
151 struct atmel_aes_base_ctx base;
152 struct atmel_sha_authenc_ctx *auth;
153 };
154 #endif
155
156 struct atmel_aes_reqctx {
157 unsigned long mode;
158 };
159
160 #ifdef CONFIG_CRYPTO_DEV_ATMEL_AUTHENC
161 struct atmel_aes_authenc_reqctx {
162 struct atmel_aes_reqctx base;
163
164 struct scatterlist src[2];
165 struct scatterlist dst[2];
166 size_t textlen;
167 u32 digest[SHA512_DIGEST_SIZE / sizeof(u32)];
168
169 /* auth_req MUST be place last. */
170 struct ahash_request auth_req;
171 };
172 #endif
173
174 struct atmel_aes_dma {
175 struct dma_chan *chan;
176 struct scatterlist *sg;
177 int nents;
178 unsigned int remainder;
179 unsigned int sg_len;
180 };
181
182 struct atmel_aes_dev {
183 struct list_head list;
184 unsigned long phys_base;
185 void __iomem *io_base;
186
187 struct crypto_async_request *areq;
188 struct atmel_aes_base_ctx *ctx;
189
190 bool is_async;
191 atmel_aes_fn_t resume;
192 atmel_aes_fn_t cpu_transfer_complete;
193
194 struct device *dev;
195 struct clk *iclk;
196 int irq;
197
198 unsigned long flags;
199
200 spinlock_t lock;
201 struct crypto_queue queue;
202
203 struct tasklet_struct done_task;
204 struct tasklet_struct queue_task;
205
206 size_t total;
207 size_t datalen;
208 u32 *data;
209
210 struct atmel_aes_dma src;
211 struct atmel_aes_dma dst;
212
213 size_t buflen;
214 void *buf;
215 struct scatterlist aligned_sg;
216 struct scatterlist *real_dst;
217
218 struct atmel_aes_caps caps;
219
220 u32 hw_version;
221 };
222
223 struct atmel_aes_drv {
224 struct list_head dev_list;
225 spinlock_t lock;
226 };
227
228 static struct atmel_aes_drv atmel_aes = {
229 .dev_list = LIST_HEAD_INIT(atmel_aes.dev_list),
230 .lock = __SPIN_LOCK_UNLOCKED(atmel_aes.lock),
231 };
232
233 #ifdef VERBOSE_DEBUG
atmel_aes_reg_name(u32 offset,char * tmp,size_t sz)234 static const char *atmel_aes_reg_name(u32 offset, char *tmp, size_t sz)
235 {
236 switch (offset) {
237 case AES_CR:
238 return "CR";
239
240 case AES_MR:
241 return "MR";
242
243 case AES_ISR:
244 return "ISR";
245
246 case AES_IMR:
247 return "IMR";
248
249 case AES_IER:
250 return "IER";
251
252 case AES_IDR:
253 return "IDR";
254
255 case AES_KEYWR(0):
256 case AES_KEYWR(1):
257 case AES_KEYWR(2):
258 case AES_KEYWR(3):
259 case AES_KEYWR(4):
260 case AES_KEYWR(5):
261 case AES_KEYWR(6):
262 case AES_KEYWR(7):
263 snprintf(tmp, sz, "KEYWR[%u]", (offset - AES_KEYWR(0)) >> 2);
264 break;
265
266 case AES_IDATAR(0):
267 case AES_IDATAR(1):
268 case AES_IDATAR(2):
269 case AES_IDATAR(3):
270 snprintf(tmp, sz, "IDATAR[%u]", (offset - AES_IDATAR(0)) >> 2);
271 break;
272
273 case AES_ODATAR(0):
274 case AES_ODATAR(1):
275 case AES_ODATAR(2):
276 case AES_ODATAR(3):
277 snprintf(tmp, sz, "ODATAR[%u]", (offset - AES_ODATAR(0)) >> 2);
278 break;
279
280 case AES_IVR(0):
281 case AES_IVR(1):
282 case AES_IVR(2):
283 case AES_IVR(3):
284 snprintf(tmp, sz, "IVR[%u]", (offset - AES_IVR(0)) >> 2);
285 break;
286
287 case AES_AADLENR:
288 return "AADLENR";
289
290 case AES_CLENR:
291 return "CLENR";
292
293 case AES_GHASHR(0):
294 case AES_GHASHR(1):
295 case AES_GHASHR(2):
296 case AES_GHASHR(3):
297 snprintf(tmp, sz, "GHASHR[%u]", (offset - AES_GHASHR(0)) >> 2);
298 break;
299
300 case AES_TAGR(0):
301 case AES_TAGR(1):
302 case AES_TAGR(2):
303 case AES_TAGR(3):
304 snprintf(tmp, sz, "TAGR[%u]", (offset - AES_TAGR(0)) >> 2);
305 break;
306
307 case AES_CTRR:
308 return "CTRR";
309
310 case AES_GCMHR(0):
311 case AES_GCMHR(1):
312 case AES_GCMHR(2):
313 case AES_GCMHR(3):
314 snprintf(tmp, sz, "GCMHR[%u]", (offset - AES_GCMHR(0)) >> 2);
315 break;
316
317 case AES_EMR:
318 return "EMR";
319
320 case AES_TWR(0):
321 case AES_TWR(1):
322 case AES_TWR(2):
323 case AES_TWR(3):
324 snprintf(tmp, sz, "TWR[%u]", (offset - AES_TWR(0)) >> 2);
325 break;
326
327 case AES_ALPHAR(0):
328 case AES_ALPHAR(1):
329 case AES_ALPHAR(2):
330 case AES_ALPHAR(3):
331 snprintf(tmp, sz, "ALPHAR[%u]", (offset - AES_ALPHAR(0)) >> 2);
332 break;
333
334 default:
335 snprintf(tmp, sz, "0x%02x", offset);
336 break;
337 }
338
339 return tmp;
340 }
341 #endif /* VERBOSE_DEBUG */
342
343 /* Shared functions */
344
atmel_aes_read(struct atmel_aes_dev * dd,u32 offset)345 static inline u32 atmel_aes_read(struct atmel_aes_dev *dd, u32 offset)
346 {
347 u32 value = readl_relaxed(dd->io_base + offset);
348
349 #ifdef VERBOSE_DEBUG
350 if (dd->flags & AES_FLAGS_DUMP_REG) {
351 char tmp[16];
352
353 dev_vdbg(dd->dev, "read 0x%08x from %s\n", value,
354 atmel_aes_reg_name(offset, tmp, sizeof(tmp)));
355 }
356 #endif /* VERBOSE_DEBUG */
357
358 return value;
359 }
360
atmel_aes_write(struct atmel_aes_dev * dd,u32 offset,u32 value)361 static inline void atmel_aes_write(struct atmel_aes_dev *dd,
362 u32 offset, u32 value)
363 {
364 #ifdef VERBOSE_DEBUG
365 if (dd->flags & AES_FLAGS_DUMP_REG) {
366 char tmp[16];
367
368 dev_vdbg(dd->dev, "write 0x%08x into %s\n", value,
369 atmel_aes_reg_name(offset, tmp, sizeof(tmp)));
370 }
371 #endif /* VERBOSE_DEBUG */
372
373 writel_relaxed(value, dd->io_base + offset);
374 }
375
atmel_aes_read_n(struct atmel_aes_dev * dd,u32 offset,u32 * value,int count)376 static void atmel_aes_read_n(struct atmel_aes_dev *dd, u32 offset,
377 u32 *value, int count)
378 {
379 for (; count--; value++, offset += 4)
380 *value = atmel_aes_read(dd, offset);
381 }
382
atmel_aes_write_n(struct atmel_aes_dev * dd,u32 offset,const u32 * value,int count)383 static void atmel_aes_write_n(struct atmel_aes_dev *dd, u32 offset,
384 const u32 *value, int count)
385 {
386 for (; count--; value++, offset += 4)
387 atmel_aes_write(dd, offset, *value);
388 }
389
atmel_aes_read_block(struct atmel_aes_dev * dd,u32 offset,u32 * value)390 static inline void atmel_aes_read_block(struct atmel_aes_dev *dd, u32 offset,
391 u32 *value)
392 {
393 atmel_aes_read_n(dd, offset, value, SIZE_IN_WORDS(AES_BLOCK_SIZE));
394 }
395
atmel_aes_write_block(struct atmel_aes_dev * dd,u32 offset,const u32 * value)396 static inline void atmel_aes_write_block(struct atmel_aes_dev *dd, u32 offset,
397 const u32 *value)
398 {
399 atmel_aes_write_n(dd, offset, value, SIZE_IN_WORDS(AES_BLOCK_SIZE));
400 }
401
atmel_aes_wait_for_data_ready(struct atmel_aes_dev * dd,atmel_aes_fn_t resume)402 static inline int atmel_aes_wait_for_data_ready(struct atmel_aes_dev *dd,
403 atmel_aes_fn_t resume)
404 {
405 u32 isr = atmel_aes_read(dd, AES_ISR);
406
407 if (unlikely(isr & AES_INT_DATARDY))
408 return resume(dd);
409
410 dd->resume = resume;
411 atmel_aes_write(dd, AES_IER, AES_INT_DATARDY);
412 return -EINPROGRESS;
413 }
414
atmel_aes_padlen(size_t len,size_t block_size)415 static inline size_t atmel_aes_padlen(size_t len, size_t block_size)
416 {
417 len &= block_size - 1;
418 return len ? block_size - len : 0;
419 }
420
atmel_aes_find_dev(struct atmel_aes_base_ctx * ctx)421 static struct atmel_aes_dev *atmel_aes_find_dev(struct atmel_aes_base_ctx *ctx)
422 {
423 struct atmel_aes_dev *aes_dd = NULL;
424 struct atmel_aes_dev *tmp;
425
426 spin_lock_bh(&atmel_aes.lock);
427 if (!ctx->dd) {
428 list_for_each_entry(tmp, &atmel_aes.dev_list, list) {
429 aes_dd = tmp;
430 break;
431 }
432 ctx->dd = aes_dd;
433 } else {
434 aes_dd = ctx->dd;
435 }
436
437 spin_unlock_bh(&atmel_aes.lock);
438
439 return aes_dd;
440 }
441
atmel_aes_hw_init(struct atmel_aes_dev * dd)442 static int atmel_aes_hw_init(struct atmel_aes_dev *dd)
443 {
444 int err;
445
446 err = clk_enable(dd->iclk);
447 if (err)
448 return err;
449
450 if (!(dd->flags & AES_FLAGS_INIT)) {
451 atmel_aes_write(dd, AES_CR, AES_CR_SWRST);
452 atmel_aes_write(dd, AES_MR, 0xE << AES_MR_CKEY_OFFSET);
453 dd->flags |= AES_FLAGS_INIT;
454 }
455
456 return 0;
457 }
458
atmel_aes_get_version(struct atmel_aes_dev * dd)459 static inline unsigned int atmel_aes_get_version(struct atmel_aes_dev *dd)
460 {
461 return atmel_aes_read(dd, AES_HW_VERSION) & 0x00000fff;
462 }
463
atmel_aes_hw_version_init(struct atmel_aes_dev * dd)464 static int atmel_aes_hw_version_init(struct atmel_aes_dev *dd)
465 {
466 int err;
467
468 err = atmel_aes_hw_init(dd);
469 if (err)
470 return err;
471
472 dd->hw_version = atmel_aes_get_version(dd);
473
474 dev_info(dd->dev, "version: 0x%x\n", dd->hw_version);
475
476 clk_disable(dd->iclk);
477 return 0;
478 }
479
atmel_aes_set_mode(struct atmel_aes_dev * dd,const struct atmel_aes_reqctx * rctx)480 static inline void atmel_aes_set_mode(struct atmel_aes_dev *dd,
481 const struct atmel_aes_reqctx *rctx)
482 {
483 /* Clear all but persistent flags and set request flags. */
484 dd->flags = (dd->flags & AES_FLAGS_PERSISTENT) | rctx->mode;
485 }
486
atmel_aes_is_encrypt(const struct atmel_aes_dev * dd)487 static inline bool atmel_aes_is_encrypt(const struct atmel_aes_dev *dd)
488 {
489 return (dd->flags & AES_FLAGS_ENCRYPT);
490 }
491
492 #ifdef CONFIG_CRYPTO_DEV_ATMEL_AUTHENC
493 static void atmel_aes_authenc_complete(struct atmel_aes_dev *dd, int err);
494 #endif
495
atmel_aes_complete(struct atmel_aes_dev * dd,int err)496 static inline int atmel_aes_complete(struct atmel_aes_dev *dd, int err)
497 {
498 #ifdef CONFIG_CRYPTO_DEV_ATMEL_AUTHENC
499 atmel_aes_authenc_complete(dd, err);
500 #endif
501
502 clk_disable(dd->iclk);
503 dd->flags &= ~AES_FLAGS_BUSY;
504
505 if (dd->is_async)
506 dd->areq->complete(dd->areq, err);
507
508 tasklet_schedule(&dd->queue_task);
509
510 return err;
511 }
512
atmel_aes_write_ctrl_key(struct atmel_aes_dev * dd,bool use_dma,const u32 * iv,const u32 * key,int keylen)513 static void atmel_aes_write_ctrl_key(struct atmel_aes_dev *dd, bool use_dma,
514 const u32 *iv, const u32 *key, int keylen)
515 {
516 u32 valmr = 0;
517
518 /* MR register must be set before IV registers */
519 if (keylen == AES_KEYSIZE_128)
520 valmr |= AES_MR_KEYSIZE_128;
521 else if (keylen == AES_KEYSIZE_192)
522 valmr |= AES_MR_KEYSIZE_192;
523 else
524 valmr |= AES_MR_KEYSIZE_256;
525
526 valmr |= dd->flags & AES_FLAGS_MODE_MASK;
527
528 if (use_dma) {
529 valmr |= AES_MR_SMOD_IDATAR0;
530 if (dd->caps.has_dualbuff)
531 valmr |= AES_MR_DUALBUFF;
532 } else {
533 valmr |= AES_MR_SMOD_AUTO;
534 }
535
536 atmel_aes_write(dd, AES_MR, valmr);
537
538 atmel_aes_write_n(dd, AES_KEYWR(0), key, SIZE_IN_WORDS(keylen));
539
540 if (iv && (valmr & AES_MR_OPMOD_MASK) != AES_MR_OPMOD_ECB)
541 atmel_aes_write_block(dd, AES_IVR(0), iv);
542 }
543
atmel_aes_write_ctrl(struct atmel_aes_dev * dd,bool use_dma,const u32 * iv)544 static inline void atmel_aes_write_ctrl(struct atmel_aes_dev *dd, bool use_dma,
545 const u32 *iv)
546
547 {
548 atmel_aes_write_ctrl_key(dd, use_dma, iv,
549 dd->ctx->key, dd->ctx->keylen);
550 }
551
552 /* CPU transfer */
553
atmel_aes_cpu_transfer(struct atmel_aes_dev * dd)554 static int atmel_aes_cpu_transfer(struct atmel_aes_dev *dd)
555 {
556 int err = 0;
557 u32 isr;
558
559 for (;;) {
560 atmel_aes_read_block(dd, AES_ODATAR(0), dd->data);
561 dd->data += 4;
562 dd->datalen -= AES_BLOCK_SIZE;
563
564 if (dd->datalen < AES_BLOCK_SIZE)
565 break;
566
567 atmel_aes_write_block(dd, AES_IDATAR(0), dd->data);
568
569 isr = atmel_aes_read(dd, AES_ISR);
570 if (!(isr & AES_INT_DATARDY)) {
571 dd->resume = atmel_aes_cpu_transfer;
572 atmel_aes_write(dd, AES_IER, AES_INT_DATARDY);
573 return -EINPROGRESS;
574 }
575 }
576
577 if (!sg_copy_from_buffer(dd->real_dst, sg_nents(dd->real_dst),
578 dd->buf, dd->total))
579 err = -EINVAL;
580
581 if (err)
582 return atmel_aes_complete(dd, err);
583
584 return dd->cpu_transfer_complete(dd);
585 }
586
atmel_aes_cpu_start(struct atmel_aes_dev * dd,struct scatterlist * src,struct scatterlist * dst,size_t len,atmel_aes_fn_t resume)587 static int atmel_aes_cpu_start(struct atmel_aes_dev *dd,
588 struct scatterlist *src,
589 struct scatterlist *dst,
590 size_t len,
591 atmel_aes_fn_t resume)
592 {
593 size_t padlen = atmel_aes_padlen(len, AES_BLOCK_SIZE);
594
595 if (unlikely(len == 0))
596 return -EINVAL;
597
598 sg_copy_to_buffer(src, sg_nents(src), dd->buf, len);
599
600 dd->total = len;
601 dd->real_dst = dst;
602 dd->cpu_transfer_complete = resume;
603 dd->datalen = len + padlen;
604 dd->data = (u32 *)dd->buf;
605 atmel_aes_write_block(dd, AES_IDATAR(0), dd->data);
606 return atmel_aes_wait_for_data_ready(dd, atmel_aes_cpu_transfer);
607 }
608
609
610 /* DMA transfer */
611
612 static void atmel_aes_dma_callback(void *data);
613
atmel_aes_check_aligned(struct atmel_aes_dev * dd,struct scatterlist * sg,size_t len,struct atmel_aes_dma * dma)614 static bool atmel_aes_check_aligned(struct atmel_aes_dev *dd,
615 struct scatterlist *sg,
616 size_t len,
617 struct atmel_aes_dma *dma)
618 {
619 int nents;
620
621 if (!IS_ALIGNED(len, dd->ctx->block_size))
622 return false;
623
624 for (nents = 0; sg; sg = sg_next(sg), ++nents) {
625 if (!IS_ALIGNED(sg->offset, sizeof(u32)))
626 return false;
627
628 if (len <= sg->length) {
629 if (!IS_ALIGNED(len, dd->ctx->block_size))
630 return false;
631
632 dma->nents = nents+1;
633 dma->remainder = sg->length - len;
634 sg->length = len;
635 return true;
636 }
637
638 if (!IS_ALIGNED(sg->length, dd->ctx->block_size))
639 return false;
640
641 len -= sg->length;
642 }
643
644 return false;
645 }
646
atmel_aes_restore_sg(const struct atmel_aes_dma * dma)647 static inline void atmel_aes_restore_sg(const struct atmel_aes_dma *dma)
648 {
649 struct scatterlist *sg = dma->sg;
650 int nents = dma->nents;
651
652 if (!dma->remainder)
653 return;
654
655 while (--nents > 0 && sg)
656 sg = sg_next(sg);
657
658 if (!sg)
659 return;
660
661 sg->length += dma->remainder;
662 }
663
atmel_aes_map(struct atmel_aes_dev * dd,struct scatterlist * src,struct scatterlist * dst,size_t len)664 static int atmel_aes_map(struct atmel_aes_dev *dd,
665 struct scatterlist *src,
666 struct scatterlist *dst,
667 size_t len)
668 {
669 bool src_aligned, dst_aligned;
670 size_t padlen;
671
672 dd->total = len;
673 dd->src.sg = src;
674 dd->dst.sg = dst;
675 dd->real_dst = dst;
676
677 src_aligned = atmel_aes_check_aligned(dd, src, len, &dd->src);
678 if (src == dst)
679 dst_aligned = src_aligned;
680 else
681 dst_aligned = atmel_aes_check_aligned(dd, dst, len, &dd->dst);
682 if (!src_aligned || !dst_aligned) {
683 padlen = atmel_aes_padlen(len, dd->ctx->block_size);
684
685 if (dd->buflen < len + padlen)
686 return -ENOMEM;
687
688 if (!src_aligned) {
689 sg_copy_to_buffer(src, sg_nents(src), dd->buf, len);
690 dd->src.sg = &dd->aligned_sg;
691 dd->src.nents = 1;
692 dd->src.remainder = 0;
693 }
694
695 if (!dst_aligned) {
696 dd->dst.sg = &dd->aligned_sg;
697 dd->dst.nents = 1;
698 dd->dst.remainder = 0;
699 }
700
701 sg_init_table(&dd->aligned_sg, 1);
702 sg_set_buf(&dd->aligned_sg, dd->buf, len + padlen);
703 }
704
705 if (dd->src.sg == dd->dst.sg) {
706 dd->src.sg_len = dma_map_sg(dd->dev, dd->src.sg, dd->src.nents,
707 DMA_BIDIRECTIONAL);
708 dd->dst.sg_len = dd->src.sg_len;
709 if (!dd->src.sg_len)
710 return -EFAULT;
711 } else {
712 dd->src.sg_len = dma_map_sg(dd->dev, dd->src.sg, dd->src.nents,
713 DMA_TO_DEVICE);
714 if (!dd->src.sg_len)
715 return -EFAULT;
716
717 dd->dst.sg_len = dma_map_sg(dd->dev, dd->dst.sg, dd->dst.nents,
718 DMA_FROM_DEVICE);
719 if (!dd->dst.sg_len) {
720 dma_unmap_sg(dd->dev, dd->src.sg, dd->src.nents,
721 DMA_TO_DEVICE);
722 return -EFAULT;
723 }
724 }
725
726 return 0;
727 }
728
atmel_aes_unmap(struct atmel_aes_dev * dd)729 static void atmel_aes_unmap(struct atmel_aes_dev *dd)
730 {
731 if (dd->src.sg == dd->dst.sg) {
732 dma_unmap_sg(dd->dev, dd->src.sg, dd->src.nents,
733 DMA_BIDIRECTIONAL);
734
735 if (dd->src.sg != &dd->aligned_sg)
736 atmel_aes_restore_sg(&dd->src);
737 } else {
738 dma_unmap_sg(dd->dev, dd->dst.sg, dd->dst.nents,
739 DMA_FROM_DEVICE);
740
741 if (dd->dst.sg != &dd->aligned_sg)
742 atmel_aes_restore_sg(&dd->dst);
743
744 dma_unmap_sg(dd->dev, dd->src.sg, dd->src.nents,
745 DMA_TO_DEVICE);
746
747 if (dd->src.sg != &dd->aligned_sg)
748 atmel_aes_restore_sg(&dd->src);
749 }
750
751 if (dd->dst.sg == &dd->aligned_sg)
752 sg_copy_from_buffer(dd->real_dst, sg_nents(dd->real_dst),
753 dd->buf, dd->total);
754 }
755
atmel_aes_dma_transfer_start(struct atmel_aes_dev * dd,enum dma_slave_buswidth addr_width,enum dma_transfer_direction dir,u32 maxburst)756 static int atmel_aes_dma_transfer_start(struct atmel_aes_dev *dd,
757 enum dma_slave_buswidth addr_width,
758 enum dma_transfer_direction dir,
759 u32 maxburst)
760 {
761 struct dma_async_tx_descriptor *desc;
762 struct dma_slave_config config;
763 dma_async_tx_callback callback;
764 struct atmel_aes_dma *dma;
765 int err;
766
767 memset(&config, 0, sizeof(config));
768 config.direction = dir;
769 config.src_addr_width = addr_width;
770 config.dst_addr_width = addr_width;
771 config.src_maxburst = maxburst;
772 config.dst_maxburst = maxburst;
773
774 switch (dir) {
775 case DMA_MEM_TO_DEV:
776 dma = &dd->src;
777 callback = NULL;
778 config.dst_addr = dd->phys_base + AES_IDATAR(0);
779 break;
780
781 case DMA_DEV_TO_MEM:
782 dma = &dd->dst;
783 callback = atmel_aes_dma_callback;
784 config.src_addr = dd->phys_base + AES_ODATAR(0);
785 break;
786
787 default:
788 return -EINVAL;
789 }
790
791 err = dmaengine_slave_config(dma->chan, &config);
792 if (err)
793 return err;
794
795 desc = dmaengine_prep_slave_sg(dma->chan, dma->sg, dma->sg_len, dir,
796 DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
797 if (!desc)
798 return -ENOMEM;
799
800 desc->callback = callback;
801 desc->callback_param = dd;
802 dmaengine_submit(desc);
803 dma_async_issue_pending(dma->chan);
804
805 return 0;
806 }
807
atmel_aes_dma_transfer_stop(struct atmel_aes_dev * dd,enum dma_transfer_direction dir)808 static void atmel_aes_dma_transfer_stop(struct atmel_aes_dev *dd,
809 enum dma_transfer_direction dir)
810 {
811 struct atmel_aes_dma *dma;
812
813 switch (dir) {
814 case DMA_MEM_TO_DEV:
815 dma = &dd->src;
816 break;
817
818 case DMA_DEV_TO_MEM:
819 dma = &dd->dst;
820 break;
821
822 default:
823 return;
824 }
825
826 dmaengine_terminate_all(dma->chan);
827 }
828
atmel_aes_dma_start(struct atmel_aes_dev * dd,struct scatterlist * src,struct scatterlist * dst,size_t len,atmel_aes_fn_t resume)829 static int atmel_aes_dma_start(struct atmel_aes_dev *dd,
830 struct scatterlist *src,
831 struct scatterlist *dst,
832 size_t len,
833 atmel_aes_fn_t resume)
834 {
835 enum dma_slave_buswidth addr_width;
836 u32 maxburst;
837 int err;
838
839 switch (dd->ctx->block_size) {
840 case CFB8_BLOCK_SIZE:
841 addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE;
842 maxburst = 1;
843 break;
844
845 case CFB16_BLOCK_SIZE:
846 addr_width = DMA_SLAVE_BUSWIDTH_2_BYTES;
847 maxburst = 1;
848 break;
849
850 case CFB32_BLOCK_SIZE:
851 case CFB64_BLOCK_SIZE:
852 addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
853 maxburst = 1;
854 break;
855
856 case AES_BLOCK_SIZE:
857 addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
858 maxburst = dd->caps.max_burst_size;
859 break;
860
861 default:
862 err = -EINVAL;
863 goto exit;
864 }
865
866 err = atmel_aes_map(dd, src, dst, len);
867 if (err)
868 goto exit;
869
870 dd->resume = resume;
871
872 /* Set output DMA transfer first */
873 err = atmel_aes_dma_transfer_start(dd, addr_width, DMA_DEV_TO_MEM,
874 maxburst);
875 if (err)
876 goto unmap;
877
878 /* Then set input DMA transfer */
879 err = atmel_aes_dma_transfer_start(dd, addr_width, DMA_MEM_TO_DEV,
880 maxburst);
881 if (err)
882 goto output_transfer_stop;
883
884 return -EINPROGRESS;
885
886 output_transfer_stop:
887 atmel_aes_dma_transfer_stop(dd, DMA_DEV_TO_MEM);
888 unmap:
889 atmel_aes_unmap(dd);
890 exit:
891 return atmel_aes_complete(dd, err);
892 }
893
atmel_aes_dma_stop(struct atmel_aes_dev * dd)894 static void atmel_aes_dma_stop(struct atmel_aes_dev *dd)
895 {
896 atmel_aes_dma_transfer_stop(dd, DMA_MEM_TO_DEV);
897 atmel_aes_dma_transfer_stop(dd, DMA_DEV_TO_MEM);
898 atmel_aes_unmap(dd);
899 }
900
atmel_aes_dma_callback(void * data)901 static void atmel_aes_dma_callback(void *data)
902 {
903 struct atmel_aes_dev *dd = data;
904
905 atmel_aes_dma_stop(dd);
906 dd->is_async = true;
907 (void)dd->resume(dd);
908 }
909
atmel_aes_handle_queue(struct atmel_aes_dev * dd,struct crypto_async_request * new_areq)910 static int atmel_aes_handle_queue(struct atmel_aes_dev *dd,
911 struct crypto_async_request *new_areq)
912 {
913 struct crypto_async_request *areq, *backlog;
914 struct atmel_aes_base_ctx *ctx;
915 unsigned long flags;
916 bool start_async;
917 int err, ret = 0;
918
919 spin_lock_irqsave(&dd->lock, flags);
920 if (new_areq)
921 ret = crypto_enqueue_request(&dd->queue, new_areq);
922 if (dd->flags & AES_FLAGS_BUSY) {
923 spin_unlock_irqrestore(&dd->lock, flags);
924 return ret;
925 }
926 backlog = crypto_get_backlog(&dd->queue);
927 areq = crypto_dequeue_request(&dd->queue);
928 if (areq)
929 dd->flags |= AES_FLAGS_BUSY;
930 spin_unlock_irqrestore(&dd->lock, flags);
931
932 if (!areq)
933 return ret;
934
935 if (backlog)
936 backlog->complete(backlog, -EINPROGRESS);
937
938 ctx = crypto_tfm_ctx(areq->tfm);
939
940 dd->areq = areq;
941 dd->ctx = ctx;
942 start_async = (areq != new_areq);
943 dd->is_async = start_async;
944
945 /* WARNING: ctx->start() MAY change dd->is_async. */
946 err = ctx->start(dd);
947 return (start_async) ? ret : err;
948 }
949
950
951 /* AES async block ciphers */
952
atmel_aes_transfer_complete(struct atmel_aes_dev * dd)953 static int atmel_aes_transfer_complete(struct atmel_aes_dev *dd)
954 {
955 return atmel_aes_complete(dd, 0);
956 }
957
atmel_aes_start(struct atmel_aes_dev * dd)958 static int atmel_aes_start(struct atmel_aes_dev *dd)
959 {
960 struct ablkcipher_request *req = ablkcipher_request_cast(dd->areq);
961 struct atmel_aes_reqctx *rctx = ablkcipher_request_ctx(req);
962 bool use_dma = (req->nbytes >= ATMEL_AES_DMA_THRESHOLD ||
963 dd->ctx->block_size != AES_BLOCK_SIZE);
964 int err;
965
966 atmel_aes_set_mode(dd, rctx);
967
968 err = atmel_aes_hw_init(dd);
969 if (err)
970 return atmel_aes_complete(dd, err);
971
972 atmel_aes_write_ctrl(dd, use_dma, req->info);
973 if (use_dma)
974 return atmel_aes_dma_start(dd, req->src, req->dst, req->nbytes,
975 atmel_aes_transfer_complete);
976
977 return atmel_aes_cpu_start(dd, req->src, req->dst, req->nbytes,
978 atmel_aes_transfer_complete);
979 }
980
981 static inline struct atmel_aes_ctr_ctx *
atmel_aes_ctr_ctx_cast(struct atmel_aes_base_ctx * ctx)982 atmel_aes_ctr_ctx_cast(struct atmel_aes_base_ctx *ctx)
983 {
984 return container_of(ctx, struct atmel_aes_ctr_ctx, base);
985 }
986
atmel_aes_ctr_transfer(struct atmel_aes_dev * dd)987 static int atmel_aes_ctr_transfer(struct atmel_aes_dev *dd)
988 {
989 struct atmel_aes_ctr_ctx *ctx = atmel_aes_ctr_ctx_cast(dd->ctx);
990 struct ablkcipher_request *req = ablkcipher_request_cast(dd->areq);
991 struct scatterlist *src, *dst;
992 size_t datalen;
993 u32 ctr;
994 u16 blocks, start, end;
995 bool use_dma, fragmented = false;
996
997 /* Check for transfer completion. */
998 ctx->offset += dd->total;
999 if (ctx->offset >= req->nbytes)
1000 return atmel_aes_transfer_complete(dd);
1001
1002 /* Compute data length. */
1003 datalen = req->nbytes - ctx->offset;
1004 blocks = DIV_ROUND_UP(datalen, AES_BLOCK_SIZE);
1005 ctr = be32_to_cpu(ctx->iv[3]);
1006
1007 /* Check 16bit counter overflow. */
1008 start = ctr & 0xffff;
1009 end = start + blocks - 1;
1010
1011 if (blocks >> 16 || end < start) {
1012 ctr |= 0xffff;
1013 datalen = AES_BLOCK_SIZE * (0x10000 - start);
1014 fragmented = true;
1015 }
1016
1017 use_dma = (datalen >= ATMEL_AES_DMA_THRESHOLD);
1018
1019 /* Jump to offset. */
1020 src = scatterwalk_ffwd(ctx->src, req->src, ctx->offset);
1021 dst = ((req->src == req->dst) ? src :
1022 scatterwalk_ffwd(ctx->dst, req->dst, ctx->offset));
1023
1024 /* Configure hardware. */
1025 atmel_aes_write_ctrl(dd, use_dma, ctx->iv);
1026 if (unlikely(fragmented)) {
1027 /*
1028 * Increment the counter manually to cope with the hardware
1029 * counter overflow.
1030 */
1031 ctx->iv[3] = cpu_to_be32(ctr);
1032 crypto_inc((u8 *)ctx->iv, AES_BLOCK_SIZE);
1033 }
1034
1035 if (use_dma)
1036 return atmel_aes_dma_start(dd, src, dst, datalen,
1037 atmel_aes_ctr_transfer);
1038
1039 return atmel_aes_cpu_start(dd, src, dst, datalen,
1040 atmel_aes_ctr_transfer);
1041 }
1042
atmel_aes_ctr_start(struct atmel_aes_dev * dd)1043 static int atmel_aes_ctr_start(struct atmel_aes_dev *dd)
1044 {
1045 struct atmel_aes_ctr_ctx *ctx = atmel_aes_ctr_ctx_cast(dd->ctx);
1046 struct ablkcipher_request *req = ablkcipher_request_cast(dd->areq);
1047 struct atmel_aes_reqctx *rctx = ablkcipher_request_ctx(req);
1048 int err;
1049
1050 atmel_aes_set_mode(dd, rctx);
1051
1052 err = atmel_aes_hw_init(dd);
1053 if (err)
1054 return atmel_aes_complete(dd, err);
1055
1056 memcpy(ctx->iv, req->info, AES_BLOCK_SIZE);
1057 ctx->offset = 0;
1058 dd->total = 0;
1059 return atmel_aes_ctr_transfer(dd);
1060 }
1061
atmel_aes_crypt(struct ablkcipher_request * req,unsigned long mode)1062 static int atmel_aes_crypt(struct ablkcipher_request *req, unsigned long mode)
1063 {
1064 struct atmel_aes_base_ctx *ctx;
1065 struct atmel_aes_reqctx *rctx;
1066 struct atmel_aes_dev *dd;
1067
1068 ctx = crypto_ablkcipher_ctx(crypto_ablkcipher_reqtfm(req));
1069 switch (mode & AES_FLAGS_OPMODE_MASK) {
1070 case AES_FLAGS_CFB8:
1071 ctx->block_size = CFB8_BLOCK_SIZE;
1072 break;
1073
1074 case AES_FLAGS_CFB16:
1075 ctx->block_size = CFB16_BLOCK_SIZE;
1076 break;
1077
1078 case AES_FLAGS_CFB32:
1079 ctx->block_size = CFB32_BLOCK_SIZE;
1080 break;
1081
1082 case AES_FLAGS_CFB64:
1083 ctx->block_size = CFB64_BLOCK_SIZE;
1084 break;
1085
1086 default:
1087 ctx->block_size = AES_BLOCK_SIZE;
1088 break;
1089 }
1090
1091 dd = atmel_aes_find_dev(ctx);
1092 if (!dd)
1093 return -ENODEV;
1094
1095 rctx = ablkcipher_request_ctx(req);
1096 rctx->mode = mode;
1097
1098 return atmel_aes_handle_queue(dd, &req->base);
1099 }
1100
atmel_aes_setkey(struct crypto_ablkcipher * tfm,const u8 * key,unsigned int keylen)1101 static int atmel_aes_setkey(struct crypto_ablkcipher *tfm, const u8 *key,
1102 unsigned int keylen)
1103 {
1104 struct atmel_aes_base_ctx *ctx = crypto_ablkcipher_ctx(tfm);
1105
1106 if (keylen != AES_KEYSIZE_128 &&
1107 keylen != AES_KEYSIZE_192 &&
1108 keylen != AES_KEYSIZE_256) {
1109 crypto_ablkcipher_set_flags(tfm, CRYPTO_TFM_RES_BAD_KEY_LEN);
1110 return -EINVAL;
1111 }
1112
1113 memcpy(ctx->key, key, keylen);
1114 ctx->keylen = keylen;
1115
1116 return 0;
1117 }
1118
atmel_aes_ecb_encrypt(struct ablkcipher_request * req)1119 static int atmel_aes_ecb_encrypt(struct ablkcipher_request *req)
1120 {
1121 return atmel_aes_crypt(req, AES_FLAGS_ECB | AES_FLAGS_ENCRYPT);
1122 }
1123
atmel_aes_ecb_decrypt(struct ablkcipher_request * req)1124 static int atmel_aes_ecb_decrypt(struct ablkcipher_request *req)
1125 {
1126 return atmel_aes_crypt(req, AES_FLAGS_ECB);
1127 }
1128
atmel_aes_cbc_encrypt(struct ablkcipher_request * req)1129 static int atmel_aes_cbc_encrypt(struct ablkcipher_request *req)
1130 {
1131 return atmel_aes_crypt(req, AES_FLAGS_CBC | AES_FLAGS_ENCRYPT);
1132 }
1133
atmel_aes_cbc_decrypt(struct ablkcipher_request * req)1134 static int atmel_aes_cbc_decrypt(struct ablkcipher_request *req)
1135 {
1136 return atmel_aes_crypt(req, AES_FLAGS_CBC);
1137 }
1138
atmel_aes_ofb_encrypt(struct ablkcipher_request * req)1139 static int atmel_aes_ofb_encrypt(struct ablkcipher_request *req)
1140 {
1141 return atmel_aes_crypt(req, AES_FLAGS_OFB | AES_FLAGS_ENCRYPT);
1142 }
1143
atmel_aes_ofb_decrypt(struct ablkcipher_request * req)1144 static int atmel_aes_ofb_decrypt(struct ablkcipher_request *req)
1145 {
1146 return atmel_aes_crypt(req, AES_FLAGS_OFB);
1147 }
1148
atmel_aes_cfb_encrypt(struct ablkcipher_request * req)1149 static int atmel_aes_cfb_encrypt(struct ablkcipher_request *req)
1150 {
1151 return atmel_aes_crypt(req, AES_FLAGS_CFB128 | AES_FLAGS_ENCRYPT);
1152 }
1153
atmel_aes_cfb_decrypt(struct ablkcipher_request * req)1154 static int atmel_aes_cfb_decrypt(struct ablkcipher_request *req)
1155 {
1156 return atmel_aes_crypt(req, AES_FLAGS_CFB128);
1157 }
1158
atmel_aes_cfb64_encrypt(struct ablkcipher_request * req)1159 static int atmel_aes_cfb64_encrypt(struct ablkcipher_request *req)
1160 {
1161 return atmel_aes_crypt(req, AES_FLAGS_CFB64 | AES_FLAGS_ENCRYPT);
1162 }
1163
atmel_aes_cfb64_decrypt(struct ablkcipher_request * req)1164 static int atmel_aes_cfb64_decrypt(struct ablkcipher_request *req)
1165 {
1166 return atmel_aes_crypt(req, AES_FLAGS_CFB64);
1167 }
1168
atmel_aes_cfb32_encrypt(struct ablkcipher_request * req)1169 static int atmel_aes_cfb32_encrypt(struct ablkcipher_request *req)
1170 {
1171 return atmel_aes_crypt(req, AES_FLAGS_CFB32 | AES_FLAGS_ENCRYPT);
1172 }
1173
atmel_aes_cfb32_decrypt(struct ablkcipher_request * req)1174 static int atmel_aes_cfb32_decrypt(struct ablkcipher_request *req)
1175 {
1176 return atmel_aes_crypt(req, AES_FLAGS_CFB32);
1177 }
1178
atmel_aes_cfb16_encrypt(struct ablkcipher_request * req)1179 static int atmel_aes_cfb16_encrypt(struct ablkcipher_request *req)
1180 {
1181 return atmel_aes_crypt(req, AES_FLAGS_CFB16 | AES_FLAGS_ENCRYPT);
1182 }
1183
atmel_aes_cfb16_decrypt(struct ablkcipher_request * req)1184 static int atmel_aes_cfb16_decrypt(struct ablkcipher_request *req)
1185 {
1186 return atmel_aes_crypt(req, AES_FLAGS_CFB16);
1187 }
1188
atmel_aes_cfb8_encrypt(struct ablkcipher_request * req)1189 static int atmel_aes_cfb8_encrypt(struct ablkcipher_request *req)
1190 {
1191 return atmel_aes_crypt(req, AES_FLAGS_CFB8 | AES_FLAGS_ENCRYPT);
1192 }
1193
atmel_aes_cfb8_decrypt(struct ablkcipher_request * req)1194 static int atmel_aes_cfb8_decrypt(struct ablkcipher_request *req)
1195 {
1196 return atmel_aes_crypt(req, AES_FLAGS_CFB8);
1197 }
1198
atmel_aes_ctr_encrypt(struct ablkcipher_request * req)1199 static int atmel_aes_ctr_encrypt(struct ablkcipher_request *req)
1200 {
1201 return atmel_aes_crypt(req, AES_FLAGS_CTR | AES_FLAGS_ENCRYPT);
1202 }
1203
atmel_aes_ctr_decrypt(struct ablkcipher_request * req)1204 static int atmel_aes_ctr_decrypt(struct ablkcipher_request *req)
1205 {
1206 return atmel_aes_crypt(req, AES_FLAGS_CTR);
1207 }
1208
atmel_aes_cra_init(struct crypto_tfm * tfm)1209 static int atmel_aes_cra_init(struct crypto_tfm *tfm)
1210 {
1211 struct atmel_aes_ctx *ctx = crypto_tfm_ctx(tfm);
1212
1213 tfm->crt_ablkcipher.reqsize = sizeof(struct atmel_aes_reqctx);
1214 ctx->base.start = atmel_aes_start;
1215
1216 return 0;
1217 }
1218
atmel_aes_ctr_cra_init(struct crypto_tfm * tfm)1219 static int atmel_aes_ctr_cra_init(struct crypto_tfm *tfm)
1220 {
1221 struct atmel_aes_ctx *ctx = crypto_tfm_ctx(tfm);
1222
1223 tfm->crt_ablkcipher.reqsize = sizeof(struct atmel_aes_reqctx);
1224 ctx->base.start = atmel_aes_ctr_start;
1225
1226 return 0;
1227 }
1228
atmel_aes_cra_exit(struct crypto_tfm * tfm)1229 static void atmel_aes_cra_exit(struct crypto_tfm *tfm)
1230 {
1231 }
1232
1233 static struct crypto_alg aes_algs[] = {
1234 {
1235 .cra_name = "ecb(aes)",
1236 .cra_driver_name = "atmel-ecb-aes",
1237 .cra_priority = ATMEL_AES_PRIORITY,
1238 .cra_flags = CRYPTO_ALG_TYPE_ABLKCIPHER | CRYPTO_ALG_ASYNC,
1239 .cra_blocksize = AES_BLOCK_SIZE,
1240 .cra_ctxsize = sizeof(struct atmel_aes_ctx),
1241 .cra_alignmask = 0xf,
1242 .cra_type = &crypto_ablkcipher_type,
1243 .cra_module = THIS_MODULE,
1244 .cra_init = atmel_aes_cra_init,
1245 .cra_exit = atmel_aes_cra_exit,
1246 .cra_u.ablkcipher = {
1247 .min_keysize = AES_MIN_KEY_SIZE,
1248 .max_keysize = AES_MAX_KEY_SIZE,
1249 .setkey = atmel_aes_setkey,
1250 .encrypt = atmel_aes_ecb_encrypt,
1251 .decrypt = atmel_aes_ecb_decrypt,
1252 }
1253 },
1254 {
1255 .cra_name = "cbc(aes)",
1256 .cra_driver_name = "atmel-cbc-aes",
1257 .cra_priority = ATMEL_AES_PRIORITY,
1258 .cra_flags = CRYPTO_ALG_TYPE_ABLKCIPHER | CRYPTO_ALG_ASYNC,
1259 .cra_blocksize = AES_BLOCK_SIZE,
1260 .cra_ctxsize = sizeof(struct atmel_aes_ctx),
1261 .cra_alignmask = 0xf,
1262 .cra_type = &crypto_ablkcipher_type,
1263 .cra_module = THIS_MODULE,
1264 .cra_init = atmel_aes_cra_init,
1265 .cra_exit = atmel_aes_cra_exit,
1266 .cra_u.ablkcipher = {
1267 .min_keysize = AES_MIN_KEY_SIZE,
1268 .max_keysize = AES_MAX_KEY_SIZE,
1269 .ivsize = AES_BLOCK_SIZE,
1270 .setkey = atmel_aes_setkey,
1271 .encrypt = atmel_aes_cbc_encrypt,
1272 .decrypt = atmel_aes_cbc_decrypt,
1273 }
1274 },
1275 {
1276 .cra_name = "ofb(aes)",
1277 .cra_driver_name = "atmel-ofb-aes",
1278 .cra_priority = ATMEL_AES_PRIORITY,
1279 .cra_flags = CRYPTO_ALG_TYPE_ABLKCIPHER | CRYPTO_ALG_ASYNC,
1280 .cra_blocksize = AES_BLOCK_SIZE,
1281 .cra_ctxsize = sizeof(struct atmel_aes_ctx),
1282 .cra_alignmask = 0xf,
1283 .cra_type = &crypto_ablkcipher_type,
1284 .cra_module = THIS_MODULE,
1285 .cra_init = atmel_aes_cra_init,
1286 .cra_exit = atmel_aes_cra_exit,
1287 .cra_u.ablkcipher = {
1288 .min_keysize = AES_MIN_KEY_SIZE,
1289 .max_keysize = AES_MAX_KEY_SIZE,
1290 .ivsize = AES_BLOCK_SIZE,
1291 .setkey = atmel_aes_setkey,
1292 .encrypt = atmel_aes_ofb_encrypt,
1293 .decrypt = atmel_aes_ofb_decrypt,
1294 }
1295 },
1296 {
1297 .cra_name = "cfb(aes)",
1298 .cra_driver_name = "atmel-cfb-aes",
1299 .cra_priority = ATMEL_AES_PRIORITY,
1300 .cra_flags = CRYPTO_ALG_TYPE_ABLKCIPHER | CRYPTO_ALG_ASYNC,
1301 .cra_blocksize = AES_BLOCK_SIZE,
1302 .cra_ctxsize = sizeof(struct atmel_aes_ctx),
1303 .cra_alignmask = 0xf,
1304 .cra_type = &crypto_ablkcipher_type,
1305 .cra_module = THIS_MODULE,
1306 .cra_init = atmel_aes_cra_init,
1307 .cra_exit = atmel_aes_cra_exit,
1308 .cra_u.ablkcipher = {
1309 .min_keysize = AES_MIN_KEY_SIZE,
1310 .max_keysize = AES_MAX_KEY_SIZE,
1311 .ivsize = AES_BLOCK_SIZE,
1312 .setkey = atmel_aes_setkey,
1313 .encrypt = atmel_aes_cfb_encrypt,
1314 .decrypt = atmel_aes_cfb_decrypt,
1315 }
1316 },
1317 {
1318 .cra_name = "cfb32(aes)",
1319 .cra_driver_name = "atmel-cfb32-aes",
1320 .cra_priority = ATMEL_AES_PRIORITY,
1321 .cra_flags = CRYPTO_ALG_TYPE_ABLKCIPHER | CRYPTO_ALG_ASYNC,
1322 .cra_blocksize = CFB32_BLOCK_SIZE,
1323 .cra_ctxsize = sizeof(struct atmel_aes_ctx),
1324 .cra_alignmask = 0x3,
1325 .cra_type = &crypto_ablkcipher_type,
1326 .cra_module = THIS_MODULE,
1327 .cra_init = atmel_aes_cra_init,
1328 .cra_exit = atmel_aes_cra_exit,
1329 .cra_u.ablkcipher = {
1330 .min_keysize = AES_MIN_KEY_SIZE,
1331 .max_keysize = AES_MAX_KEY_SIZE,
1332 .ivsize = AES_BLOCK_SIZE,
1333 .setkey = atmel_aes_setkey,
1334 .encrypt = atmel_aes_cfb32_encrypt,
1335 .decrypt = atmel_aes_cfb32_decrypt,
1336 }
1337 },
1338 {
1339 .cra_name = "cfb16(aes)",
1340 .cra_driver_name = "atmel-cfb16-aes",
1341 .cra_priority = ATMEL_AES_PRIORITY,
1342 .cra_flags = CRYPTO_ALG_TYPE_ABLKCIPHER | CRYPTO_ALG_ASYNC,
1343 .cra_blocksize = CFB16_BLOCK_SIZE,
1344 .cra_ctxsize = sizeof(struct atmel_aes_ctx),
1345 .cra_alignmask = 0x1,
1346 .cra_type = &crypto_ablkcipher_type,
1347 .cra_module = THIS_MODULE,
1348 .cra_init = atmel_aes_cra_init,
1349 .cra_exit = atmel_aes_cra_exit,
1350 .cra_u.ablkcipher = {
1351 .min_keysize = AES_MIN_KEY_SIZE,
1352 .max_keysize = AES_MAX_KEY_SIZE,
1353 .ivsize = AES_BLOCK_SIZE,
1354 .setkey = atmel_aes_setkey,
1355 .encrypt = atmel_aes_cfb16_encrypt,
1356 .decrypt = atmel_aes_cfb16_decrypt,
1357 }
1358 },
1359 {
1360 .cra_name = "cfb8(aes)",
1361 .cra_driver_name = "atmel-cfb8-aes",
1362 .cra_priority = ATMEL_AES_PRIORITY,
1363 .cra_flags = CRYPTO_ALG_TYPE_ABLKCIPHER | CRYPTO_ALG_ASYNC,
1364 .cra_blocksize = CFB8_BLOCK_SIZE,
1365 .cra_ctxsize = sizeof(struct atmel_aes_ctx),
1366 .cra_alignmask = 0x0,
1367 .cra_type = &crypto_ablkcipher_type,
1368 .cra_module = THIS_MODULE,
1369 .cra_init = atmel_aes_cra_init,
1370 .cra_exit = atmel_aes_cra_exit,
1371 .cra_u.ablkcipher = {
1372 .min_keysize = AES_MIN_KEY_SIZE,
1373 .max_keysize = AES_MAX_KEY_SIZE,
1374 .ivsize = AES_BLOCK_SIZE,
1375 .setkey = atmel_aes_setkey,
1376 .encrypt = atmel_aes_cfb8_encrypt,
1377 .decrypt = atmel_aes_cfb8_decrypt,
1378 }
1379 },
1380 {
1381 .cra_name = "ctr(aes)",
1382 .cra_driver_name = "atmel-ctr-aes",
1383 .cra_priority = ATMEL_AES_PRIORITY,
1384 .cra_flags = CRYPTO_ALG_TYPE_ABLKCIPHER | CRYPTO_ALG_ASYNC,
1385 .cra_blocksize = 1,
1386 .cra_ctxsize = sizeof(struct atmel_aes_ctr_ctx),
1387 .cra_alignmask = 0xf,
1388 .cra_type = &crypto_ablkcipher_type,
1389 .cra_module = THIS_MODULE,
1390 .cra_init = atmel_aes_ctr_cra_init,
1391 .cra_exit = atmel_aes_cra_exit,
1392 .cra_u.ablkcipher = {
1393 .min_keysize = AES_MIN_KEY_SIZE,
1394 .max_keysize = AES_MAX_KEY_SIZE,
1395 .ivsize = AES_BLOCK_SIZE,
1396 .setkey = atmel_aes_setkey,
1397 .encrypt = atmel_aes_ctr_encrypt,
1398 .decrypt = atmel_aes_ctr_decrypt,
1399 }
1400 },
1401 };
1402
1403 static struct crypto_alg aes_cfb64_alg = {
1404 .cra_name = "cfb64(aes)",
1405 .cra_driver_name = "atmel-cfb64-aes",
1406 .cra_priority = ATMEL_AES_PRIORITY,
1407 .cra_flags = CRYPTO_ALG_TYPE_ABLKCIPHER | CRYPTO_ALG_ASYNC,
1408 .cra_blocksize = CFB64_BLOCK_SIZE,
1409 .cra_ctxsize = sizeof(struct atmel_aes_ctx),
1410 .cra_alignmask = 0x7,
1411 .cra_type = &crypto_ablkcipher_type,
1412 .cra_module = THIS_MODULE,
1413 .cra_init = atmel_aes_cra_init,
1414 .cra_exit = atmel_aes_cra_exit,
1415 .cra_u.ablkcipher = {
1416 .min_keysize = AES_MIN_KEY_SIZE,
1417 .max_keysize = AES_MAX_KEY_SIZE,
1418 .ivsize = AES_BLOCK_SIZE,
1419 .setkey = atmel_aes_setkey,
1420 .encrypt = atmel_aes_cfb64_encrypt,
1421 .decrypt = atmel_aes_cfb64_decrypt,
1422 }
1423 };
1424
1425
1426 /* gcm aead functions */
1427
1428 static int atmel_aes_gcm_ghash(struct atmel_aes_dev *dd,
1429 const u32 *data, size_t datalen,
1430 const u32 *ghash_in, u32 *ghash_out,
1431 atmel_aes_fn_t resume);
1432 static int atmel_aes_gcm_ghash_init(struct atmel_aes_dev *dd);
1433 static int atmel_aes_gcm_ghash_finalize(struct atmel_aes_dev *dd);
1434
1435 static int atmel_aes_gcm_start(struct atmel_aes_dev *dd);
1436 static int atmel_aes_gcm_process(struct atmel_aes_dev *dd);
1437 static int atmel_aes_gcm_length(struct atmel_aes_dev *dd);
1438 static int atmel_aes_gcm_data(struct atmel_aes_dev *dd);
1439 static int atmel_aes_gcm_tag_init(struct atmel_aes_dev *dd);
1440 static int atmel_aes_gcm_tag(struct atmel_aes_dev *dd);
1441 static int atmel_aes_gcm_finalize(struct atmel_aes_dev *dd);
1442
1443 static inline struct atmel_aes_gcm_ctx *
atmel_aes_gcm_ctx_cast(struct atmel_aes_base_ctx * ctx)1444 atmel_aes_gcm_ctx_cast(struct atmel_aes_base_ctx *ctx)
1445 {
1446 return container_of(ctx, struct atmel_aes_gcm_ctx, base);
1447 }
1448
atmel_aes_gcm_ghash(struct atmel_aes_dev * dd,const u32 * data,size_t datalen,const u32 * ghash_in,u32 * ghash_out,atmel_aes_fn_t resume)1449 static int atmel_aes_gcm_ghash(struct atmel_aes_dev *dd,
1450 const u32 *data, size_t datalen,
1451 const u32 *ghash_in, u32 *ghash_out,
1452 atmel_aes_fn_t resume)
1453 {
1454 struct atmel_aes_gcm_ctx *ctx = atmel_aes_gcm_ctx_cast(dd->ctx);
1455
1456 dd->data = (u32 *)data;
1457 dd->datalen = datalen;
1458 ctx->ghash_in = ghash_in;
1459 ctx->ghash_out = ghash_out;
1460 ctx->ghash_resume = resume;
1461
1462 atmel_aes_write_ctrl(dd, false, NULL);
1463 return atmel_aes_wait_for_data_ready(dd, atmel_aes_gcm_ghash_init);
1464 }
1465
atmel_aes_gcm_ghash_init(struct atmel_aes_dev * dd)1466 static int atmel_aes_gcm_ghash_init(struct atmel_aes_dev *dd)
1467 {
1468 struct atmel_aes_gcm_ctx *ctx = atmel_aes_gcm_ctx_cast(dd->ctx);
1469
1470 /* Set the data length. */
1471 atmel_aes_write(dd, AES_AADLENR, dd->total);
1472 atmel_aes_write(dd, AES_CLENR, 0);
1473
1474 /* If needed, overwrite the GCM Intermediate Hash Word Registers */
1475 if (ctx->ghash_in)
1476 atmel_aes_write_block(dd, AES_GHASHR(0), ctx->ghash_in);
1477
1478 return atmel_aes_gcm_ghash_finalize(dd);
1479 }
1480
atmel_aes_gcm_ghash_finalize(struct atmel_aes_dev * dd)1481 static int atmel_aes_gcm_ghash_finalize(struct atmel_aes_dev *dd)
1482 {
1483 struct atmel_aes_gcm_ctx *ctx = atmel_aes_gcm_ctx_cast(dd->ctx);
1484 u32 isr;
1485
1486 /* Write data into the Input Data Registers. */
1487 while (dd->datalen > 0) {
1488 atmel_aes_write_block(dd, AES_IDATAR(0), dd->data);
1489 dd->data += 4;
1490 dd->datalen -= AES_BLOCK_SIZE;
1491
1492 isr = atmel_aes_read(dd, AES_ISR);
1493 if (!(isr & AES_INT_DATARDY)) {
1494 dd->resume = atmel_aes_gcm_ghash_finalize;
1495 atmel_aes_write(dd, AES_IER, AES_INT_DATARDY);
1496 return -EINPROGRESS;
1497 }
1498 }
1499
1500 /* Read the computed hash from GHASHRx. */
1501 atmel_aes_read_block(dd, AES_GHASHR(0), ctx->ghash_out);
1502
1503 return ctx->ghash_resume(dd);
1504 }
1505
1506
atmel_aes_gcm_start(struct atmel_aes_dev * dd)1507 static int atmel_aes_gcm_start(struct atmel_aes_dev *dd)
1508 {
1509 struct atmel_aes_gcm_ctx *ctx = atmel_aes_gcm_ctx_cast(dd->ctx);
1510 struct aead_request *req = aead_request_cast(dd->areq);
1511 struct crypto_aead *tfm = crypto_aead_reqtfm(req);
1512 struct atmel_aes_reqctx *rctx = aead_request_ctx(req);
1513 size_t ivsize = crypto_aead_ivsize(tfm);
1514 size_t datalen, padlen;
1515 const void *iv = req->iv;
1516 u8 *data = dd->buf;
1517 int err;
1518
1519 atmel_aes_set_mode(dd, rctx);
1520
1521 err = atmel_aes_hw_init(dd);
1522 if (err)
1523 return atmel_aes_complete(dd, err);
1524
1525 if (likely(ivsize == 12)) {
1526 memcpy(ctx->j0, iv, ivsize);
1527 ctx->j0[3] = cpu_to_be32(1);
1528 return atmel_aes_gcm_process(dd);
1529 }
1530
1531 padlen = atmel_aes_padlen(ivsize, AES_BLOCK_SIZE);
1532 datalen = ivsize + padlen + AES_BLOCK_SIZE;
1533 if (datalen > dd->buflen)
1534 return atmel_aes_complete(dd, -EINVAL);
1535
1536 memcpy(data, iv, ivsize);
1537 memset(data + ivsize, 0, padlen + sizeof(u64));
1538 ((u64 *)(data + datalen))[-1] = cpu_to_be64(ivsize * 8);
1539
1540 return atmel_aes_gcm_ghash(dd, (const u32 *)data, datalen,
1541 NULL, ctx->j0, atmel_aes_gcm_process);
1542 }
1543
atmel_aes_gcm_process(struct atmel_aes_dev * dd)1544 static int atmel_aes_gcm_process(struct atmel_aes_dev *dd)
1545 {
1546 struct atmel_aes_gcm_ctx *ctx = atmel_aes_gcm_ctx_cast(dd->ctx);
1547 struct aead_request *req = aead_request_cast(dd->areq);
1548 struct crypto_aead *tfm = crypto_aead_reqtfm(req);
1549 bool enc = atmel_aes_is_encrypt(dd);
1550 u32 authsize;
1551
1552 /* Compute text length. */
1553 authsize = crypto_aead_authsize(tfm);
1554 ctx->textlen = req->cryptlen - (enc ? 0 : authsize);
1555
1556 /*
1557 * According to tcrypt test suite, the GCM Automatic Tag Generation
1558 * fails when both the message and its associated data are empty.
1559 */
1560 if (likely(req->assoclen != 0 || ctx->textlen != 0))
1561 dd->flags |= AES_FLAGS_GTAGEN;
1562
1563 atmel_aes_write_ctrl(dd, false, NULL);
1564 return atmel_aes_wait_for_data_ready(dd, atmel_aes_gcm_length);
1565 }
1566
atmel_aes_gcm_length(struct atmel_aes_dev * dd)1567 static int atmel_aes_gcm_length(struct atmel_aes_dev *dd)
1568 {
1569 struct atmel_aes_gcm_ctx *ctx = atmel_aes_gcm_ctx_cast(dd->ctx);
1570 struct aead_request *req = aead_request_cast(dd->areq);
1571 u32 j0_lsw, *j0 = ctx->j0;
1572 size_t padlen;
1573
1574 /* Write incr32(J0) into IV. */
1575 j0_lsw = j0[3];
1576 j0[3] = cpu_to_be32(be32_to_cpu(j0[3]) + 1);
1577 atmel_aes_write_block(dd, AES_IVR(0), j0);
1578 j0[3] = j0_lsw;
1579
1580 /* Set aad and text lengths. */
1581 atmel_aes_write(dd, AES_AADLENR, req->assoclen);
1582 atmel_aes_write(dd, AES_CLENR, ctx->textlen);
1583
1584 /* Check whether AAD are present. */
1585 if (unlikely(req->assoclen == 0)) {
1586 dd->datalen = 0;
1587 return atmel_aes_gcm_data(dd);
1588 }
1589
1590 /* Copy assoc data and add padding. */
1591 padlen = atmel_aes_padlen(req->assoclen, AES_BLOCK_SIZE);
1592 if (unlikely(req->assoclen + padlen > dd->buflen))
1593 return atmel_aes_complete(dd, -EINVAL);
1594 sg_copy_to_buffer(req->src, sg_nents(req->src), dd->buf, req->assoclen);
1595
1596 /* Write assoc data into the Input Data register. */
1597 dd->data = (u32 *)dd->buf;
1598 dd->datalen = req->assoclen + padlen;
1599 return atmel_aes_gcm_data(dd);
1600 }
1601
atmel_aes_gcm_data(struct atmel_aes_dev * dd)1602 static int atmel_aes_gcm_data(struct atmel_aes_dev *dd)
1603 {
1604 struct atmel_aes_gcm_ctx *ctx = atmel_aes_gcm_ctx_cast(dd->ctx);
1605 struct aead_request *req = aead_request_cast(dd->areq);
1606 bool use_dma = (ctx->textlen >= ATMEL_AES_DMA_THRESHOLD);
1607 struct scatterlist *src, *dst;
1608 u32 isr, mr;
1609
1610 /* Write AAD first. */
1611 while (dd->datalen > 0) {
1612 atmel_aes_write_block(dd, AES_IDATAR(0), dd->data);
1613 dd->data += 4;
1614 dd->datalen -= AES_BLOCK_SIZE;
1615
1616 isr = atmel_aes_read(dd, AES_ISR);
1617 if (!(isr & AES_INT_DATARDY)) {
1618 dd->resume = atmel_aes_gcm_data;
1619 atmel_aes_write(dd, AES_IER, AES_INT_DATARDY);
1620 return -EINPROGRESS;
1621 }
1622 }
1623
1624 /* GMAC only. */
1625 if (unlikely(ctx->textlen == 0))
1626 return atmel_aes_gcm_tag_init(dd);
1627
1628 /* Prepare src and dst scatter lists to transfer cipher/plain texts */
1629 src = scatterwalk_ffwd(ctx->src, req->src, req->assoclen);
1630 dst = ((req->src == req->dst) ? src :
1631 scatterwalk_ffwd(ctx->dst, req->dst, req->assoclen));
1632
1633 if (use_dma) {
1634 /* Update the Mode Register for DMA transfers. */
1635 mr = atmel_aes_read(dd, AES_MR);
1636 mr &= ~(AES_MR_SMOD_MASK | AES_MR_DUALBUFF);
1637 mr |= AES_MR_SMOD_IDATAR0;
1638 if (dd->caps.has_dualbuff)
1639 mr |= AES_MR_DUALBUFF;
1640 atmel_aes_write(dd, AES_MR, mr);
1641
1642 return atmel_aes_dma_start(dd, src, dst, ctx->textlen,
1643 atmel_aes_gcm_tag_init);
1644 }
1645
1646 return atmel_aes_cpu_start(dd, src, dst, ctx->textlen,
1647 atmel_aes_gcm_tag_init);
1648 }
1649
atmel_aes_gcm_tag_init(struct atmel_aes_dev * dd)1650 static int atmel_aes_gcm_tag_init(struct atmel_aes_dev *dd)
1651 {
1652 struct atmel_aes_gcm_ctx *ctx = atmel_aes_gcm_ctx_cast(dd->ctx);
1653 struct aead_request *req = aead_request_cast(dd->areq);
1654 u64 *data = dd->buf;
1655
1656 if (likely(dd->flags & AES_FLAGS_GTAGEN)) {
1657 if (!(atmel_aes_read(dd, AES_ISR) & AES_INT_TAGRDY)) {
1658 dd->resume = atmel_aes_gcm_tag_init;
1659 atmel_aes_write(dd, AES_IER, AES_INT_TAGRDY);
1660 return -EINPROGRESS;
1661 }
1662
1663 return atmel_aes_gcm_finalize(dd);
1664 }
1665
1666 /* Read the GCM Intermediate Hash Word Registers. */
1667 atmel_aes_read_block(dd, AES_GHASHR(0), ctx->ghash);
1668
1669 data[0] = cpu_to_be64(req->assoclen * 8);
1670 data[1] = cpu_to_be64(ctx->textlen * 8);
1671
1672 return atmel_aes_gcm_ghash(dd, (const u32 *)data, AES_BLOCK_SIZE,
1673 ctx->ghash, ctx->ghash, atmel_aes_gcm_tag);
1674 }
1675
atmel_aes_gcm_tag(struct atmel_aes_dev * dd)1676 static int atmel_aes_gcm_tag(struct atmel_aes_dev *dd)
1677 {
1678 struct atmel_aes_gcm_ctx *ctx = atmel_aes_gcm_ctx_cast(dd->ctx);
1679 unsigned long flags;
1680
1681 /*
1682 * Change mode to CTR to complete the tag generation.
1683 * Use J0 as Initialization Vector.
1684 */
1685 flags = dd->flags;
1686 dd->flags &= ~(AES_FLAGS_OPMODE_MASK | AES_FLAGS_GTAGEN);
1687 dd->flags |= AES_FLAGS_CTR;
1688 atmel_aes_write_ctrl(dd, false, ctx->j0);
1689 dd->flags = flags;
1690
1691 atmel_aes_write_block(dd, AES_IDATAR(0), ctx->ghash);
1692 return atmel_aes_wait_for_data_ready(dd, atmel_aes_gcm_finalize);
1693 }
1694
atmel_aes_gcm_finalize(struct atmel_aes_dev * dd)1695 static int atmel_aes_gcm_finalize(struct atmel_aes_dev *dd)
1696 {
1697 struct atmel_aes_gcm_ctx *ctx = atmel_aes_gcm_ctx_cast(dd->ctx);
1698 struct aead_request *req = aead_request_cast(dd->areq);
1699 struct crypto_aead *tfm = crypto_aead_reqtfm(req);
1700 bool enc = atmel_aes_is_encrypt(dd);
1701 u32 offset, authsize, itag[4], *otag = ctx->tag;
1702 int err;
1703
1704 /* Read the computed tag. */
1705 if (likely(dd->flags & AES_FLAGS_GTAGEN))
1706 atmel_aes_read_block(dd, AES_TAGR(0), ctx->tag);
1707 else
1708 atmel_aes_read_block(dd, AES_ODATAR(0), ctx->tag);
1709
1710 offset = req->assoclen + ctx->textlen;
1711 authsize = crypto_aead_authsize(tfm);
1712 if (enc) {
1713 scatterwalk_map_and_copy(otag, req->dst, offset, authsize, 1);
1714 err = 0;
1715 } else {
1716 scatterwalk_map_and_copy(itag, req->src, offset, authsize, 0);
1717 err = crypto_memneq(itag, otag, authsize) ? -EBADMSG : 0;
1718 }
1719
1720 return atmel_aes_complete(dd, err);
1721 }
1722
atmel_aes_gcm_crypt(struct aead_request * req,unsigned long mode)1723 static int atmel_aes_gcm_crypt(struct aead_request *req,
1724 unsigned long mode)
1725 {
1726 struct atmel_aes_base_ctx *ctx;
1727 struct atmel_aes_reqctx *rctx;
1728 struct atmel_aes_dev *dd;
1729
1730 ctx = crypto_aead_ctx(crypto_aead_reqtfm(req));
1731 ctx->block_size = AES_BLOCK_SIZE;
1732
1733 dd = atmel_aes_find_dev(ctx);
1734 if (!dd)
1735 return -ENODEV;
1736
1737 rctx = aead_request_ctx(req);
1738 rctx->mode = AES_FLAGS_GCM | mode;
1739
1740 return atmel_aes_handle_queue(dd, &req->base);
1741 }
1742
atmel_aes_gcm_setkey(struct crypto_aead * tfm,const u8 * key,unsigned int keylen)1743 static int atmel_aes_gcm_setkey(struct crypto_aead *tfm, const u8 *key,
1744 unsigned int keylen)
1745 {
1746 struct atmel_aes_base_ctx *ctx = crypto_aead_ctx(tfm);
1747
1748 if (keylen != AES_KEYSIZE_256 &&
1749 keylen != AES_KEYSIZE_192 &&
1750 keylen != AES_KEYSIZE_128) {
1751 crypto_aead_set_flags(tfm, CRYPTO_TFM_RES_BAD_KEY_LEN);
1752 return -EINVAL;
1753 }
1754
1755 memcpy(ctx->key, key, keylen);
1756 ctx->keylen = keylen;
1757
1758 return 0;
1759 }
1760
atmel_aes_gcm_setauthsize(struct crypto_aead * tfm,unsigned int authsize)1761 static int atmel_aes_gcm_setauthsize(struct crypto_aead *tfm,
1762 unsigned int authsize)
1763 {
1764 /* Same as crypto_gcm_authsize() from crypto/gcm.c */
1765 switch (authsize) {
1766 case 4:
1767 case 8:
1768 case 12:
1769 case 13:
1770 case 14:
1771 case 15:
1772 case 16:
1773 break;
1774 default:
1775 return -EINVAL;
1776 }
1777
1778 return 0;
1779 }
1780
atmel_aes_gcm_encrypt(struct aead_request * req)1781 static int atmel_aes_gcm_encrypt(struct aead_request *req)
1782 {
1783 return atmel_aes_gcm_crypt(req, AES_FLAGS_ENCRYPT);
1784 }
1785
atmel_aes_gcm_decrypt(struct aead_request * req)1786 static int atmel_aes_gcm_decrypt(struct aead_request *req)
1787 {
1788 return atmel_aes_gcm_crypt(req, 0);
1789 }
1790
atmel_aes_gcm_init(struct crypto_aead * tfm)1791 static int atmel_aes_gcm_init(struct crypto_aead *tfm)
1792 {
1793 struct atmel_aes_gcm_ctx *ctx = crypto_aead_ctx(tfm);
1794
1795 crypto_aead_set_reqsize(tfm, sizeof(struct atmel_aes_reqctx));
1796 ctx->base.start = atmel_aes_gcm_start;
1797
1798 return 0;
1799 }
1800
atmel_aes_gcm_exit(struct crypto_aead * tfm)1801 static void atmel_aes_gcm_exit(struct crypto_aead *tfm)
1802 {
1803
1804 }
1805
1806 static struct aead_alg aes_gcm_alg = {
1807 .setkey = atmel_aes_gcm_setkey,
1808 .setauthsize = atmel_aes_gcm_setauthsize,
1809 .encrypt = atmel_aes_gcm_encrypt,
1810 .decrypt = atmel_aes_gcm_decrypt,
1811 .init = atmel_aes_gcm_init,
1812 .exit = atmel_aes_gcm_exit,
1813 .ivsize = 12,
1814 .maxauthsize = AES_BLOCK_SIZE,
1815
1816 .base = {
1817 .cra_name = "gcm(aes)",
1818 .cra_driver_name = "atmel-gcm-aes",
1819 .cra_priority = ATMEL_AES_PRIORITY,
1820 .cra_flags = CRYPTO_ALG_ASYNC,
1821 .cra_blocksize = 1,
1822 .cra_ctxsize = sizeof(struct atmel_aes_gcm_ctx),
1823 .cra_alignmask = 0xf,
1824 .cra_module = THIS_MODULE,
1825 },
1826 };
1827
1828
1829 /* xts functions */
1830
1831 static inline struct atmel_aes_xts_ctx *
atmel_aes_xts_ctx_cast(struct atmel_aes_base_ctx * ctx)1832 atmel_aes_xts_ctx_cast(struct atmel_aes_base_ctx *ctx)
1833 {
1834 return container_of(ctx, struct atmel_aes_xts_ctx, base);
1835 }
1836
1837 static int atmel_aes_xts_process_data(struct atmel_aes_dev *dd);
1838
atmel_aes_xts_start(struct atmel_aes_dev * dd)1839 static int atmel_aes_xts_start(struct atmel_aes_dev *dd)
1840 {
1841 struct atmel_aes_xts_ctx *ctx = atmel_aes_xts_ctx_cast(dd->ctx);
1842 struct ablkcipher_request *req = ablkcipher_request_cast(dd->areq);
1843 struct atmel_aes_reqctx *rctx = ablkcipher_request_ctx(req);
1844 unsigned long flags;
1845 int err;
1846
1847 atmel_aes_set_mode(dd, rctx);
1848
1849 err = atmel_aes_hw_init(dd);
1850 if (err)
1851 return atmel_aes_complete(dd, err);
1852
1853 /* Compute the tweak value from req->info with ecb(aes). */
1854 flags = dd->flags;
1855 dd->flags &= ~AES_FLAGS_MODE_MASK;
1856 dd->flags |= (AES_FLAGS_ECB | AES_FLAGS_ENCRYPT);
1857 atmel_aes_write_ctrl_key(dd, false, NULL,
1858 ctx->key2, ctx->base.keylen);
1859 dd->flags = flags;
1860
1861 atmel_aes_write_block(dd, AES_IDATAR(0), req->info);
1862 return atmel_aes_wait_for_data_ready(dd, atmel_aes_xts_process_data);
1863 }
1864
atmel_aes_xts_process_data(struct atmel_aes_dev * dd)1865 static int atmel_aes_xts_process_data(struct atmel_aes_dev *dd)
1866 {
1867 struct ablkcipher_request *req = ablkcipher_request_cast(dd->areq);
1868 bool use_dma = (req->nbytes >= ATMEL_AES_DMA_THRESHOLD);
1869 u32 tweak[AES_BLOCK_SIZE / sizeof(u32)];
1870 static const u32 one[AES_BLOCK_SIZE / sizeof(u32)] = {cpu_to_le32(1), };
1871 u8 *tweak_bytes = (u8 *)tweak;
1872 int i;
1873
1874 /* Read the computed ciphered tweak value. */
1875 atmel_aes_read_block(dd, AES_ODATAR(0), tweak);
1876 /*
1877 * Hardware quirk:
1878 * the order of the ciphered tweak bytes need to be reversed before
1879 * writing them into the ODATARx registers.
1880 */
1881 for (i = 0; i < AES_BLOCK_SIZE/2; ++i) {
1882 u8 tmp = tweak_bytes[AES_BLOCK_SIZE - 1 - i];
1883
1884 tweak_bytes[AES_BLOCK_SIZE - 1 - i] = tweak_bytes[i];
1885 tweak_bytes[i] = tmp;
1886 }
1887
1888 /* Process the data. */
1889 atmel_aes_write_ctrl(dd, use_dma, NULL);
1890 atmel_aes_write_block(dd, AES_TWR(0), tweak);
1891 atmel_aes_write_block(dd, AES_ALPHAR(0), one);
1892 if (use_dma)
1893 return atmel_aes_dma_start(dd, req->src, req->dst, req->nbytes,
1894 atmel_aes_transfer_complete);
1895
1896 return atmel_aes_cpu_start(dd, req->src, req->dst, req->nbytes,
1897 atmel_aes_transfer_complete);
1898 }
1899
atmel_aes_xts_setkey(struct crypto_ablkcipher * tfm,const u8 * key,unsigned int keylen)1900 static int atmel_aes_xts_setkey(struct crypto_ablkcipher *tfm, const u8 *key,
1901 unsigned int keylen)
1902 {
1903 struct atmel_aes_xts_ctx *ctx = crypto_ablkcipher_ctx(tfm);
1904 int err;
1905
1906 err = xts_check_key(crypto_ablkcipher_tfm(tfm), key, keylen);
1907 if (err)
1908 return err;
1909
1910 memcpy(ctx->base.key, key, keylen/2);
1911 memcpy(ctx->key2, key + keylen/2, keylen/2);
1912 ctx->base.keylen = keylen/2;
1913
1914 return 0;
1915 }
1916
atmel_aes_xts_encrypt(struct ablkcipher_request * req)1917 static int atmel_aes_xts_encrypt(struct ablkcipher_request *req)
1918 {
1919 return atmel_aes_crypt(req, AES_FLAGS_XTS | AES_FLAGS_ENCRYPT);
1920 }
1921
atmel_aes_xts_decrypt(struct ablkcipher_request * req)1922 static int atmel_aes_xts_decrypt(struct ablkcipher_request *req)
1923 {
1924 return atmel_aes_crypt(req, AES_FLAGS_XTS);
1925 }
1926
atmel_aes_xts_cra_init(struct crypto_tfm * tfm)1927 static int atmel_aes_xts_cra_init(struct crypto_tfm *tfm)
1928 {
1929 struct atmel_aes_xts_ctx *ctx = crypto_tfm_ctx(tfm);
1930
1931 tfm->crt_ablkcipher.reqsize = sizeof(struct atmel_aes_reqctx);
1932 ctx->base.start = atmel_aes_xts_start;
1933
1934 return 0;
1935 }
1936
1937 static struct crypto_alg aes_xts_alg = {
1938 .cra_name = "xts(aes)",
1939 .cra_driver_name = "atmel-xts-aes",
1940 .cra_priority = ATMEL_AES_PRIORITY,
1941 .cra_flags = CRYPTO_ALG_TYPE_ABLKCIPHER | CRYPTO_ALG_ASYNC,
1942 .cra_blocksize = AES_BLOCK_SIZE,
1943 .cra_ctxsize = sizeof(struct atmel_aes_xts_ctx),
1944 .cra_alignmask = 0xf,
1945 .cra_type = &crypto_ablkcipher_type,
1946 .cra_module = THIS_MODULE,
1947 .cra_init = atmel_aes_xts_cra_init,
1948 .cra_exit = atmel_aes_cra_exit,
1949 .cra_u.ablkcipher = {
1950 .min_keysize = 2 * AES_MIN_KEY_SIZE,
1951 .max_keysize = 2 * AES_MAX_KEY_SIZE,
1952 .ivsize = AES_BLOCK_SIZE,
1953 .setkey = atmel_aes_xts_setkey,
1954 .encrypt = atmel_aes_xts_encrypt,
1955 .decrypt = atmel_aes_xts_decrypt,
1956 }
1957 };
1958
1959 #ifdef CONFIG_CRYPTO_DEV_ATMEL_AUTHENC
1960 /* authenc aead functions */
1961
1962 static int atmel_aes_authenc_start(struct atmel_aes_dev *dd);
1963 static int atmel_aes_authenc_init(struct atmel_aes_dev *dd, int err,
1964 bool is_async);
1965 static int atmel_aes_authenc_transfer(struct atmel_aes_dev *dd, int err,
1966 bool is_async);
1967 static int atmel_aes_authenc_digest(struct atmel_aes_dev *dd);
1968 static int atmel_aes_authenc_final(struct atmel_aes_dev *dd, int err,
1969 bool is_async);
1970
atmel_aes_authenc_complete(struct atmel_aes_dev * dd,int err)1971 static void atmel_aes_authenc_complete(struct atmel_aes_dev *dd, int err)
1972 {
1973 struct aead_request *req = aead_request_cast(dd->areq);
1974 struct atmel_aes_authenc_reqctx *rctx = aead_request_ctx(req);
1975
1976 if (err && (dd->flags & AES_FLAGS_OWN_SHA))
1977 atmel_sha_authenc_abort(&rctx->auth_req);
1978 dd->flags &= ~AES_FLAGS_OWN_SHA;
1979 }
1980
atmel_aes_authenc_start(struct atmel_aes_dev * dd)1981 static int atmel_aes_authenc_start(struct atmel_aes_dev *dd)
1982 {
1983 struct aead_request *req = aead_request_cast(dd->areq);
1984 struct atmel_aes_authenc_reqctx *rctx = aead_request_ctx(req);
1985 struct crypto_aead *tfm = crypto_aead_reqtfm(req);
1986 struct atmel_aes_authenc_ctx *ctx = crypto_aead_ctx(tfm);
1987 int err;
1988
1989 atmel_aes_set_mode(dd, &rctx->base);
1990
1991 err = atmel_aes_hw_init(dd);
1992 if (err)
1993 return atmel_aes_complete(dd, err);
1994
1995 return atmel_sha_authenc_schedule(&rctx->auth_req, ctx->auth,
1996 atmel_aes_authenc_init, dd);
1997 }
1998
atmel_aes_authenc_init(struct atmel_aes_dev * dd,int err,bool is_async)1999 static int atmel_aes_authenc_init(struct atmel_aes_dev *dd, int err,
2000 bool is_async)
2001 {
2002 struct aead_request *req = aead_request_cast(dd->areq);
2003 struct atmel_aes_authenc_reqctx *rctx = aead_request_ctx(req);
2004
2005 if (is_async)
2006 dd->is_async = true;
2007 if (err)
2008 return atmel_aes_complete(dd, err);
2009
2010 /* If here, we've got the ownership of the SHA device. */
2011 dd->flags |= AES_FLAGS_OWN_SHA;
2012
2013 /* Configure the SHA device. */
2014 return atmel_sha_authenc_init(&rctx->auth_req,
2015 req->src, req->assoclen,
2016 rctx->textlen,
2017 atmel_aes_authenc_transfer, dd);
2018 }
2019
atmel_aes_authenc_transfer(struct atmel_aes_dev * dd,int err,bool is_async)2020 static int atmel_aes_authenc_transfer(struct atmel_aes_dev *dd, int err,
2021 bool is_async)
2022 {
2023 struct aead_request *req = aead_request_cast(dd->areq);
2024 struct atmel_aes_authenc_reqctx *rctx = aead_request_ctx(req);
2025 bool enc = atmel_aes_is_encrypt(dd);
2026 struct scatterlist *src, *dst;
2027 u32 iv[AES_BLOCK_SIZE / sizeof(u32)];
2028 u32 emr;
2029
2030 if (is_async)
2031 dd->is_async = true;
2032 if (err)
2033 return atmel_aes_complete(dd, err);
2034
2035 /* Prepare src and dst scatter-lists to transfer cipher/plain texts. */
2036 src = scatterwalk_ffwd(rctx->src, req->src, req->assoclen);
2037 dst = src;
2038
2039 if (req->src != req->dst)
2040 dst = scatterwalk_ffwd(rctx->dst, req->dst, req->assoclen);
2041
2042 /* Configure the AES device. */
2043 memcpy(iv, req->iv, sizeof(iv));
2044
2045 /*
2046 * Here we always set the 2nd parameter of atmel_aes_write_ctrl() to
2047 * 'true' even if the data transfer is actually performed by the CPU (so
2048 * not by the DMA) because we must force the AES_MR_SMOD bitfield to the
2049 * value AES_MR_SMOD_IDATAR0. Indeed, both AES_MR_SMOD and SHA_MR_SMOD
2050 * must be set to *_MR_SMOD_IDATAR0.
2051 */
2052 atmel_aes_write_ctrl(dd, true, iv);
2053 emr = AES_EMR_PLIPEN;
2054 if (!enc)
2055 emr |= AES_EMR_PLIPD;
2056 atmel_aes_write(dd, AES_EMR, emr);
2057
2058 /* Transfer data. */
2059 return atmel_aes_dma_start(dd, src, dst, rctx->textlen,
2060 atmel_aes_authenc_digest);
2061 }
2062
atmel_aes_authenc_digest(struct atmel_aes_dev * dd)2063 static int atmel_aes_authenc_digest(struct atmel_aes_dev *dd)
2064 {
2065 struct aead_request *req = aead_request_cast(dd->areq);
2066 struct atmel_aes_authenc_reqctx *rctx = aead_request_ctx(req);
2067
2068 /* atmel_sha_authenc_final() releases the SHA device. */
2069 dd->flags &= ~AES_FLAGS_OWN_SHA;
2070 return atmel_sha_authenc_final(&rctx->auth_req,
2071 rctx->digest, sizeof(rctx->digest),
2072 atmel_aes_authenc_final, dd);
2073 }
2074
atmel_aes_authenc_final(struct atmel_aes_dev * dd,int err,bool is_async)2075 static int atmel_aes_authenc_final(struct atmel_aes_dev *dd, int err,
2076 bool is_async)
2077 {
2078 struct aead_request *req = aead_request_cast(dd->areq);
2079 struct atmel_aes_authenc_reqctx *rctx = aead_request_ctx(req);
2080 struct crypto_aead *tfm = crypto_aead_reqtfm(req);
2081 bool enc = atmel_aes_is_encrypt(dd);
2082 u32 idigest[SHA512_DIGEST_SIZE / sizeof(u32)], *odigest = rctx->digest;
2083 u32 offs, authsize;
2084
2085 if (is_async)
2086 dd->is_async = true;
2087 if (err)
2088 goto complete;
2089
2090 offs = req->assoclen + rctx->textlen;
2091 authsize = crypto_aead_authsize(tfm);
2092 if (enc) {
2093 scatterwalk_map_and_copy(odigest, req->dst, offs, authsize, 1);
2094 } else {
2095 scatterwalk_map_and_copy(idigest, req->src, offs, authsize, 0);
2096 if (crypto_memneq(idigest, odigest, authsize))
2097 err = -EBADMSG;
2098 }
2099
2100 complete:
2101 return atmel_aes_complete(dd, err);
2102 }
2103
atmel_aes_authenc_setkey(struct crypto_aead * tfm,const u8 * key,unsigned int keylen)2104 static int atmel_aes_authenc_setkey(struct crypto_aead *tfm, const u8 *key,
2105 unsigned int keylen)
2106 {
2107 struct atmel_aes_authenc_ctx *ctx = crypto_aead_ctx(tfm);
2108 struct crypto_authenc_keys keys;
2109 u32 flags;
2110 int err;
2111
2112 if (crypto_authenc_extractkeys(&keys, key, keylen) != 0)
2113 goto badkey;
2114
2115 if (keys.enckeylen > sizeof(ctx->base.key))
2116 goto badkey;
2117
2118 /* Save auth key. */
2119 flags = crypto_aead_get_flags(tfm);
2120 err = atmel_sha_authenc_setkey(ctx->auth,
2121 keys.authkey, keys.authkeylen,
2122 &flags);
2123 crypto_aead_set_flags(tfm, flags & CRYPTO_TFM_RES_MASK);
2124 if (err) {
2125 memzero_explicit(&keys, sizeof(keys));
2126 return err;
2127 }
2128
2129 /* Save enc key. */
2130 ctx->base.keylen = keys.enckeylen;
2131 memcpy(ctx->base.key, keys.enckey, keys.enckeylen);
2132
2133 memzero_explicit(&keys, sizeof(keys));
2134 return 0;
2135
2136 badkey:
2137 crypto_aead_set_flags(tfm, CRYPTO_TFM_RES_BAD_KEY_LEN);
2138 memzero_explicit(&keys, sizeof(keys));
2139 return -EINVAL;
2140 }
2141
atmel_aes_authenc_init_tfm(struct crypto_aead * tfm,unsigned long auth_mode)2142 static int atmel_aes_authenc_init_tfm(struct crypto_aead *tfm,
2143 unsigned long auth_mode)
2144 {
2145 struct atmel_aes_authenc_ctx *ctx = crypto_aead_ctx(tfm);
2146 unsigned int auth_reqsize = atmel_sha_authenc_get_reqsize();
2147
2148 ctx->auth = atmel_sha_authenc_spawn(auth_mode);
2149 if (IS_ERR(ctx->auth))
2150 return PTR_ERR(ctx->auth);
2151
2152 crypto_aead_set_reqsize(tfm, (sizeof(struct atmel_aes_authenc_reqctx) +
2153 auth_reqsize));
2154 ctx->base.start = atmel_aes_authenc_start;
2155
2156 return 0;
2157 }
2158
atmel_aes_authenc_hmac_sha1_init_tfm(struct crypto_aead * tfm)2159 static int atmel_aes_authenc_hmac_sha1_init_tfm(struct crypto_aead *tfm)
2160 {
2161 return atmel_aes_authenc_init_tfm(tfm, SHA_FLAGS_HMAC_SHA1);
2162 }
2163
atmel_aes_authenc_hmac_sha224_init_tfm(struct crypto_aead * tfm)2164 static int atmel_aes_authenc_hmac_sha224_init_tfm(struct crypto_aead *tfm)
2165 {
2166 return atmel_aes_authenc_init_tfm(tfm, SHA_FLAGS_HMAC_SHA224);
2167 }
2168
atmel_aes_authenc_hmac_sha256_init_tfm(struct crypto_aead * tfm)2169 static int atmel_aes_authenc_hmac_sha256_init_tfm(struct crypto_aead *tfm)
2170 {
2171 return atmel_aes_authenc_init_tfm(tfm, SHA_FLAGS_HMAC_SHA256);
2172 }
2173
atmel_aes_authenc_hmac_sha384_init_tfm(struct crypto_aead * tfm)2174 static int atmel_aes_authenc_hmac_sha384_init_tfm(struct crypto_aead *tfm)
2175 {
2176 return atmel_aes_authenc_init_tfm(tfm, SHA_FLAGS_HMAC_SHA384);
2177 }
2178
atmel_aes_authenc_hmac_sha512_init_tfm(struct crypto_aead * tfm)2179 static int atmel_aes_authenc_hmac_sha512_init_tfm(struct crypto_aead *tfm)
2180 {
2181 return atmel_aes_authenc_init_tfm(tfm, SHA_FLAGS_HMAC_SHA512);
2182 }
2183
atmel_aes_authenc_exit_tfm(struct crypto_aead * tfm)2184 static void atmel_aes_authenc_exit_tfm(struct crypto_aead *tfm)
2185 {
2186 struct atmel_aes_authenc_ctx *ctx = crypto_aead_ctx(tfm);
2187
2188 atmel_sha_authenc_free(ctx->auth);
2189 }
2190
atmel_aes_authenc_crypt(struct aead_request * req,unsigned long mode)2191 static int atmel_aes_authenc_crypt(struct aead_request *req,
2192 unsigned long mode)
2193 {
2194 struct atmel_aes_authenc_reqctx *rctx = aead_request_ctx(req);
2195 struct crypto_aead *tfm = crypto_aead_reqtfm(req);
2196 struct atmel_aes_base_ctx *ctx = crypto_aead_ctx(tfm);
2197 u32 authsize = crypto_aead_authsize(tfm);
2198 bool enc = (mode & AES_FLAGS_ENCRYPT);
2199 struct atmel_aes_dev *dd;
2200
2201 /* Compute text length. */
2202 if (!enc && req->cryptlen < authsize)
2203 return -EINVAL;
2204 rctx->textlen = req->cryptlen - (enc ? 0 : authsize);
2205
2206 /*
2207 * Currently, empty messages are not supported yet:
2208 * the SHA auto-padding can be used only on non-empty messages.
2209 * Hence a special case needs to be implemented for empty message.
2210 */
2211 if (!rctx->textlen && !req->assoclen)
2212 return -EINVAL;
2213
2214 rctx->base.mode = mode;
2215 ctx->block_size = AES_BLOCK_SIZE;
2216
2217 dd = atmel_aes_find_dev(ctx);
2218 if (!dd)
2219 return -ENODEV;
2220
2221 return atmel_aes_handle_queue(dd, &req->base);
2222 }
2223
atmel_aes_authenc_cbc_aes_encrypt(struct aead_request * req)2224 static int atmel_aes_authenc_cbc_aes_encrypt(struct aead_request *req)
2225 {
2226 return atmel_aes_authenc_crypt(req, AES_FLAGS_CBC | AES_FLAGS_ENCRYPT);
2227 }
2228
atmel_aes_authenc_cbc_aes_decrypt(struct aead_request * req)2229 static int atmel_aes_authenc_cbc_aes_decrypt(struct aead_request *req)
2230 {
2231 return atmel_aes_authenc_crypt(req, AES_FLAGS_CBC);
2232 }
2233
2234 static struct aead_alg aes_authenc_algs[] = {
2235 {
2236 .setkey = atmel_aes_authenc_setkey,
2237 .encrypt = atmel_aes_authenc_cbc_aes_encrypt,
2238 .decrypt = atmel_aes_authenc_cbc_aes_decrypt,
2239 .init = atmel_aes_authenc_hmac_sha1_init_tfm,
2240 .exit = atmel_aes_authenc_exit_tfm,
2241 .ivsize = AES_BLOCK_SIZE,
2242 .maxauthsize = SHA1_DIGEST_SIZE,
2243
2244 .base = {
2245 .cra_name = "authenc(hmac(sha1),cbc(aes))",
2246 .cra_driver_name = "atmel-authenc-hmac-sha1-cbc-aes",
2247 .cra_priority = ATMEL_AES_PRIORITY,
2248 .cra_flags = CRYPTO_ALG_ASYNC,
2249 .cra_blocksize = AES_BLOCK_SIZE,
2250 .cra_ctxsize = sizeof(struct atmel_aes_authenc_ctx),
2251 .cra_alignmask = 0xf,
2252 .cra_module = THIS_MODULE,
2253 },
2254 },
2255 {
2256 .setkey = atmel_aes_authenc_setkey,
2257 .encrypt = atmel_aes_authenc_cbc_aes_encrypt,
2258 .decrypt = atmel_aes_authenc_cbc_aes_decrypt,
2259 .init = atmel_aes_authenc_hmac_sha224_init_tfm,
2260 .exit = atmel_aes_authenc_exit_tfm,
2261 .ivsize = AES_BLOCK_SIZE,
2262 .maxauthsize = SHA224_DIGEST_SIZE,
2263
2264 .base = {
2265 .cra_name = "authenc(hmac(sha224),cbc(aes))",
2266 .cra_driver_name = "atmel-authenc-hmac-sha224-cbc-aes",
2267 .cra_priority = ATMEL_AES_PRIORITY,
2268 .cra_flags = CRYPTO_ALG_ASYNC,
2269 .cra_blocksize = AES_BLOCK_SIZE,
2270 .cra_ctxsize = sizeof(struct atmel_aes_authenc_ctx),
2271 .cra_alignmask = 0xf,
2272 .cra_module = THIS_MODULE,
2273 },
2274 },
2275 {
2276 .setkey = atmel_aes_authenc_setkey,
2277 .encrypt = atmel_aes_authenc_cbc_aes_encrypt,
2278 .decrypt = atmel_aes_authenc_cbc_aes_decrypt,
2279 .init = atmel_aes_authenc_hmac_sha256_init_tfm,
2280 .exit = atmel_aes_authenc_exit_tfm,
2281 .ivsize = AES_BLOCK_SIZE,
2282 .maxauthsize = SHA256_DIGEST_SIZE,
2283
2284 .base = {
2285 .cra_name = "authenc(hmac(sha256),cbc(aes))",
2286 .cra_driver_name = "atmel-authenc-hmac-sha256-cbc-aes",
2287 .cra_priority = ATMEL_AES_PRIORITY,
2288 .cra_flags = CRYPTO_ALG_ASYNC,
2289 .cra_blocksize = AES_BLOCK_SIZE,
2290 .cra_ctxsize = sizeof(struct atmel_aes_authenc_ctx),
2291 .cra_alignmask = 0xf,
2292 .cra_module = THIS_MODULE,
2293 },
2294 },
2295 {
2296 .setkey = atmel_aes_authenc_setkey,
2297 .encrypt = atmel_aes_authenc_cbc_aes_encrypt,
2298 .decrypt = atmel_aes_authenc_cbc_aes_decrypt,
2299 .init = atmel_aes_authenc_hmac_sha384_init_tfm,
2300 .exit = atmel_aes_authenc_exit_tfm,
2301 .ivsize = AES_BLOCK_SIZE,
2302 .maxauthsize = SHA384_DIGEST_SIZE,
2303
2304 .base = {
2305 .cra_name = "authenc(hmac(sha384),cbc(aes))",
2306 .cra_driver_name = "atmel-authenc-hmac-sha384-cbc-aes",
2307 .cra_priority = ATMEL_AES_PRIORITY,
2308 .cra_flags = CRYPTO_ALG_ASYNC,
2309 .cra_blocksize = AES_BLOCK_SIZE,
2310 .cra_ctxsize = sizeof(struct atmel_aes_authenc_ctx),
2311 .cra_alignmask = 0xf,
2312 .cra_module = THIS_MODULE,
2313 },
2314 },
2315 {
2316 .setkey = atmel_aes_authenc_setkey,
2317 .encrypt = atmel_aes_authenc_cbc_aes_encrypt,
2318 .decrypt = atmel_aes_authenc_cbc_aes_decrypt,
2319 .init = atmel_aes_authenc_hmac_sha512_init_tfm,
2320 .exit = atmel_aes_authenc_exit_tfm,
2321 .ivsize = AES_BLOCK_SIZE,
2322 .maxauthsize = SHA512_DIGEST_SIZE,
2323
2324 .base = {
2325 .cra_name = "authenc(hmac(sha512),cbc(aes))",
2326 .cra_driver_name = "atmel-authenc-hmac-sha512-cbc-aes",
2327 .cra_priority = ATMEL_AES_PRIORITY,
2328 .cra_flags = CRYPTO_ALG_ASYNC,
2329 .cra_blocksize = AES_BLOCK_SIZE,
2330 .cra_ctxsize = sizeof(struct atmel_aes_authenc_ctx),
2331 .cra_alignmask = 0xf,
2332 .cra_module = THIS_MODULE,
2333 },
2334 },
2335 };
2336 #endif /* CONFIG_CRYPTO_DEV_ATMEL_AUTHENC */
2337
2338 /* Probe functions */
2339
atmel_aes_buff_init(struct atmel_aes_dev * dd)2340 static int atmel_aes_buff_init(struct atmel_aes_dev *dd)
2341 {
2342 dd->buf = (void *)__get_free_pages(GFP_KERNEL, ATMEL_AES_BUFFER_ORDER);
2343 dd->buflen = ATMEL_AES_BUFFER_SIZE;
2344 dd->buflen &= ~(AES_BLOCK_SIZE - 1);
2345
2346 if (!dd->buf) {
2347 dev_err(dd->dev, "unable to alloc pages.\n");
2348 return -ENOMEM;
2349 }
2350
2351 return 0;
2352 }
2353
atmel_aes_buff_cleanup(struct atmel_aes_dev * dd)2354 static void atmel_aes_buff_cleanup(struct atmel_aes_dev *dd)
2355 {
2356 free_page((unsigned long)dd->buf);
2357 }
2358
atmel_aes_filter(struct dma_chan * chan,void * slave)2359 static bool atmel_aes_filter(struct dma_chan *chan, void *slave)
2360 {
2361 struct at_dma_slave *sl = slave;
2362
2363 if (sl && sl->dma_dev == chan->device->dev) {
2364 chan->private = sl;
2365 return true;
2366 } else {
2367 return false;
2368 }
2369 }
2370
atmel_aes_dma_init(struct atmel_aes_dev * dd,struct crypto_platform_data * pdata)2371 static int atmel_aes_dma_init(struct atmel_aes_dev *dd,
2372 struct crypto_platform_data *pdata)
2373 {
2374 struct at_dma_slave *slave;
2375 int err = -ENOMEM;
2376 dma_cap_mask_t mask;
2377
2378 dma_cap_zero(mask);
2379 dma_cap_set(DMA_SLAVE, mask);
2380
2381 /* Try to grab 2 DMA channels */
2382 slave = &pdata->dma_slave->rxdata;
2383 dd->src.chan = dma_request_slave_channel_compat(mask, atmel_aes_filter,
2384 slave, dd->dev, "tx");
2385 if (!dd->src.chan)
2386 goto err_dma_in;
2387
2388 slave = &pdata->dma_slave->txdata;
2389 dd->dst.chan = dma_request_slave_channel_compat(mask, atmel_aes_filter,
2390 slave, dd->dev, "rx");
2391 if (!dd->dst.chan)
2392 goto err_dma_out;
2393
2394 return 0;
2395
2396 err_dma_out:
2397 dma_release_channel(dd->src.chan);
2398 err_dma_in:
2399 dev_warn(dd->dev, "no DMA channel available\n");
2400 return err;
2401 }
2402
atmel_aes_dma_cleanup(struct atmel_aes_dev * dd)2403 static void atmel_aes_dma_cleanup(struct atmel_aes_dev *dd)
2404 {
2405 dma_release_channel(dd->dst.chan);
2406 dma_release_channel(dd->src.chan);
2407 }
2408
atmel_aes_queue_task(unsigned long data)2409 static void atmel_aes_queue_task(unsigned long data)
2410 {
2411 struct atmel_aes_dev *dd = (struct atmel_aes_dev *)data;
2412
2413 atmel_aes_handle_queue(dd, NULL);
2414 }
2415
atmel_aes_done_task(unsigned long data)2416 static void atmel_aes_done_task(unsigned long data)
2417 {
2418 struct atmel_aes_dev *dd = (struct atmel_aes_dev *)data;
2419
2420 dd->is_async = true;
2421 (void)dd->resume(dd);
2422 }
2423
atmel_aes_irq(int irq,void * dev_id)2424 static irqreturn_t atmel_aes_irq(int irq, void *dev_id)
2425 {
2426 struct atmel_aes_dev *aes_dd = dev_id;
2427 u32 reg;
2428
2429 reg = atmel_aes_read(aes_dd, AES_ISR);
2430 if (reg & atmel_aes_read(aes_dd, AES_IMR)) {
2431 atmel_aes_write(aes_dd, AES_IDR, reg);
2432 if (AES_FLAGS_BUSY & aes_dd->flags)
2433 tasklet_schedule(&aes_dd->done_task);
2434 else
2435 dev_warn(aes_dd->dev, "AES interrupt when no active requests.\n");
2436 return IRQ_HANDLED;
2437 }
2438
2439 return IRQ_NONE;
2440 }
2441
atmel_aes_unregister_algs(struct atmel_aes_dev * dd)2442 static void atmel_aes_unregister_algs(struct atmel_aes_dev *dd)
2443 {
2444 int i;
2445
2446 #ifdef CONFIG_CRYPTO_DEV_ATMEL_AUTHENC
2447 if (dd->caps.has_authenc)
2448 for (i = 0; i < ARRAY_SIZE(aes_authenc_algs); i++)
2449 crypto_unregister_aead(&aes_authenc_algs[i]);
2450 #endif
2451
2452 if (dd->caps.has_xts)
2453 crypto_unregister_alg(&aes_xts_alg);
2454
2455 if (dd->caps.has_gcm)
2456 crypto_unregister_aead(&aes_gcm_alg);
2457
2458 if (dd->caps.has_cfb64)
2459 crypto_unregister_alg(&aes_cfb64_alg);
2460
2461 for (i = 0; i < ARRAY_SIZE(aes_algs); i++)
2462 crypto_unregister_alg(&aes_algs[i]);
2463 }
2464
atmel_aes_register_algs(struct atmel_aes_dev * dd)2465 static int atmel_aes_register_algs(struct atmel_aes_dev *dd)
2466 {
2467 int err, i, j;
2468
2469 for (i = 0; i < ARRAY_SIZE(aes_algs); i++) {
2470 err = crypto_register_alg(&aes_algs[i]);
2471 if (err)
2472 goto err_aes_algs;
2473 }
2474
2475 if (dd->caps.has_cfb64) {
2476 err = crypto_register_alg(&aes_cfb64_alg);
2477 if (err)
2478 goto err_aes_cfb64_alg;
2479 }
2480
2481 if (dd->caps.has_gcm) {
2482 err = crypto_register_aead(&aes_gcm_alg);
2483 if (err)
2484 goto err_aes_gcm_alg;
2485 }
2486
2487 if (dd->caps.has_xts) {
2488 err = crypto_register_alg(&aes_xts_alg);
2489 if (err)
2490 goto err_aes_xts_alg;
2491 }
2492
2493 #ifdef CONFIG_CRYPTO_DEV_ATMEL_AUTHENC
2494 if (dd->caps.has_authenc) {
2495 for (i = 0; i < ARRAY_SIZE(aes_authenc_algs); i++) {
2496 err = crypto_register_aead(&aes_authenc_algs[i]);
2497 if (err)
2498 goto err_aes_authenc_alg;
2499 }
2500 }
2501 #endif
2502
2503 return 0;
2504
2505 #ifdef CONFIG_CRYPTO_DEV_ATMEL_AUTHENC
2506 /* i = ARRAY_SIZE(aes_authenc_algs); */
2507 err_aes_authenc_alg:
2508 for (j = 0; j < i; j++)
2509 crypto_unregister_aead(&aes_authenc_algs[j]);
2510 crypto_unregister_alg(&aes_xts_alg);
2511 #endif
2512 err_aes_xts_alg:
2513 crypto_unregister_aead(&aes_gcm_alg);
2514 err_aes_gcm_alg:
2515 crypto_unregister_alg(&aes_cfb64_alg);
2516 err_aes_cfb64_alg:
2517 i = ARRAY_SIZE(aes_algs);
2518 err_aes_algs:
2519 for (j = 0; j < i; j++)
2520 crypto_unregister_alg(&aes_algs[j]);
2521
2522 return err;
2523 }
2524
atmel_aes_get_cap(struct atmel_aes_dev * dd)2525 static void atmel_aes_get_cap(struct atmel_aes_dev *dd)
2526 {
2527 dd->caps.has_dualbuff = 0;
2528 dd->caps.has_cfb64 = 0;
2529 dd->caps.has_gcm = 0;
2530 dd->caps.has_xts = 0;
2531 dd->caps.has_authenc = 0;
2532 dd->caps.max_burst_size = 1;
2533
2534 /* keep only major version number */
2535 switch (dd->hw_version & 0xff0) {
2536 case 0x500:
2537 dd->caps.has_dualbuff = 1;
2538 dd->caps.has_cfb64 = 1;
2539 dd->caps.has_gcm = 1;
2540 dd->caps.has_xts = 1;
2541 dd->caps.has_authenc = 1;
2542 dd->caps.max_burst_size = 4;
2543 break;
2544 case 0x200:
2545 dd->caps.has_dualbuff = 1;
2546 dd->caps.has_cfb64 = 1;
2547 dd->caps.has_gcm = 1;
2548 dd->caps.max_burst_size = 4;
2549 break;
2550 case 0x130:
2551 dd->caps.has_dualbuff = 1;
2552 dd->caps.has_cfb64 = 1;
2553 dd->caps.max_burst_size = 4;
2554 break;
2555 case 0x120:
2556 break;
2557 default:
2558 dev_warn(dd->dev,
2559 "Unmanaged aes version, set minimum capabilities\n");
2560 break;
2561 }
2562 }
2563
2564 #if defined(CONFIG_OF)
2565 static const struct of_device_id atmel_aes_dt_ids[] = {
2566 { .compatible = "atmel,at91sam9g46-aes" },
2567 { /* sentinel */ }
2568 };
2569 MODULE_DEVICE_TABLE(of, atmel_aes_dt_ids);
2570
atmel_aes_of_init(struct platform_device * pdev)2571 static struct crypto_platform_data *atmel_aes_of_init(struct platform_device *pdev)
2572 {
2573 struct device_node *np = pdev->dev.of_node;
2574 struct crypto_platform_data *pdata;
2575
2576 if (!np) {
2577 dev_err(&pdev->dev, "device node not found\n");
2578 return ERR_PTR(-EINVAL);
2579 }
2580
2581 pdata = devm_kzalloc(&pdev->dev, sizeof(*pdata), GFP_KERNEL);
2582 if (!pdata) {
2583 dev_err(&pdev->dev, "could not allocate memory for pdata\n");
2584 return ERR_PTR(-ENOMEM);
2585 }
2586
2587 pdata->dma_slave = devm_kzalloc(&pdev->dev,
2588 sizeof(*(pdata->dma_slave)),
2589 GFP_KERNEL);
2590 if (!pdata->dma_slave) {
2591 dev_err(&pdev->dev, "could not allocate memory for dma_slave\n");
2592 devm_kfree(&pdev->dev, pdata);
2593 return ERR_PTR(-ENOMEM);
2594 }
2595
2596 return pdata;
2597 }
2598 #else
atmel_aes_of_init(struct platform_device * pdev)2599 static inline struct crypto_platform_data *atmel_aes_of_init(struct platform_device *pdev)
2600 {
2601 return ERR_PTR(-EINVAL);
2602 }
2603 #endif
2604
atmel_aes_probe(struct platform_device * pdev)2605 static int atmel_aes_probe(struct platform_device *pdev)
2606 {
2607 struct atmel_aes_dev *aes_dd;
2608 struct crypto_platform_data *pdata;
2609 struct device *dev = &pdev->dev;
2610 struct resource *aes_res;
2611 int err;
2612
2613 pdata = pdev->dev.platform_data;
2614 if (!pdata) {
2615 pdata = atmel_aes_of_init(pdev);
2616 if (IS_ERR(pdata)) {
2617 err = PTR_ERR(pdata);
2618 goto aes_dd_err;
2619 }
2620 }
2621
2622 if (!pdata->dma_slave) {
2623 err = -ENXIO;
2624 goto aes_dd_err;
2625 }
2626
2627 aes_dd = devm_kzalloc(&pdev->dev, sizeof(*aes_dd), GFP_KERNEL);
2628 if (aes_dd == NULL) {
2629 dev_err(dev, "unable to alloc data struct.\n");
2630 err = -ENOMEM;
2631 goto aes_dd_err;
2632 }
2633
2634 aes_dd->dev = dev;
2635
2636 platform_set_drvdata(pdev, aes_dd);
2637
2638 INIT_LIST_HEAD(&aes_dd->list);
2639 spin_lock_init(&aes_dd->lock);
2640
2641 tasklet_init(&aes_dd->done_task, atmel_aes_done_task,
2642 (unsigned long)aes_dd);
2643 tasklet_init(&aes_dd->queue_task, atmel_aes_queue_task,
2644 (unsigned long)aes_dd);
2645
2646 crypto_init_queue(&aes_dd->queue, ATMEL_AES_QUEUE_LENGTH);
2647
2648 aes_dd->irq = -1;
2649
2650 /* Get the base address */
2651 aes_res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
2652 if (!aes_res) {
2653 dev_err(dev, "no MEM resource info\n");
2654 err = -ENODEV;
2655 goto res_err;
2656 }
2657 aes_dd->phys_base = aes_res->start;
2658
2659 /* Get the IRQ */
2660 aes_dd->irq = platform_get_irq(pdev, 0);
2661 if (aes_dd->irq < 0) {
2662 dev_err(dev, "no IRQ resource info\n");
2663 err = aes_dd->irq;
2664 goto res_err;
2665 }
2666
2667 err = devm_request_irq(&pdev->dev, aes_dd->irq, atmel_aes_irq,
2668 IRQF_SHARED, "atmel-aes", aes_dd);
2669 if (err) {
2670 dev_err(dev, "unable to request aes irq.\n");
2671 goto res_err;
2672 }
2673
2674 /* Initializing the clock */
2675 aes_dd->iclk = devm_clk_get(&pdev->dev, "aes_clk");
2676 if (IS_ERR(aes_dd->iclk)) {
2677 dev_err(dev, "clock initialization failed.\n");
2678 err = PTR_ERR(aes_dd->iclk);
2679 goto res_err;
2680 }
2681
2682 aes_dd->io_base = devm_ioremap_resource(&pdev->dev, aes_res);
2683 if (IS_ERR(aes_dd->io_base)) {
2684 dev_err(dev, "can't ioremap\n");
2685 err = PTR_ERR(aes_dd->io_base);
2686 goto res_err;
2687 }
2688
2689 err = clk_prepare(aes_dd->iclk);
2690 if (err)
2691 goto res_err;
2692
2693 err = atmel_aes_hw_version_init(aes_dd);
2694 if (err)
2695 goto iclk_unprepare;
2696
2697 atmel_aes_get_cap(aes_dd);
2698
2699 #ifdef CONFIG_CRYPTO_DEV_ATMEL_AUTHENC
2700 if (aes_dd->caps.has_authenc && !atmel_sha_authenc_is_ready()) {
2701 err = -EPROBE_DEFER;
2702 goto iclk_unprepare;
2703 }
2704 #endif
2705
2706 err = atmel_aes_buff_init(aes_dd);
2707 if (err)
2708 goto err_aes_buff;
2709
2710 err = atmel_aes_dma_init(aes_dd, pdata);
2711 if (err)
2712 goto err_aes_dma;
2713
2714 spin_lock(&atmel_aes.lock);
2715 list_add_tail(&aes_dd->list, &atmel_aes.dev_list);
2716 spin_unlock(&atmel_aes.lock);
2717
2718 err = atmel_aes_register_algs(aes_dd);
2719 if (err)
2720 goto err_algs;
2721
2722 dev_info(dev, "Atmel AES - Using %s, %s for DMA transfers\n",
2723 dma_chan_name(aes_dd->src.chan),
2724 dma_chan_name(aes_dd->dst.chan));
2725
2726 return 0;
2727
2728 err_algs:
2729 spin_lock(&atmel_aes.lock);
2730 list_del(&aes_dd->list);
2731 spin_unlock(&atmel_aes.lock);
2732 atmel_aes_dma_cleanup(aes_dd);
2733 err_aes_dma:
2734 atmel_aes_buff_cleanup(aes_dd);
2735 err_aes_buff:
2736 iclk_unprepare:
2737 clk_unprepare(aes_dd->iclk);
2738 res_err:
2739 tasklet_kill(&aes_dd->done_task);
2740 tasklet_kill(&aes_dd->queue_task);
2741 aes_dd_err:
2742 if (err != -EPROBE_DEFER)
2743 dev_err(dev, "initialization failed.\n");
2744
2745 return err;
2746 }
2747
atmel_aes_remove(struct platform_device * pdev)2748 static int atmel_aes_remove(struct platform_device *pdev)
2749 {
2750 struct atmel_aes_dev *aes_dd;
2751
2752 aes_dd = platform_get_drvdata(pdev);
2753 if (!aes_dd)
2754 return -ENODEV;
2755 spin_lock(&atmel_aes.lock);
2756 list_del(&aes_dd->list);
2757 spin_unlock(&atmel_aes.lock);
2758
2759 atmel_aes_unregister_algs(aes_dd);
2760
2761 tasklet_kill(&aes_dd->done_task);
2762 tasklet_kill(&aes_dd->queue_task);
2763
2764 atmel_aes_dma_cleanup(aes_dd);
2765 atmel_aes_buff_cleanup(aes_dd);
2766
2767 clk_unprepare(aes_dd->iclk);
2768
2769 return 0;
2770 }
2771
2772 static struct platform_driver atmel_aes_driver = {
2773 .probe = atmel_aes_probe,
2774 .remove = atmel_aes_remove,
2775 .driver = {
2776 .name = "atmel_aes",
2777 .of_match_table = of_match_ptr(atmel_aes_dt_ids),
2778 },
2779 };
2780
2781 module_platform_driver(atmel_aes_driver);
2782
2783 MODULE_DESCRIPTION("Atmel AES hw acceleration support.");
2784 MODULE_LICENSE("GPL v2");
2785 MODULE_AUTHOR("Nicolas Royer - Eukréa Electromatique");
2786