1 /*
2 * Support functions for OMAP GPIO
3 *
4 * Copyright (C) 2003-2005 Nokia Corporation
5 * Written by Juha Yrjölä <juha.yrjola@nokia.com>
6 *
7 * Copyright (C) 2009 Texas Instruments
8 * Added OMAP4 support - Santosh Shilimkar <santosh.shilimkar@ti.com>
9 *
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License version 2 as
12 * published by the Free Software Foundation.
13 */
14
15 #include <linux/init.h>
16 #include <linux/module.h>
17 #include <linux/interrupt.h>
18 #include <linux/syscore_ops.h>
19 #include <linux/err.h>
20 #include <linux/clk.h>
21 #include <linux/io.h>
22 #include <linux/device.h>
23 #include <linux/pm_runtime.h>
24 #include <linux/pm.h>
25 #include <linux/of.h>
26 #include <linux/of_device.h>
27 #include <linux/gpio.h>
28 #include <linux/bitops.h>
29 #include <linux/platform_data/gpio-omap.h>
30
31 #define OFF_MODE 1
32 #define OMAP4_GPIO_DEBOUNCINGTIME_MASK 0xFF
33
34 static LIST_HEAD(omap_gpio_list);
35
36 struct gpio_regs {
37 u32 irqenable1;
38 u32 irqenable2;
39 u32 wake_en;
40 u32 ctrl;
41 u32 oe;
42 u32 leveldetect0;
43 u32 leveldetect1;
44 u32 risingdetect;
45 u32 fallingdetect;
46 u32 dataout;
47 u32 debounce;
48 u32 debounce_en;
49 };
50
51 struct gpio_bank {
52 struct list_head node;
53 void __iomem *base;
54 int irq;
55 u32 non_wakeup_gpios;
56 u32 enabled_non_wakeup_gpios;
57 struct gpio_regs context;
58 u32 saved_datain;
59 u32 level_mask;
60 u32 toggle_mask;
61 raw_spinlock_t lock;
62 raw_spinlock_t wa_lock;
63 struct gpio_chip chip;
64 struct clk *dbck;
65 u32 mod_usage;
66 u32 irq_usage;
67 u32 dbck_enable_mask;
68 bool dbck_enabled;
69 bool is_mpuio;
70 bool dbck_flag;
71 bool loses_context;
72 bool context_valid;
73 int stride;
74 u32 width;
75 int context_loss_count;
76 int power_mode;
77 bool workaround_enabled;
78
79 void (*set_dataout)(struct gpio_bank *bank, unsigned gpio, int enable);
80 int (*get_context_loss_count)(struct device *dev);
81
82 struct omap_gpio_reg_offs *regs;
83 };
84
85 #define GPIO_MOD_CTRL_BIT BIT(0)
86
87 #define BANK_USED(bank) (bank->mod_usage || bank->irq_usage)
88 #define LINE_USED(line, offset) (line & (BIT(offset)))
89
90 static void omap_gpio_unmask_irq(struct irq_data *d);
91
omap_irq_data_get_bank(struct irq_data * d)92 static inline struct gpio_bank *omap_irq_data_get_bank(struct irq_data *d)
93 {
94 struct gpio_chip *chip = irq_data_get_irq_chip_data(d);
95 return gpiochip_get_data(chip);
96 }
97
omap_set_gpio_direction(struct gpio_bank * bank,int gpio,int is_input)98 static void omap_set_gpio_direction(struct gpio_bank *bank, int gpio,
99 int is_input)
100 {
101 void __iomem *reg = bank->base;
102 u32 l;
103
104 reg += bank->regs->direction;
105 l = readl_relaxed(reg);
106 if (is_input)
107 l |= BIT(gpio);
108 else
109 l &= ~(BIT(gpio));
110 writel_relaxed(l, reg);
111 bank->context.oe = l;
112 }
113
114
115 /* set data out value using dedicate set/clear register */
omap_set_gpio_dataout_reg(struct gpio_bank * bank,unsigned offset,int enable)116 static void omap_set_gpio_dataout_reg(struct gpio_bank *bank, unsigned offset,
117 int enable)
118 {
119 void __iomem *reg = bank->base;
120 u32 l = BIT(offset);
121
122 if (enable) {
123 reg += bank->regs->set_dataout;
124 bank->context.dataout |= l;
125 } else {
126 reg += bank->regs->clr_dataout;
127 bank->context.dataout &= ~l;
128 }
129
130 writel_relaxed(l, reg);
131 }
132
133 /* set data out value using mask register */
omap_set_gpio_dataout_mask(struct gpio_bank * bank,unsigned offset,int enable)134 static void omap_set_gpio_dataout_mask(struct gpio_bank *bank, unsigned offset,
135 int enable)
136 {
137 void __iomem *reg = bank->base + bank->regs->dataout;
138 u32 gpio_bit = BIT(offset);
139 u32 l;
140
141 l = readl_relaxed(reg);
142 if (enable)
143 l |= gpio_bit;
144 else
145 l &= ~gpio_bit;
146 writel_relaxed(l, reg);
147 bank->context.dataout = l;
148 }
149
omap_get_gpio_datain(struct gpio_bank * bank,int offset)150 static int omap_get_gpio_datain(struct gpio_bank *bank, int offset)
151 {
152 void __iomem *reg = bank->base + bank->regs->datain;
153
154 return (readl_relaxed(reg) & (BIT(offset))) != 0;
155 }
156
omap_get_gpio_dataout(struct gpio_bank * bank,int offset)157 static int omap_get_gpio_dataout(struct gpio_bank *bank, int offset)
158 {
159 void __iomem *reg = bank->base + bank->regs->dataout;
160
161 return (readl_relaxed(reg) & (BIT(offset))) != 0;
162 }
163
omap_gpio_rmw(void __iomem * base,u32 reg,u32 mask,bool set)164 static inline void omap_gpio_rmw(void __iomem *base, u32 reg, u32 mask, bool set)
165 {
166 int l = readl_relaxed(base + reg);
167
168 if (set)
169 l |= mask;
170 else
171 l &= ~mask;
172
173 writel_relaxed(l, base + reg);
174 }
175
omap_gpio_dbck_enable(struct gpio_bank * bank)176 static inline void omap_gpio_dbck_enable(struct gpio_bank *bank)
177 {
178 if (bank->dbck_enable_mask && !bank->dbck_enabled) {
179 clk_enable(bank->dbck);
180 bank->dbck_enabled = true;
181
182 writel_relaxed(bank->dbck_enable_mask,
183 bank->base + bank->regs->debounce_en);
184 }
185 }
186
omap_gpio_dbck_disable(struct gpio_bank * bank)187 static inline void omap_gpio_dbck_disable(struct gpio_bank *bank)
188 {
189 if (bank->dbck_enable_mask && bank->dbck_enabled) {
190 /*
191 * Disable debounce before cutting it's clock. If debounce is
192 * enabled but the clock is not, GPIO module seems to be unable
193 * to detect events and generate interrupts at least on OMAP3.
194 */
195 writel_relaxed(0, bank->base + bank->regs->debounce_en);
196
197 clk_disable(bank->dbck);
198 bank->dbck_enabled = false;
199 }
200 }
201
202 /**
203 * omap2_set_gpio_debounce - low level gpio debounce time
204 * @bank: the gpio bank we're acting upon
205 * @offset: the gpio number on this @bank
206 * @debounce: debounce time to use
207 *
208 * OMAP's debounce time is in 31us steps
209 * <debounce time> = (GPIO_DEBOUNCINGTIME[7:0].DEBOUNCETIME + 1) x 31
210 * so we need to convert and round up to the closest unit.
211 *
212 * Return: 0 on success, negative error otherwise.
213 */
omap2_set_gpio_debounce(struct gpio_bank * bank,unsigned offset,unsigned debounce)214 static int omap2_set_gpio_debounce(struct gpio_bank *bank, unsigned offset,
215 unsigned debounce)
216 {
217 void __iomem *reg;
218 u32 val;
219 u32 l;
220 bool enable = !!debounce;
221
222 if (!bank->dbck_flag)
223 return -ENOTSUPP;
224
225 if (enable) {
226 debounce = DIV_ROUND_UP(debounce, 31) - 1;
227 if ((debounce & OMAP4_GPIO_DEBOUNCINGTIME_MASK) != debounce)
228 return -EINVAL;
229 }
230
231 l = BIT(offset);
232
233 clk_enable(bank->dbck);
234 reg = bank->base + bank->regs->debounce;
235 writel_relaxed(debounce, reg);
236
237 reg = bank->base + bank->regs->debounce_en;
238 val = readl_relaxed(reg);
239
240 if (enable)
241 val |= l;
242 else
243 val &= ~l;
244 bank->dbck_enable_mask = val;
245
246 writel_relaxed(val, reg);
247 clk_disable(bank->dbck);
248 /*
249 * Enable debounce clock per module.
250 * This call is mandatory because in omap_gpio_request() when
251 * *_runtime_get_sync() is called, _gpio_dbck_enable() within
252 * runtime callbck fails to turn on dbck because dbck_enable_mask
253 * used within _gpio_dbck_enable() is still not initialized at
254 * that point. Therefore we have to enable dbck here.
255 */
256 omap_gpio_dbck_enable(bank);
257 if (bank->dbck_enable_mask) {
258 bank->context.debounce = debounce;
259 bank->context.debounce_en = val;
260 }
261
262 return 0;
263 }
264
265 /**
266 * omap_clear_gpio_debounce - clear debounce settings for a gpio
267 * @bank: the gpio bank we're acting upon
268 * @offset: the gpio number on this @bank
269 *
270 * If a gpio is using debounce, then clear the debounce enable bit and if
271 * this is the only gpio in this bank using debounce, then clear the debounce
272 * time too. The debounce clock will also be disabled when calling this function
273 * if this is the only gpio in the bank using debounce.
274 */
omap_clear_gpio_debounce(struct gpio_bank * bank,unsigned offset)275 static void omap_clear_gpio_debounce(struct gpio_bank *bank, unsigned offset)
276 {
277 u32 gpio_bit = BIT(offset);
278
279 if (!bank->dbck_flag)
280 return;
281
282 if (!(bank->dbck_enable_mask & gpio_bit))
283 return;
284
285 bank->dbck_enable_mask &= ~gpio_bit;
286 bank->context.debounce_en &= ~gpio_bit;
287 writel_relaxed(bank->context.debounce_en,
288 bank->base + bank->regs->debounce_en);
289
290 if (!bank->dbck_enable_mask) {
291 bank->context.debounce = 0;
292 writel_relaxed(bank->context.debounce, bank->base +
293 bank->regs->debounce);
294 clk_disable(bank->dbck);
295 bank->dbck_enabled = false;
296 }
297 }
298
299 /*
300 * Off mode wake-up capable GPIOs in bank(s) that are in the wakeup domain.
301 * See TRM section for GPIO for "Wake-Up Generation" for the list of GPIOs
302 * in wakeup domain. If bank->non_wakeup_gpios is not configured, assume none
303 * are capable waking up the system from off mode.
304 */
omap_gpio_is_off_wakeup_capable(struct gpio_bank * bank,u32 gpio_mask)305 static bool omap_gpio_is_off_wakeup_capable(struct gpio_bank *bank, u32 gpio_mask)
306 {
307 u32 no_wake = bank->non_wakeup_gpios;
308
309 if (no_wake)
310 return !!(~no_wake & gpio_mask);
311
312 return false;
313 }
314
omap_set_gpio_trigger(struct gpio_bank * bank,int gpio,unsigned trigger)315 static inline void omap_set_gpio_trigger(struct gpio_bank *bank, int gpio,
316 unsigned trigger)
317 {
318 void __iomem *base = bank->base;
319 u32 gpio_bit = BIT(gpio);
320
321 omap_gpio_rmw(base, bank->regs->leveldetect0, gpio_bit,
322 trigger & IRQ_TYPE_LEVEL_LOW);
323 omap_gpio_rmw(base, bank->regs->leveldetect1, gpio_bit,
324 trigger & IRQ_TYPE_LEVEL_HIGH);
325 omap_gpio_rmw(base, bank->regs->risingdetect, gpio_bit,
326 trigger & IRQ_TYPE_EDGE_RISING);
327 omap_gpio_rmw(base, bank->regs->fallingdetect, gpio_bit,
328 trigger & IRQ_TYPE_EDGE_FALLING);
329
330 bank->context.leveldetect0 =
331 readl_relaxed(bank->base + bank->regs->leveldetect0);
332 bank->context.leveldetect1 =
333 readl_relaxed(bank->base + bank->regs->leveldetect1);
334 bank->context.risingdetect =
335 readl_relaxed(bank->base + bank->regs->risingdetect);
336 bank->context.fallingdetect =
337 readl_relaxed(bank->base + bank->regs->fallingdetect);
338
339 if (likely(!(bank->non_wakeup_gpios & gpio_bit))) {
340 omap_gpio_rmw(base, bank->regs->wkup_en, gpio_bit, trigger != 0);
341 bank->context.wake_en =
342 readl_relaxed(bank->base + bank->regs->wkup_en);
343 }
344
345 /* This part needs to be executed always for OMAP{34xx, 44xx} */
346 if (!bank->regs->irqctrl && !omap_gpio_is_off_wakeup_capable(bank, gpio)) {
347 /*
348 * Log the edge gpio and manually trigger the IRQ
349 * after resume if the input level changes
350 * to avoid irq lost during PER RET/OFF mode
351 * Applies for omap2 non-wakeup gpio and all omap3 gpios
352 */
353 if (trigger & IRQ_TYPE_EDGE_BOTH)
354 bank->enabled_non_wakeup_gpios |= gpio_bit;
355 else
356 bank->enabled_non_wakeup_gpios &= ~gpio_bit;
357 }
358
359 bank->level_mask =
360 readl_relaxed(bank->base + bank->regs->leveldetect0) |
361 readl_relaxed(bank->base + bank->regs->leveldetect1);
362 }
363
364 #ifdef CONFIG_ARCH_OMAP1
365 /*
366 * This only applies to chips that can't do both rising and falling edge
367 * detection at once. For all other chips, this function is a noop.
368 */
omap_toggle_gpio_edge_triggering(struct gpio_bank * bank,int gpio)369 static void omap_toggle_gpio_edge_triggering(struct gpio_bank *bank, int gpio)
370 {
371 void __iomem *reg = bank->base;
372 u32 l = 0;
373
374 if (!bank->regs->irqctrl)
375 return;
376
377 reg += bank->regs->irqctrl;
378
379 l = readl_relaxed(reg);
380 if ((l >> gpio) & 1)
381 l &= ~(BIT(gpio));
382 else
383 l |= BIT(gpio);
384
385 writel_relaxed(l, reg);
386 }
387 #else
omap_toggle_gpio_edge_triggering(struct gpio_bank * bank,int gpio)388 static void omap_toggle_gpio_edge_triggering(struct gpio_bank *bank, int gpio) {}
389 #endif
390
omap_set_gpio_triggering(struct gpio_bank * bank,int gpio,unsigned trigger)391 static int omap_set_gpio_triggering(struct gpio_bank *bank, int gpio,
392 unsigned trigger)
393 {
394 void __iomem *reg = bank->base;
395 void __iomem *base = bank->base;
396 u32 l = 0;
397
398 if (bank->regs->leveldetect0 && bank->regs->wkup_en) {
399 omap_set_gpio_trigger(bank, gpio, trigger);
400 } else if (bank->regs->irqctrl) {
401 reg += bank->regs->irqctrl;
402
403 l = readl_relaxed(reg);
404 if ((trigger & IRQ_TYPE_SENSE_MASK) == IRQ_TYPE_EDGE_BOTH)
405 bank->toggle_mask |= BIT(gpio);
406 if (trigger & IRQ_TYPE_EDGE_RISING)
407 l |= BIT(gpio);
408 else if (trigger & IRQ_TYPE_EDGE_FALLING)
409 l &= ~(BIT(gpio));
410 else
411 return -EINVAL;
412
413 writel_relaxed(l, reg);
414 } else if (bank->regs->edgectrl1) {
415 if (gpio & 0x08)
416 reg += bank->regs->edgectrl2;
417 else
418 reg += bank->regs->edgectrl1;
419
420 gpio &= 0x07;
421 l = readl_relaxed(reg);
422 l &= ~(3 << (gpio << 1));
423 if (trigger & IRQ_TYPE_EDGE_RISING)
424 l |= 2 << (gpio << 1);
425 if (trigger & IRQ_TYPE_EDGE_FALLING)
426 l |= BIT(gpio << 1);
427
428 /* Enable wake-up during idle for dynamic tick */
429 omap_gpio_rmw(base, bank->regs->wkup_en, BIT(gpio), trigger);
430 bank->context.wake_en =
431 readl_relaxed(bank->base + bank->regs->wkup_en);
432 writel_relaxed(l, reg);
433 }
434 return 0;
435 }
436
omap_enable_gpio_module(struct gpio_bank * bank,unsigned offset)437 static void omap_enable_gpio_module(struct gpio_bank *bank, unsigned offset)
438 {
439 if (bank->regs->pinctrl) {
440 void __iomem *reg = bank->base + bank->regs->pinctrl;
441
442 /* Claim the pin for MPU */
443 writel_relaxed(readl_relaxed(reg) | (BIT(offset)), reg);
444 }
445
446 if (bank->regs->ctrl && !BANK_USED(bank)) {
447 void __iomem *reg = bank->base + bank->regs->ctrl;
448 u32 ctrl;
449
450 ctrl = readl_relaxed(reg);
451 /* Module is enabled, clocks are not gated */
452 ctrl &= ~GPIO_MOD_CTRL_BIT;
453 writel_relaxed(ctrl, reg);
454 bank->context.ctrl = ctrl;
455 }
456 }
457
omap_disable_gpio_module(struct gpio_bank * bank,unsigned offset)458 static void omap_disable_gpio_module(struct gpio_bank *bank, unsigned offset)
459 {
460 void __iomem *base = bank->base;
461
462 if (bank->regs->wkup_en &&
463 !LINE_USED(bank->mod_usage, offset) &&
464 !LINE_USED(bank->irq_usage, offset)) {
465 /* Disable wake-up during idle for dynamic tick */
466 omap_gpio_rmw(base, bank->regs->wkup_en, BIT(offset), 0);
467 bank->context.wake_en =
468 readl_relaxed(bank->base + bank->regs->wkup_en);
469 }
470
471 if (bank->regs->ctrl && !BANK_USED(bank)) {
472 void __iomem *reg = bank->base + bank->regs->ctrl;
473 u32 ctrl;
474
475 ctrl = readl_relaxed(reg);
476 /* Module is disabled, clocks are gated */
477 ctrl |= GPIO_MOD_CTRL_BIT;
478 writel_relaxed(ctrl, reg);
479 bank->context.ctrl = ctrl;
480 }
481 }
482
omap_gpio_is_input(struct gpio_bank * bank,unsigned offset)483 static int omap_gpio_is_input(struct gpio_bank *bank, unsigned offset)
484 {
485 void __iomem *reg = bank->base + bank->regs->direction;
486
487 return readl_relaxed(reg) & BIT(offset);
488 }
489
omap_gpio_init_irq(struct gpio_bank * bank,unsigned offset)490 static void omap_gpio_init_irq(struct gpio_bank *bank, unsigned offset)
491 {
492 if (!LINE_USED(bank->mod_usage, offset)) {
493 omap_enable_gpio_module(bank, offset);
494 omap_set_gpio_direction(bank, offset, 1);
495 }
496 bank->irq_usage |= BIT(offset);
497 }
498
omap_gpio_irq_type(struct irq_data * d,unsigned type)499 static int omap_gpio_irq_type(struct irq_data *d, unsigned type)
500 {
501 struct gpio_bank *bank = omap_irq_data_get_bank(d);
502 int retval;
503 unsigned long flags;
504 unsigned offset = d->hwirq;
505
506 if (type & ~IRQ_TYPE_SENSE_MASK)
507 return -EINVAL;
508
509 if (!bank->regs->leveldetect0 &&
510 (type & (IRQ_TYPE_LEVEL_LOW|IRQ_TYPE_LEVEL_HIGH)))
511 return -EINVAL;
512
513 raw_spin_lock_irqsave(&bank->lock, flags);
514 retval = omap_set_gpio_triggering(bank, offset, type);
515 if (retval) {
516 raw_spin_unlock_irqrestore(&bank->lock, flags);
517 goto error;
518 }
519 omap_gpio_init_irq(bank, offset);
520 if (!omap_gpio_is_input(bank, offset)) {
521 raw_spin_unlock_irqrestore(&bank->lock, flags);
522 retval = -EINVAL;
523 goto error;
524 }
525 raw_spin_unlock_irqrestore(&bank->lock, flags);
526
527 if (type & (IRQ_TYPE_LEVEL_LOW | IRQ_TYPE_LEVEL_HIGH))
528 irq_set_handler_locked(d, handle_level_irq);
529 else if (type & (IRQ_TYPE_EDGE_FALLING | IRQ_TYPE_EDGE_RISING))
530 /*
531 * Edge IRQs are already cleared/acked in irq_handler and
532 * not need to be masked, as result handle_edge_irq()
533 * logic is excessed here and may cause lose of interrupts.
534 * So just use handle_simple_irq.
535 */
536 irq_set_handler_locked(d, handle_simple_irq);
537
538 return 0;
539
540 error:
541 return retval;
542 }
543
omap_clear_gpio_irqbank(struct gpio_bank * bank,int gpio_mask)544 static void omap_clear_gpio_irqbank(struct gpio_bank *bank, int gpio_mask)
545 {
546 void __iomem *reg = bank->base;
547
548 reg += bank->regs->irqstatus;
549 writel_relaxed(gpio_mask, reg);
550
551 /* Workaround for clearing DSP GPIO interrupts to allow retention */
552 if (bank->regs->irqstatus2) {
553 reg = bank->base + bank->regs->irqstatus2;
554 writel_relaxed(gpio_mask, reg);
555 }
556
557 /* Flush posted write for the irq status to avoid spurious interrupts */
558 readl_relaxed(reg);
559 }
560
omap_clear_gpio_irqstatus(struct gpio_bank * bank,unsigned offset)561 static inline void omap_clear_gpio_irqstatus(struct gpio_bank *bank,
562 unsigned offset)
563 {
564 omap_clear_gpio_irqbank(bank, BIT(offset));
565 }
566
omap_get_gpio_irqbank_mask(struct gpio_bank * bank)567 static u32 omap_get_gpio_irqbank_mask(struct gpio_bank *bank)
568 {
569 void __iomem *reg = bank->base;
570 u32 l;
571 u32 mask = (BIT(bank->width)) - 1;
572
573 reg += bank->regs->irqenable;
574 l = readl_relaxed(reg);
575 if (bank->regs->irqenable_inv)
576 l = ~l;
577 l &= mask;
578 return l;
579 }
580
omap_enable_gpio_irqbank(struct gpio_bank * bank,int gpio_mask)581 static void omap_enable_gpio_irqbank(struct gpio_bank *bank, int gpio_mask)
582 {
583 void __iomem *reg = bank->base;
584 u32 l;
585
586 if (bank->regs->set_irqenable) {
587 reg += bank->regs->set_irqenable;
588 l = gpio_mask;
589 bank->context.irqenable1 |= gpio_mask;
590 } else {
591 reg += bank->regs->irqenable;
592 l = readl_relaxed(reg);
593 if (bank->regs->irqenable_inv)
594 l &= ~gpio_mask;
595 else
596 l |= gpio_mask;
597 bank->context.irqenable1 = l;
598 }
599
600 writel_relaxed(l, reg);
601 }
602
omap_disable_gpio_irqbank(struct gpio_bank * bank,int gpio_mask)603 static void omap_disable_gpio_irqbank(struct gpio_bank *bank, int gpio_mask)
604 {
605 void __iomem *reg = bank->base;
606 u32 l;
607
608 if (bank->regs->clr_irqenable) {
609 reg += bank->regs->clr_irqenable;
610 l = gpio_mask;
611 bank->context.irqenable1 &= ~gpio_mask;
612 } else {
613 reg += bank->regs->irqenable;
614 l = readl_relaxed(reg);
615 if (bank->regs->irqenable_inv)
616 l |= gpio_mask;
617 else
618 l &= ~gpio_mask;
619 bank->context.irqenable1 = l;
620 }
621
622 writel_relaxed(l, reg);
623 }
624
omap_set_gpio_irqenable(struct gpio_bank * bank,unsigned offset,int enable)625 static inline void omap_set_gpio_irqenable(struct gpio_bank *bank,
626 unsigned offset, int enable)
627 {
628 if (enable)
629 omap_enable_gpio_irqbank(bank, BIT(offset));
630 else
631 omap_disable_gpio_irqbank(bank, BIT(offset));
632 }
633
634 /* Use disable_irq_wake() and enable_irq_wake() functions from drivers */
omap_gpio_wake_enable(struct irq_data * d,unsigned int enable)635 static int omap_gpio_wake_enable(struct irq_data *d, unsigned int enable)
636 {
637 struct gpio_bank *bank = omap_irq_data_get_bank(d);
638
639 return irq_set_irq_wake(bank->irq, enable);
640 }
641
omap_gpio_request(struct gpio_chip * chip,unsigned offset)642 static int omap_gpio_request(struct gpio_chip *chip, unsigned offset)
643 {
644 struct gpio_bank *bank = gpiochip_get_data(chip);
645 unsigned long flags;
646
647 /*
648 * If this is the first gpio_request for the bank,
649 * enable the bank module.
650 */
651 if (!BANK_USED(bank))
652 pm_runtime_get_sync(chip->parent);
653
654 raw_spin_lock_irqsave(&bank->lock, flags);
655 omap_enable_gpio_module(bank, offset);
656 bank->mod_usage |= BIT(offset);
657 raw_spin_unlock_irqrestore(&bank->lock, flags);
658
659 return 0;
660 }
661
omap_gpio_free(struct gpio_chip * chip,unsigned offset)662 static void omap_gpio_free(struct gpio_chip *chip, unsigned offset)
663 {
664 struct gpio_bank *bank = gpiochip_get_data(chip);
665 unsigned long flags;
666
667 raw_spin_lock_irqsave(&bank->lock, flags);
668 bank->mod_usage &= ~(BIT(offset));
669 if (!LINE_USED(bank->irq_usage, offset)) {
670 omap_set_gpio_direction(bank, offset, 1);
671 omap_clear_gpio_debounce(bank, offset);
672 }
673 omap_disable_gpio_module(bank, offset);
674 raw_spin_unlock_irqrestore(&bank->lock, flags);
675
676 /*
677 * If this is the last gpio to be freed in the bank,
678 * disable the bank module.
679 */
680 if (!BANK_USED(bank))
681 pm_runtime_put(chip->parent);
682 }
683
684 /*
685 * We need to unmask the GPIO bank interrupt as soon as possible to
686 * avoid missing GPIO interrupts for other lines in the bank.
687 * Then we need to mask-read-clear-unmask the triggered GPIO lines
688 * in the bank to avoid missing nested interrupts for a GPIO line.
689 * If we wait to unmask individual GPIO lines in the bank after the
690 * line's interrupt handler has been run, we may miss some nested
691 * interrupts.
692 */
omap_gpio_irq_handler(int irq,void * gpiobank)693 static irqreturn_t omap_gpio_irq_handler(int irq, void *gpiobank)
694 {
695 void __iomem *isr_reg = NULL;
696 u32 enabled, isr, level_mask;
697 unsigned int bit;
698 struct gpio_bank *bank = gpiobank;
699 unsigned long wa_lock_flags;
700 unsigned long lock_flags;
701
702 isr_reg = bank->base + bank->regs->irqstatus;
703 if (WARN_ON(!isr_reg))
704 goto exit;
705
706 pm_runtime_get_sync(bank->chip.parent);
707
708 while (1) {
709 raw_spin_lock_irqsave(&bank->lock, lock_flags);
710
711 enabled = omap_get_gpio_irqbank_mask(bank);
712 isr = readl_relaxed(isr_reg) & enabled;
713
714 if (bank->level_mask)
715 level_mask = bank->level_mask & enabled;
716 else
717 level_mask = 0;
718
719 /* clear edge sensitive interrupts before handler(s) are
720 called so that we don't miss any interrupt occurred while
721 executing them */
722 if (isr & ~level_mask)
723 omap_clear_gpio_irqbank(bank, isr & ~level_mask);
724
725 raw_spin_unlock_irqrestore(&bank->lock, lock_flags);
726
727 if (!isr)
728 break;
729
730 while (isr) {
731 bit = __ffs(isr);
732 isr &= ~(BIT(bit));
733
734 raw_spin_lock_irqsave(&bank->lock, lock_flags);
735 /*
736 * Some chips can't respond to both rising and falling
737 * at the same time. If this irq was requested with
738 * both flags, we need to flip the ICR data for the IRQ
739 * to respond to the IRQ for the opposite direction.
740 * This will be indicated in the bank toggle_mask.
741 */
742 if (bank->toggle_mask & (BIT(bit)))
743 omap_toggle_gpio_edge_triggering(bank, bit);
744
745 raw_spin_unlock_irqrestore(&bank->lock, lock_flags);
746
747 raw_spin_lock_irqsave(&bank->wa_lock, wa_lock_flags);
748
749 generic_handle_irq(irq_find_mapping(bank->chip.irqdomain,
750 bit));
751
752 raw_spin_unlock_irqrestore(&bank->wa_lock,
753 wa_lock_flags);
754 }
755 }
756 exit:
757 pm_runtime_put(bank->chip.parent);
758 return IRQ_HANDLED;
759 }
760
omap_gpio_irq_startup(struct irq_data * d)761 static unsigned int omap_gpio_irq_startup(struct irq_data *d)
762 {
763 struct gpio_bank *bank = omap_irq_data_get_bank(d);
764 unsigned long flags;
765 unsigned offset = d->hwirq;
766
767 raw_spin_lock_irqsave(&bank->lock, flags);
768
769 if (!LINE_USED(bank->mod_usage, offset))
770 omap_set_gpio_direction(bank, offset, 1);
771 else if (!omap_gpio_is_input(bank, offset))
772 goto err;
773 omap_enable_gpio_module(bank, offset);
774 bank->irq_usage |= BIT(offset);
775
776 raw_spin_unlock_irqrestore(&bank->lock, flags);
777 omap_gpio_unmask_irq(d);
778
779 return 0;
780 err:
781 raw_spin_unlock_irqrestore(&bank->lock, flags);
782 return -EINVAL;
783 }
784
omap_gpio_irq_shutdown(struct irq_data * d)785 static void omap_gpio_irq_shutdown(struct irq_data *d)
786 {
787 struct gpio_bank *bank = omap_irq_data_get_bank(d);
788 unsigned long flags;
789 unsigned offset = d->hwirq;
790
791 raw_spin_lock_irqsave(&bank->lock, flags);
792 bank->irq_usage &= ~(BIT(offset));
793 omap_set_gpio_triggering(bank, offset, IRQ_TYPE_NONE);
794 omap_clear_gpio_irqstatus(bank, offset);
795 omap_set_gpio_irqenable(bank, offset, 0);
796 if (!LINE_USED(bank->mod_usage, offset))
797 omap_clear_gpio_debounce(bank, offset);
798 omap_disable_gpio_module(bank, offset);
799 raw_spin_unlock_irqrestore(&bank->lock, flags);
800 }
801
omap_gpio_irq_bus_lock(struct irq_data * data)802 static void omap_gpio_irq_bus_lock(struct irq_data *data)
803 {
804 struct gpio_bank *bank = omap_irq_data_get_bank(data);
805
806 if (!BANK_USED(bank))
807 pm_runtime_get_sync(bank->chip.parent);
808 }
809
gpio_irq_bus_sync_unlock(struct irq_data * data)810 static void gpio_irq_bus_sync_unlock(struct irq_data *data)
811 {
812 struct gpio_bank *bank = omap_irq_data_get_bank(data);
813
814 /*
815 * If this is the last IRQ to be freed in the bank,
816 * disable the bank module.
817 */
818 if (!BANK_USED(bank))
819 pm_runtime_put(bank->chip.parent);
820 }
821
omap_gpio_ack_irq(struct irq_data * d)822 static void omap_gpio_ack_irq(struct irq_data *d)
823 {
824 struct gpio_bank *bank = omap_irq_data_get_bank(d);
825 unsigned offset = d->hwirq;
826
827 omap_clear_gpio_irqstatus(bank, offset);
828 }
829
omap_gpio_mask_irq(struct irq_data * d)830 static void omap_gpio_mask_irq(struct irq_data *d)
831 {
832 struct gpio_bank *bank = omap_irq_data_get_bank(d);
833 unsigned offset = d->hwirq;
834 unsigned long flags;
835
836 raw_spin_lock_irqsave(&bank->lock, flags);
837 omap_set_gpio_triggering(bank, offset, IRQ_TYPE_NONE);
838 omap_set_gpio_irqenable(bank, offset, 0);
839 raw_spin_unlock_irqrestore(&bank->lock, flags);
840 }
841
omap_gpio_unmask_irq(struct irq_data * d)842 static void omap_gpio_unmask_irq(struct irq_data *d)
843 {
844 struct gpio_bank *bank = omap_irq_data_get_bank(d);
845 unsigned offset = d->hwirq;
846 u32 trigger = irqd_get_trigger_type(d);
847 unsigned long flags;
848
849 raw_spin_lock_irqsave(&bank->lock, flags);
850 omap_set_gpio_irqenable(bank, offset, 1);
851
852 /*
853 * For level-triggered GPIOs, clearing must be done after the source
854 * is cleared, thus after the handler has run. OMAP4 needs this done
855 * after enabing the interrupt to clear the wakeup status.
856 */
857 if (bank->regs->leveldetect0 && bank->regs->wkup_en &&
858 trigger & (IRQ_TYPE_LEVEL_HIGH | IRQ_TYPE_LEVEL_LOW))
859 omap_clear_gpio_irqstatus(bank, offset);
860
861 if (trigger)
862 omap_set_gpio_triggering(bank, offset, trigger);
863
864 raw_spin_unlock_irqrestore(&bank->lock, flags);
865 }
866
867 /*---------------------------------------------------------------------*/
868
omap_mpuio_suspend_noirq(struct device * dev)869 static int omap_mpuio_suspend_noirq(struct device *dev)
870 {
871 struct platform_device *pdev = to_platform_device(dev);
872 struct gpio_bank *bank = platform_get_drvdata(pdev);
873 void __iomem *mask_reg = bank->base +
874 OMAP_MPUIO_GPIO_MASKIT / bank->stride;
875 unsigned long flags;
876
877 raw_spin_lock_irqsave(&bank->lock, flags);
878 writel_relaxed(0xffff & ~bank->context.wake_en, mask_reg);
879 raw_spin_unlock_irqrestore(&bank->lock, flags);
880
881 return 0;
882 }
883
omap_mpuio_resume_noirq(struct device * dev)884 static int omap_mpuio_resume_noirq(struct device *dev)
885 {
886 struct platform_device *pdev = to_platform_device(dev);
887 struct gpio_bank *bank = platform_get_drvdata(pdev);
888 void __iomem *mask_reg = bank->base +
889 OMAP_MPUIO_GPIO_MASKIT / bank->stride;
890 unsigned long flags;
891
892 raw_spin_lock_irqsave(&bank->lock, flags);
893 writel_relaxed(bank->context.wake_en, mask_reg);
894 raw_spin_unlock_irqrestore(&bank->lock, flags);
895
896 return 0;
897 }
898
899 static const struct dev_pm_ops omap_mpuio_dev_pm_ops = {
900 .suspend_noirq = omap_mpuio_suspend_noirq,
901 .resume_noirq = omap_mpuio_resume_noirq,
902 };
903
904 /* use platform_driver for this. */
905 static struct platform_driver omap_mpuio_driver = {
906 .driver = {
907 .name = "mpuio",
908 .pm = &omap_mpuio_dev_pm_ops,
909 },
910 };
911
912 static struct platform_device omap_mpuio_device = {
913 .name = "mpuio",
914 .id = -1,
915 .dev = {
916 .driver = &omap_mpuio_driver.driver,
917 }
918 /* could list the /proc/iomem resources */
919 };
920
omap_mpuio_init(struct gpio_bank * bank)921 static inline void omap_mpuio_init(struct gpio_bank *bank)
922 {
923 platform_set_drvdata(&omap_mpuio_device, bank);
924
925 if (platform_driver_register(&omap_mpuio_driver) == 0)
926 (void) platform_device_register(&omap_mpuio_device);
927 }
928
929 /*---------------------------------------------------------------------*/
930
omap_gpio_get_direction(struct gpio_chip * chip,unsigned offset)931 static int omap_gpio_get_direction(struct gpio_chip *chip, unsigned offset)
932 {
933 struct gpio_bank *bank;
934 unsigned long flags;
935 void __iomem *reg;
936 int dir;
937
938 bank = gpiochip_get_data(chip);
939 reg = bank->base + bank->regs->direction;
940 raw_spin_lock_irqsave(&bank->lock, flags);
941 dir = !!(readl_relaxed(reg) & BIT(offset));
942 raw_spin_unlock_irqrestore(&bank->lock, flags);
943 return dir;
944 }
945
omap_gpio_input(struct gpio_chip * chip,unsigned offset)946 static int omap_gpio_input(struct gpio_chip *chip, unsigned offset)
947 {
948 struct gpio_bank *bank;
949 unsigned long flags;
950
951 bank = gpiochip_get_data(chip);
952 raw_spin_lock_irqsave(&bank->lock, flags);
953 omap_set_gpio_direction(bank, offset, 1);
954 raw_spin_unlock_irqrestore(&bank->lock, flags);
955 return 0;
956 }
957
omap_gpio_get(struct gpio_chip * chip,unsigned offset)958 static int omap_gpio_get(struct gpio_chip *chip, unsigned offset)
959 {
960 struct gpio_bank *bank;
961
962 bank = gpiochip_get_data(chip);
963
964 if (omap_gpio_is_input(bank, offset))
965 return omap_get_gpio_datain(bank, offset);
966 else
967 return omap_get_gpio_dataout(bank, offset);
968 }
969
omap_gpio_output(struct gpio_chip * chip,unsigned offset,int value)970 static int omap_gpio_output(struct gpio_chip *chip, unsigned offset, int value)
971 {
972 struct gpio_bank *bank;
973 unsigned long flags;
974
975 bank = gpiochip_get_data(chip);
976 raw_spin_lock_irqsave(&bank->lock, flags);
977 bank->set_dataout(bank, offset, value);
978 omap_set_gpio_direction(bank, offset, 0);
979 raw_spin_unlock_irqrestore(&bank->lock, flags);
980 return 0;
981 }
982
omap_gpio_debounce(struct gpio_chip * chip,unsigned offset,unsigned debounce)983 static int omap_gpio_debounce(struct gpio_chip *chip, unsigned offset,
984 unsigned debounce)
985 {
986 struct gpio_bank *bank;
987 unsigned long flags;
988 int ret;
989
990 bank = gpiochip_get_data(chip);
991
992 raw_spin_lock_irqsave(&bank->lock, flags);
993 ret = omap2_set_gpio_debounce(bank, offset, debounce);
994 raw_spin_unlock_irqrestore(&bank->lock, flags);
995
996 if (ret)
997 dev_info(chip->parent,
998 "Could not set line %u debounce to %u microseconds (%d)",
999 offset, debounce, ret);
1000
1001 return ret;
1002 }
1003
omap_gpio_set_config(struct gpio_chip * chip,unsigned offset,unsigned long config)1004 static int omap_gpio_set_config(struct gpio_chip *chip, unsigned offset,
1005 unsigned long config)
1006 {
1007 u32 debounce;
1008
1009 if (pinconf_to_config_param(config) != PIN_CONFIG_INPUT_DEBOUNCE)
1010 return -ENOTSUPP;
1011
1012 debounce = pinconf_to_config_argument(config);
1013 return omap_gpio_debounce(chip, offset, debounce);
1014 }
1015
omap_gpio_set(struct gpio_chip * chip,unsigned offset,int value)1016 static void omap_gpio_set(struct gpio_chip *chip, unsigned offset, int value)
1017 {
1018 struct gpio_bank *bank;
1019 unsigned long flags;
1020
1021 bank = gpiochip_get_data(chip);
1022 raw_spin_lock_irqsave(&bank->lock, flags);
1023 bank->set_dataout(bank, offset, value);
1024 raw_spin_unlock_irqrestore(&bank->lock, flags);
1025 }
1026
1027 /*---------------------------------------------------------------------*/
1028
omap_gpio_show_rev(struct gpio_bank * bank)1029 static void omap_gpio_show_rev(struct gpio_bank *bank)
1030 {
1031 static bool called;
1032 u32 rev;
1033
1034 if (called || bank->regs->revision == USHRT_MAX)
1035 return;
1036
1037 rev = readw_relaxed(bank->base + bank->regs->revision);
1038 pr_info("OMAP GPIO hardware version %d.%d\n",
1039 (rev >> 4) & 0x0f, rev & 0x0f);
1040
1041 called = true;
1042 }
1043
omap_gpio_mod_init(struct gpio_bank * bank)1044 static void omap_gpio_mod_init(struct gpio_bank *bank)
1045 {
1046 void __iomem *base = bank->base;
1047 u32 l = 0xffffffff;
1048
1049 if (bank->width == 16)
1050 l = 0xffff;
1051
1052 if (bank->is_mpuio) {
1053 writel_relaxed(l, bank->base + bank->regs->irqenable);
1054 return;
1055 }
1056
1057 omap_gpio_rmw(base, bank->regs->irqenable, l,
1058 bank->regs->irqenable_inv);
1059 omap_gpio_rmw(base, bank->regs->irqstatus, l,
1060 !bank->regs->irqenable_inv);
1061 if (bank->regs->debounce_en)
1062 writel_relaxed(0, base + bank->regs->debounce_en);
1063
1064 /* Save OE default value (0xffffffff) in the context */
1065 bank->context.oe = readl_relaxed(bank->base + bank->regs->direction);
1066 /* Initialize interface clk ungated, module enabled */
1067 if (bank->regs->ctrl)
1068 writel_relaxed(0, base + bank->regs->ctrl);
1069 }
1070
omap_gpio_chip_init(struct gpio_bank * bank,struct irq_chip * irqc)1071 static int omap_gpio_chip_init(struct gpio_bank *bank, struct irq_chip *irqc)
1072 {
1073 static int gpio;
1074 int irq_base = 0;
1075 int ret;
1076
1077 /*
1078 * REVISIT eventually switch from OMAP-specific gpio structs
1079 * over to the generic ones
1080 */
1081 bank->chip.request = omap_gpio_request;
1082 bank->chip.free = omap_gpio_free;
1083 bank->chip.get_direction = omap_gpio_get_direction;
1084 bank->chip.direction_input = omap_gpio_input;
1085 bank->chip.get = omap_gpio_get;
1086 bank->chip.direction_output = omap_gpio_output;
1087 bank->chip.set_config = omap_gpio_set_config;
1088 bank->chip.set = omap_gpio_set;
1089 if (bank->is_mpuio) {
1090 bank->chip.label = "mpuio";
1091 if (bank->regs->wkup_en)
1092 bank->chip.parent = &omap_mpuio_device.dev;
1093 bank->chip.base = OMAP_MPUIO(0);
1094 } else {
1095 bank->chip.label = "gpio";
1096 bank->chip.base = gpio;
1097 }
1098 bank->chip.ngpio = bank->width;
1099
1100 ret = gpiochip_add_data(&bank->chip, bank);
1101 if (ret) {
1102 dev_err(bank->chip.parent,
1103 "Could not register gpio chip %d\n", ret);
1104 return ret;
1105 }
1106
1107 if (!bank->is_mpuio)
1108 gpio += bank->width;
1109
1110 #ifdef CONFIG_ARCH_OMAP1
1111 /*
1112 * REVISIT: Once we have OMAP1 supporting SPARSE_IRQ, we can drop
1113 * irq_alloc_descs() since a base IRQ offset will no longer be needed.
1114 */
1115 irq_base = devm_irq_alloc_descs(bank->chip.parent,
1116 -1, 0, bank->width, 0);
1117 if (irq_base < 0) {
1118 dev_err(bank->chip.parent, "Couldn't allocate IRQ numbers\n");
1119 return -ENODEV;
1120 }
1121 #endif
1122
1123 /* MPUIO is a bit different, reading IRQ status clears it */
1124 if (bank->is_mpuio) {
1125 irqc->irq_ack = dummy_irq_chip.irq_ack;
1126 if (!bank->regs->wkup_en)
1127 irqc->irq_set_wake = NULL;
1128 }
1129
1130 ret = gpiochip_irqchip_add(&bank->chip, irqc,
1131 irq_base, handle_bad_irq,
1132 IRQ_TYPE_NONE);
1133
1134 if (ret) {
1135 dev_err(bank->chip.parent,
1136 "Couldn't add irqchip to gpiochip %d\n", ret);
1137 gpiochip_remove(&bank->chip);
1138 return -ENODEV;
1139 }
1140
1141 gpiochip_set_chained_irqchip(&bank->chip, irqc, bank->irq, NULL);
1142
1143 ret = devm_request_irq(bank->chip.parent, bank->irq,
1144 omap_gpio_irq_handler,
1145 0, dev_name(bank->chip.parent), bank);
1146 if (ret)
1147 gpiochip_remove(&bank->chip);
1148
1149 return ret;
1150 }
1151
1152 static const struct of_device_id omap_gpio_match[];
1153
omap_gpio_probe(struct platform_device * pdev)1154 static int omap_gpio_probe(struct platform_device *pdev)
1155 {
1156 struct device *dev = &pdev->dev;
1157 struct device_node *node = dev->of_node;
1158 const struct of_device_id *match;
1159 const struct omap_gpio_platform_data *pdata;
1160 struct resource *res;
1161 struct gpio_bank *bank;
1162 struct irq_chip *irqc;
1163 int ret;
1164
1165 match = of_match_device(of_match_ptr(omap_gpio_match), dev);
1166
1167 pdata = match ? match->data : dev_get_platdata(dev);
1168 if (!pdata)
1169 return -EINVAL;
1170
1171 bank = devm_kzalloc(dev, sizeof(struct gpio_bank), GFP_KERNEL);
1172 if (!bank) {
1173 dev_err(dev, "Memory alloc failed\n");
1174 return -ENOMEM;
1175 }
1176
1177 irqc = devm_kzalloc(dev, sizeof(*irqc), GFP_KERNEL);
1178 if (!irqc)
1179 return -ENOMEM;
1180
1181 irqc->irq_startup = omap_gpio_irq_startup,
1182 irqc->irq_shutdown = omap_gpio_irq_shutdown,
1183 irqc->irq_ack = omap_gpio_ack_irq,
1184 irqc->irq_mask = omap_gpio_mask_irq,
1185 irqc->irq_unmask = omap_gpio_unmask_irq,
1186 irqc->irq_set_type = omap_gpio_irq_type,
1187 irqc->irq_set_wake = omap_gpio_wake_enable,
1188 irqc->irq_bus_lock = omap_gpio_irq_bus_lock,
1189 irqc->irq_bus_sync_unlock = gpio_irq_bus_sync_unlock,
1190 irqc->name = dev_name(&pdev->dev);
1191 irqc->flags = IRQCHIP_MASK_ON_SUSPEND;
1192
1193 bank->irq = platform_get_irq(pdev, 0);
1194 if (bank->irq <= 0) {
1195 if (!bank->irq)
1196 bank->irq = -ENXIO;
1197 if (bank->irq != -EPROBE_DEFER)
1198 dev_err(dev,
1199 "can't get irq resource ret=%d\n", bank->irq);
1200 return bank->irq;
1201 }
1202
1203 bank->chip.parent = dev;
1204 bank->chip.owner = THIS_MODULE;
1205 bank->dbck_flag = pdata->dbck_flag;
1206 bank->stride = pdata->bank_stride;
1207 bank->width = pdata->bank_width;
1208 bank->is_mpuio = pdata->is_mpuio;
1209 bank->non_wakeup_gpios = pdata->non_wakeup_gpios;
1210 bank->regs = pdata->regs;
1211 #ifdef CONFIG_OF_GPIO
1212 bank->chip.of_node = of_node_get(node);
1213 #endif
1214 if (node) {
1215 if (!of_property_read_bool(node, "ti,gpio-always-on"))
1216 bank->loses_context = true;
1217 } else {
1218 bank->loses_context = pdata->loses_context;
1219
1220 if (bank->loses_context)
1221 bank->get_context_loss_count =
1222 pdata->get_context_loss_count;
1223 }
1224
1225 if (bank->regs->set_dataout && bank->regs->clr_dataout)
1226 bank->set_dataout = omap_set_gpio_dataout_reg;
1227 else
1228 bank->set_dataout = omap_set_gpio_dataout_mask;
1229
1230 raw_spin_lock_init(&bank->lock);
1231 raw_spin_lock_init(&bank->wa_lock);
1232
1233 /* Static mapping, never released */
1234 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1235 bank->base = devm_ioremap_resource(dev, res);
1236 if (IS_ERR(bank->base)) {
1237 return PTR_ERR(bank->base);
1238 }
1239
1240 if (bank->dbck_flag) {
1241 bank->dbck = devm_clk_get(dev, "dbclk");
1242 if (IS_ERR(bank->dbck)) {
1243 dev_err(dev,
1244 "Could not get gpio dbck. Disable debounce\n");
1245 bank->dbck_flag = false;
1246 } else {
1247 clk_prepare(bank->dbck);
1248 }
1249 }
1250
1251 platform_set_drvdata(pdev, bank);
1252
1253 pm_runtime_enable(dev);
1254 pm_runtime_irq_safe(dev);
1255 pm_runtime_get_sync(dev);
1256
1257 if (bank->is_mpuio)
1258 omap_mpuio_init(bank);
1259
1260 omap_gpio_mod_init(bank);
1261
1262 ret = omap_gpio_chip_init(bank, irqc);
1263 if (ret) {
1264 pm_runtime_put_sync(dev);
1265 pm_runtime_disable(dev);
1266 if (bank->dbck_flag)
1267 clk_unprepare(bank->dbck);
1268 return ret;
1269 }
1270
1271 omap_gpio_show_rev(bank);
1272
1273 pm_runtime_put(dev);
1274
1275 list_add_tail(&bank->node, &omap_gpio_list);
1276
1277 return 0;
1278 }
1279
omap_gpio_remove(struct platform_device * pdev)1280 static int omap_gpio_remove(struct platform_device *pdev)
1281 {
1282 struct gpio_bank *bank = platform_get_drvdata(pdev);
1283
1284 list_del(&bank->node);
1285 gpiochip_remove(&bank->chip);
1286 pm_runtime_disable(&pdev->dev);
1287 if (bank->dbck_flag)
1288 clk_unprepare(bank->dbck);
1289
1290 return 0;
1291 }
1292
1293 #ifdef CONFIG_ARCH_OMAP2PLUS
1294
1295 #if defined(CONFIG_PM)
1296 static void omap_gpio_restore_context(struct gpio_bank *bank);
1297
omap_gpio_runtime_suspend(struct device * dev)1298 static int omap_gpio_runtime_suspend(struct device *dev)
1299 {
1300 struct platform_device *pdev = to_platform_device(dev);
1301 struct gpio_bank *bank = platform_get_drvdata(pdev);
1302 u32 l1 = 0, l2 = 0;
1303 unsigned long flags;
1304 u32 wake_low, wake_hi;
1305
1306 raw_spin_lock_irqsave(&bank->lock, flags);
1307
1308 /*
1309 * Only edges can generate a wakeup event to the PRCM.
1310 *
1311 * Therefore, ensure any wake-up capable GPIOs have
1312 * edge-detection enabled before going idle to ensure a wakeup
1313 * to the PRCM is generated on a GPIO transition. (c.f. 34xx
1314 * NDA TRM 25.5.3.1)
1315 *
1316 * The normal values will be restored upon ->runtime_resume()
1317 * by writing back the values saved in bank->context.
1318 */
1319 wake_low = bank->context.leveldetect0 & bank->context.wake_en;
1320 if (wake_low)
1321 writel_relaxed(wake_low | bank->context.fallingdetect,
1322 bank->base + bank->regs->fallingdetect);
1323 wake_hi = bank->context.leveldetect1 & bank->context.wake_en;
1324 if (wake_hi)
1325 writel_relaxed(wake_hi | bank->context.risingdetect,
1326 bank->base + bank->regs->risingdetect);
1327
1328 if (!bank->enabled_non_wakeup_gpios)
1329 goto update_gpio_context_count;
1330
1331 if (bank->power_mode != OFF_MODE) {
1332 bank->power_mode = 0;
1333 goto update_gpio_context_count;
1334 }
1335 /*
1336 * If going to OFF, remove triggering for all
1337 * non-wakeup GPIOs. Otherwise spurious IRQs will be
1338 * generated. See OMAP2420 Errata item 1.101.
1339 */
1340 bank->saved_datain = readl_relaxed(bank->base +
1341 bank->regs->datain);
1342 l1 = bank->context.fallingdetect;
1343 l2 = bank->context.risingdetect;
1344
1345 l1 &= ~bank->enabled_non_wakeup_gpios;
1346 l2 &= ~bank->enabled_non_wakeup_gpios;
1347
1348 writel_relaxed(l1, bank->base + bank->regs->fallingdetect);
1349 writel_relaxed(l2, bank->base + bank->regs->risingdetect);
1350
1351 bank->workaround_enabled = true;
1352
1353 update_gpio_context_count:
1354 if (bank->get_context_loss_count)
1355 bank->context_loss_count =
1356 bank->get_context_loss_count(dev);
1357
1358 omap_gpio_dbck_disable(bank);
1359 raw_spin_unlock_irqrestore(&bank->lock, flags);
1360
1361 return 0;
1362 }
1363
1364 static void omap_gpio_init_context(struct gpio_bank *p);
1365
omap_gpio_runtime_resume(struct device * dev)1366 static int omap_gpio_runtime_resume(struct device *dev)
1367 {
1368 struct platform_device *pdev = to_platform_device(dev);
1369 struct gpio_bank *bank = platform_get_drvdata(pdev);
1370 u32 l = 0, gen, gen0, gen1;
1371 unsigned long flags;
1372 int c;
1373
1374 raw_spin_lock_irqsave(&bank->lock, flags);
1375
1376 /*
1377 * On the first resume during the probe, the context has not
1378 * been initialised and so initialise it now. Also initialise
1379 * the context loss count.
1380 */
1381 if (bank->loses_context && !bank->context_valid) {
1382 omap_gpio_init_context(bank);
1383
1384 if (bank->get_context_loss_count)
1385 bank->context_loss_count =
1386 bank->get_context_loss_count(dev);
1387 }
1388
1389 omap_gpio_dbck_enable(bank);
1390
1391 /*
1392 * In ->runtime_suspend(), level-triggered, wakeup-enabled
1393 * GPIOs were set to edge trigger also in order to be able to
1394 * generate a PRCM wakeup. Here we restore the
1395 * pre-runtime_suspend() values for edge triggering.
1396 */
1397 writel_relaxed(bank->context.fallingdetect,
1398 bank->base + bank->regs->fallingdetect);
1399 writel_relaxed(bank->context.risingdetect,
1400 bank->base + bank->regs->risingdetect);
1401
1402 if (bank->loses_context) {
1403 if (!bank->get_context_loss_count) {
1404 omap_gpio_restore_context(bank);
1405 } else {
1406 c = bank->get_context_loss_count(dev);
1407 if (c != bank->context_loss_count) {
1408 omap_gpio_restore_context(bank);
1409 } else {
1410 raw_spin_unlock_irqrestore(&bank->lock, flags);
1411 return 0;
1412 }
1413 }
1414 }
1415
1416 if (!bank->workaround_enabled) {
1417 raw_spin_unlock_irqrestore(&bank->lock, flags);
1418 return 0;
1419 }
1420
1421 l = readl_relaxed(bank->base + bank->regs->datain);
1422
1423 /*
1424 * Check if any of the non-wakeup interrupt GPIOs have changed
1425 * state. If so, generate an IRQ by software. This is
1426 * horribly racy, but it's the best we can do to work around
1427 * this silicon bug.
1428 */
1429 l ^= bank->saved_datain;
1430 l &= bank->enabled_non_wakeup_gpios;
1431
1432 /*
1433 * No need to generate IRQs for the rising edge for gpio IRQs
1434 * configured with falling edge only; and vice versa.
1435 */
1436 gen0 = l & bank->context.fallingdetect;
1437 gen0 &= bank->saved_datain;
1438
1439 gen1 = l & bank->context.risingdetect;
1440 gen1 &= ~(bank->saved_datain);
1441
1442 /* FIXME: Consider GPIO IRQs with level detections properly! */
1443 gen = l & (~(bank->context.fallingdetect) &
1444 ~(bank->context.risingdetect));
1445 /* Consider all GPIO IRQs needed to be updated */
1446 gen |= gen0 | gen1;
1447
1448 if (gen) {
1449 u32 old0, old1;
1450
1451 old0 = readl_relaxed(bank->base + bank->regs->leveldetect0);
1452 old1 = readl_relaxed(bank->base + bank->regs->leveldetect1);
1453
1454 if (!bank->regs->irqstatus_raw0) {
1455 writel_relaxed(old0 | gen, bank->base +
1456 bank->regs->leveldetect0);
1457 writel_relaxed(old1 | gen, bank->base +
1458 bank->regs->leveldetect1);
1459 }
1460
1461 if (bank->regs->irqstatus_raw0) {
1462 writel_relaxed(old0 | l, bank->base +
1463 bank->regs->leveldetect0);
1464 writel_relaxed(old1 | l, bank->base +
1465 bank->regs->leveldetect1);
1466 }
1467 writel_relaxed(old0, bank->base + bank->regs->leveldetect0);
1468 writel_relaxed(old1, bank->base + bank->regs->leveldetect1);
1469 }
1470
1471 bank->workaround_enabled = false;
1472 raw_spin_unlock_irqrestore(&bank->lock, flags);
1473
1474 return 0;
1475 }
1476 #endif /* CONFIG_PM */
1477
1478 #if IS_BUILTIN(CONFIG_GPIO_OMAP)
omap2_gpio_prepare_for_idle(int pwr_mode)1479 void omap2_gpio_prepare_for_idle(int pwr_mode)
1480 {
1481 struct gpio_bank *bank;
1482
1483 list_for_each_entry(bank, &omap_gpio_list, node) {
1484 if (!BANK_USED(bank) || !bank->loses_context)
1485 continue;
1486
1487 bank->power_mode = pwr_mode;
1488
1489 pm_runtime_put_sync_suspend(bank->chip.parent);
1490 }
1491 }
1492
omap2_gpio_resume_after_idle(void)1493 void omap2_gpio_resume_after_idle(void)
1494 {
1495 struct gpio_bank *bank;
1496
1497 list_for_each_entry(bank, &omap_gpio_list, node) {
1498 if (!BANK_USED(bank) || !bank->loses_context)
1499 continue;
1500
1501 pm_runtime_get_sync(bank->chip.parent);
1502 }
1503 }
1504 #endif
1505
1506 #if defined(CONFIG_PM)
omap_gpio_init_context(struct gpio_bank * p)1507 static void omap_gpio_init_context(struct gpio_bank *p)
1508 {
1509 struct omap_gpio_reg_offs *regs = p->regs;
1510 void __iomem *base = p->base;
1511
1512 p->context.ctrl = readl_relaxed(base + regs->ctrl);
1513 p->context.oe = readl_relaxed(base + regs->direction);
1514 p->context.wake_en = readl_relaxed(base + regs->wkup_en);
1515 p->context.leveldetect0 = readl_relaxed(base + regs->leveldetect0);
1516 p->context.leveldetect1 = readl_relaxed(base + regs->leveldetect1);
1517 p->context.risingdetect = readl_relaxed(base + regs->risingdetect);
1518 p->context.fallingdetect = readl_relaxed(base + regs->fallingdetect);
1519 p->context.irqenable1 = readl_relaxed(base + regs->irqenable);
1520 p->context.irqenable2 = readl_relaxed(base + regs->irqenable2);
1521
1522 if (regs->set_dataout && p->regs->clr_dataout)
1523 p->context.dataout = readl_relaxed(base + regs->set_dataout);
1524 else
1525 p->context.dataout = readl_relaxed(base + regs->dataout);
1526
1527 p->context_valid = true;
1528 }
1529
omap_gpio_restore_context(struct gpio_bank * bank)1530 static void omap_gpio_restore_context(struct gpio_bank *bank)
1531 {
1532 writel_relaxed(bank->context.wake_en,
1533 bank->base + bank->regs->wkup_en);
1534 writel_relaxed(bank->context.ctrl, bank->base + bank->regs->ctrl);
1535 writel_relaxed(bank->context.leveldetect0,
1536 bank->base + bank->regs->leveldetect0);
1537 writel_relaxed(bank->context.leveldetect1,
1538 bank->base + bank->regs->leveldetect1);
1539 writel_relaxed(bank->context.risingdetect,
1540 bank->base + bank->regs->risingdetect);
1541 writel_relaxed(bank->context.fallingdetect,
1542 bank->base + bank->regs->fallingdetect);
1543 if (bank->regs->set_dataout && bank->regs->clr_dataout)
1544 writel_relaxed(bank->context.dataout,
1545 bank->base + bank->regs->set_dataout);
1546 else
1547 writel_relaxed(bank->context.dataout,
1548 bank->base + bank->regs->dataout);
1549 writel_relaxed(bank->context.oe, bank->base + bank->regs->direction);
1550
1551 if (bank->dbck_enable_mask) {
1552 writel_relaxed(bank->context.debounce, bank->base +
1553 bank->regs->debounce);
1554 writel_relaxed(bank->context.debounce_en,
1555 bank->base + bank->regs->debounce_en);
1556 }
1557
1558 writel_relaxed(bank->context.irqenable1,
1559 bank->base + bank->regs->irqenable);
1560 writel_relaxed(bank->context.irqenable2,
1561 bank->base + bank->regs->irqenable2);
1562 }
1563 #endif /* CONFIG_PM */
1564 #else
1565 #define omap_gpio_runtime_suspend NULL
1566 #define omap_gpio_runtime_resume NULL
omap_gpio_init_context(struct gpio_bank * p)1567 static inline void omap_gpio_init_context(struct gpio_bank *p) {}
1568 #endif
1569
1570 static const struct dev_pm_ops gpio_pm_ops = {
1571 SET_RUNTIME_PM_OPS(omap_gpio_runtime_suspend, omap_gpio_runtime_resume,
1572 NULL)
1573 };
1574
1575 #if defined(CONFIG_OF)
1576 static struct omap_gpio_reg_offs omap2_gpio_regs = {
1577 .revision = OMAP24XX_GPIO_REVISION,
1578 .direction = OMAP24XX_GPIO_OE,
1579 .datain = OMAP24XX_GPIO_DATAIN,
1580 .dataout = OMAP24XX_GPIO_DATAOUT,
1581 .set_dataout = OMAP24XX_GPIO_SETDATAOUT,
1582 .clr_dataout = OMAP24XX_GPIO_CLEARDATAOUT,
1583 .irqstatus = OMAP24XX_GPIO_IRQSTATUS1,
1584 .irqstatus2 = OMAP24XX_GPIO_IRQSTATUS2,
1585 .irqenable = OMAP24XX_GPIO_IRQENABLE1,
1586 .irqenable2 = OMAP24XX_GPIO_IRQENABLE2,
1587 .set_irqenable = OMAP24XX_GPIO_SETIRQENABLE1,
1588 .clr_irqenable = OMAP24XX_GPIO_CLEARIRQENABLE1,
1589 .debounce = OMAP24XX_GPIO_DEBOUNCE_VAL,
1590 .debounce_en = OMAP24XX_GPIO_DEBOUNCE_EN,
1591 .ctrl = OMAP24XX_GPIO_CTRL,
1592 .wkup_en = OMAP24XX_GPIO_WAKE_EN,
1593 .leveldetect0 = OMAP24XX_GPIO_LEVELDETECT0,
1594 .leveldetect1 = OMAP24XX_GPIO_LEVELDETECT1,
1595 .risingdetect = OMAP24XX_GPIO_RISINGDETECT,
1596 .fallingdetect = OMAP24XX_GPIO_FALLINGDETECT,
1597 };
1598
1599 static struct omap_gpio_reg_offs omap4_gpio_regs = {
1600 .revision = OMAP4_GPIO_REVISION,
1601 .direction = OMAP4_GPIO_OE,
1602 .datain = OMAP4_GPIO_DATAIN,
1603 .dataout = OMAP4_GPIO_DATAOUT,
1604 .set_dataout = OMAP4_GPIO_SETDATAOUT,
1605 .clr_dataout = OMAP4_GPIO_CLEARDATAOUT,
1606 .irqstatus = OMAP4_GPIO_IRQSTATUS0,
1607 .irqstatus2 = OMAP4_GPIO_IRQSTATUS1,
1608 .irqstatus_raw0 = OMAP4_GPIO_IRQSTATUSRAW0,
1609 .irqstatus_raw1 = OMAP4_GPIO_IRQSTATUSRAW1,
1610 .irqenable = OMAP4_GPIO_IRQSTATUSSET0,
1611 .irqenable2 = OMAP4_GPIO_IRQSTATUSSET1,
1612 .set_irqenable = OMAP4_GPIO_IRQSTATUSSET0,
1613 .clr_irqenable = OMAP4_GPIO_IRQSTATUSCLR0,
1614 .debounce = OMAP4_GPIO_DEBOUNCINGTIME,
1615 .debounce_en = OMAP4_GPIO_DEBOUNCENABLE,
1616 .ctrl = OMAP4_GPIO_CTRL,
1617 .wkup_en = OMAP4_GPIO_IRQWAKEN0,
1618 .leveldetect0 = OMAP4_GPIO_LEVELDETECT0,
1619 .leveldetect1 = OMAP4_GPIO_LEVELDETECT1,
1620 .risingdetect = OMAP4_GPIO_RISINGDETECT,
1621 .fallingdetect = OMAP4_GPIO_FALLINGDETECT,
1622 };
1623
1624 static const struct omap_gpio_platform_data omap2_pdata = {
1625 .regs = &omap2_gpio_regs,
1626 .bank_width = 32,
1627 .dbck_flag = false,
1628 };
1629
1630 static const struct omap_gpio_platform_data omap3_pdata = {
1631 .regs = &omap2_gpio_regs,
1632 .bank_width = 32,
1633 .dbck_flag = true,
1634 };
1635
1636 static const struct omap_gpio_platform_data omap4_pdata = {
1637 .regs = &omap4_gpio_regs,
1638 .bank_width = 32,
1639 .dbck_flag = true,
1640 };
1641
1642 static const struct of_device_id omap_gpio_match[] = {
1643 {
1644 .compatible = "ti,omap4-gpio",
1645 .data = &omap4_pdata,
1646 },
1647 {
1648 .compatible = "ti,omap3-gpio",
1649 .data = &omap3_pdata,
1650 },
1651 {
1652 .compatible = "ti,omap2-gpio",
1653 .data = &omap2_pdata,
1654 },
1655 { },
1656 };
1657 MODULE_DEVICE_TABLE(of, omap_gpio_match);
1658 #endif
1659
1660 static struct platform_driver omap_gpio_driver = {
1661 .probe = omap_gpio_probe,
1662 .remove = omap_gpio_remove,
1663 .driver = {
1664 .name = "omap_gpio",
1665 .pm = &gpio_pm_ops,
1666 .of_match_table = of_match_ptr(omap_gpio_match),
1667 },
1668 };
1669
1670 /*
1671 * gpio driver register needs to be done before
1672 * machine_init functions access gpio APIs.
1673 * Hence omap_gpio_drv_reg() is a postcore_initcall.
1674 */
omap_gpio_drv_reg(void)1675 static int __init omap_gpio_drv_reg(void)
1676 {
1677 return platform_driver_register(&omap_gpio_driver);
1678 }
1679 postcore_initcall(omap_gpio_drv_reg);
1680
omap_gpio_exit(void)1681 static void __exit omap_gpio_exit(void)
1682 {
1683 platform_driver_unregister(&omap_gpio_driver);
1684 }
1685 module_exit(omap_gpio_exit);
1686
1687 MODULE_DESCRIPTION("omap gpio driver");
1688 MODULE_ALIAS("platform:gpio-omap");
1689 MODULE_LICENSE("GPL v2");
1690