1 /*
2 * Copyright 2007-8 Advanced Micro Devices, Inc.
3 * Copyright 2008 Red Hat Inc.
4 *
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
9 * and/or sell copies of the Software, and to permit persons to whom the
10 * Software is furnished to do so, subject to the following conditions:
11 *
12 * The above copyright notice and this permission notice shall be included in
13 * all copies or substantial portions of the Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
19 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
20 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
21 * OTHER DEALINGS IN THE SOFTWARE.
22 *
23 * Authors: Dave Airlie
24 * Alex Deucher
25 */
26 #include <drm/drmP.h>
27 #include <drm/drm_edid.h>
28 #include <drm/drm_crtc_helper.h>
29 #include <drm/drm_fb_helper.h>
30 #include <drm/amdgpu_drm.h>
31 #include "amdgpu.h"
32 #include "atom.h"
33 #include "atombios_encoders.h"
34 #include "atombios_dp.h"
35 #include "amdgpu_connectors.h"
36 #include "amdgpu_i2c.h"
37
38 #include <linux/pm_runtime.h>
39
amdgpu_connector_hotplug(struct drm_connector * connector)40 void amdgpu_connector_hotplug(struct drm_connector *connector)
41 {
42 struct drm_device *dev = connector->dev;
43 struct amdgpu_device *adev = dev->dev_private;
44 struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector);
45
46 /* bail if the connector does not have hpd pin, e.g.,
47 * VGA, TV, etc.
48 */
49 if (amdgpu_connector->hpd.hpd == AMDGPU_HPD_NONE)
50 return;
51
52 amdgpu_display_hpd_set_polarity(adev, amdgpu_connector->hpd.hpd);
53
54 /* if the connector is already off, don't turn it back on */
55 if (connector->dpms != DRM_MODE_DPMS_ON)
56 return;
57
58 /* just deal with DP (not eDP) here. */
59 if (connector->connector_type == DRM_MODE_CONNECTOR_DisplayPort) {
60 struct amdgpu_connector_atom_dig *dig_connector =
61 amdgpu_connector->con_priv;
62
63 /* if existing sink type was not DP no need to retrain */
64 if (dig_connector->dp_sink_type != CONNECTOR_OBJECT_ID_DISPLAYPORT)
65 return;
66
67 /* first get sink type as it may be reset after (un)plug */
68 dig_connector->dp_sink_type = amdgpu_atombios_dp_get_sinktype(amdgpu_connector);
69 /* don't do anything if sink is not display port, i.e.,
70 * passive dp->(dvi|hdmi) adaptor
71 */
72 if (dig_connector->dp_sink_type == CONNECTOR_OBJECT_ID_DISPLAYPORT &&
73 amdgpu_display_hpd_sense(adev, amdgpu_connector->hpd.hpd) &&
74 amdgpu_atombios_dp_needs_link_train(amdgpu_connector)) {
75 /* Don't start link training before we have the DPCD */
76 if (amdgpu_atombios_dp_get_dpcd(amdgpu_connector))
77 return;
78
79 /* Turn the connector off and back on immediately, which
80 * will trigger link training
81 */
82 drm_helper_connector_dpms(connector, DRM_MODE_DPMS_OFF);
83 drm_helper_connector_dpms(connector, DRM_MODE_DPMS_ON);
84 }
85 }
86 }
87
amdgpu_connector_property_change_mode(struct drm_encoder * encoder)88 static void amdgpu_connector_property_change_mode(struct drm_encoder *encoder)
89 {
90 struct drm_crtc *crtc = encoder->crtc;
91
92 if (crtc && crtc->enabled) {
93 drm_crtc_helper_set_mode(crtc, &crtc->mode,
94 crtc->x, crtc->y, crtc->primary->fb);
95 }
96 }
97
amdgpu_connector_get_monitor_bpc(struct drm_connector * connector)98 int amdgpu_connector_get_monitor_bpc(struct drm_connector *connector)
99 {
100 struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector);
101 struct amdgpu_connector_atom_dig *dig_connector;
102 int bpc = 8;
103 unsigned mode_clock, max_tmds_clock;
104
105 switch (connector->connector_type) {
106 case DRM_MODE_CONNECTOR_DVII:
107 case DRM_MODE_CONNECTOR_HDMIB:
108 if (amdgpu_connector->use_digital) {
109 if (drm_detect_hdmi_monitor(amdgpu_connector_edid(connector))) {
110 if (connector->display_info.bpc)
111 bpc = connector->display_info.bpc;
112 }
113 }
114 break;
115 case DRM_MODE_CONNECTOR_DVID:
116 case DRM_MODE_CONNECTOR_HDMIA:
117 if (drm_detect_hdmi_monitor(amdgpu_connector_edid(connector))) {
118 if (connector->display_info.bpc)
119 bpc = connector->display_info.bpc;
120 }
121 break;
122 case DRM_MODE_CONNECTOR_DisplayPort:
123 dig_connector = amdgpu_connector->con_priv;
124 if ((dig_connector->dp_sink_type == CONNECTOR_OBJECT_ID_DISPLAYPORT) ||
125 (dig_connector->dp_sink_type == CONNECTOR_OBJECT_ID_eDP) ||
126 drm_detect_hdmi_monitor(amdgpu_connector_edid(connector))) {
127 if (connector->display_info.bpc)
128 bpc = connector->display_info.bpc;
129 }
130 break;
131 case DRM_MODE_CONNECTOR_eDP:
132 case DRM_MODE_CONNECTOR_LVDS:
133 if (connector->display_info.bpc)
134 bpc = connector->display_info.bpc;
135 else {
136 const struct drm_connector_helper_funcs *connector_funcs =
137 connector->helper_private;
138 struct drm_encoder *encoder = connector_funcs->best_encoder(connector);
139 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
140 struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv;
141
142 if (dig->lcd_misc & ATOM_PANEL_MISC_V13_6BIT_PER_COLOR)
143 bpc = 6;
144 else if (dig->lcd_misc & ATOM_PANEL_MISC_V13_8BIT_PER_COLOR)
145 bpc = 8;
146 }
147 break;
148 }
149
150 if (drm_detect_hdmi_monitor(amdgpu_connector_edid(connector))) {
151 /*
152 * Pre DCE-8 hw can't handle > 12 bpc, and more than 12 bpc doesn't make
153 * much sense without support for > 12 bpc framebuffers. RGB 4:4:4 at
154 * 12 bpc is always supported on hdmi deep color sinks, as this is
155 * required by the HDMI-1.3 spec. Clamp to a safe 12 bpc maximum.
156 */
157 if (bpc > 12) {
158 DRM_DEBUG("%s: HDMI deep color %d bpc unsupported. Using 12 bpc.\n",
159 connector->name, bpc);
160 bpc = 12;
161 }
162
163 /* Any defined maximum tmds clock limit we must not exceed? */
164 if (connector->display_info.max_tmds_clock > 0) {
165 /* mode_clock is clock in kHz for mode to be modeset on this connector */
166 mode_clock = amdgpu_connector->pixelclock_for_modeset;
167
168 /* Maximum allowable input clock in kHz */
169 max_tmds_clock = connector->display_info.max_tmds_clock;
170
171 DRM_DEBUG("%s: hdmi mode dotclock %d kHz, max tmds input clock %d kHz.\n",
172 connector->name, mode_clock, max_tmds_clock);
173
174 /* Check if bpc is within clock limit. Try to degrade gracefully otherwise */
175 if ((bpc == 12) && (mode_clock * 3/2 > max_tmds_clock)) {
176 if ((connector->display_info.edid_hdmi_dc_modes & DRM_EDID_HDMI_DC_30) &&
177 (mode_clock * 5/4 <= max_tmds_clock))
178 bpc = 10;
179 else
180 bpc = 8;
181
182 DRM_DEBUG("%s: HDMI deep color 12 bpc exceeds max tmds clock. Using %d bpc.\n",
183 connector->name, bpc);
184 }
185
186 if ((bpc == 10) && (mode_clock * 5/4 > max_tmds_clock)) {
187 bpc = 8;
188 DRM_DEBUG("%s: HDMI deep color 10 bpc exceeds max tmds clock. Using %d bpc.\n",
189 connector->name, bpc);
190 }
191 } else if (bpc > 8) {
192 /* max_tmds_clock missing, but hdmi spec mandates it for deep color. */
193 DRM_DEBUG("%s: Required max tmds clock for HDMI deep color missing. Using 8 bpc.\n",
194 connector->name);
195 bpc = 8;
196 }
197 }
198
199 if ((amdgpu_deep_color == 0) && (bpc > 8)) {
200 DRM_DEBUG("%s: Deep color disabled. Set amdgpu module param deep_color=1 to enable.\n",
201 connector->name);
202 bpc = 8;
203 }
204
205 DRM_DEBUG("%s: Display bpc=%d, returned bpc=%d\n",
206 connector->name, connector->display_info.bpc, bpc);
207
208 return bpc;
209 }
210
211 static void
amdgpu_connector_update_scratch_regs(struct drm_connector * connector,enum drm_connector_status status)212 amdgpu_connector_update_scratch_regs(struct drm_connector *connector,
213 enum drm_connector_status status)
214 {
215 struct drm_encoder *best_encoder = NULL;
216 struct drm_encoder *encoder = NULL;
217 const struct drm_connector_helper_funcs *connector_funcs = connector->helper_private;
218 bool connected;
219 int i;
220
221 best_encoder = connector_funcs->best_encoder(connector);
222
223 for (i = 0; i < DRM_CONNECTOR_MAX_ENCODER; i++) {
224 if (connector->encoder_ids[i] == 0)
225 break;
226
227 encoder = drm_encoder_find(connector->dev,
228 connector->encoder_ids[i]);
229 if (!encoder)
230 continue;
231
232 if ((encoder == best_encoder) && (status == connector_status_connected))
233 connected = true;
234 else
235 connected = false;
236
237 amdgpu_atombios_encoder_set_bios_scratch_regs(connector, encoder, connected);
238
239 }
240 }
241
242 static struct drm_encoder *
amdgpu_connector_find_encoder(struct drm_connector * connector,int encoder_type)243 amdgpu_connector_find_encoder(struct drm_connector *connector,
244 int encoder_type)
245 {
246 struct drm_encoder *encoder;
247 int i;
248
249 for (i = 0; i < DRM_CONNECTOR_MAX_ENCODER; i++) {
250 if (connector->encoder_ids[i] == 0)
251 break;
252 encoder = drm_encoder_find(connector->dev,
253 connector->encoder_ids[i]);
254 if (!encoder)
255 continue;
256
257 if (encoder->encoder_type == encoder_type)
258 return encoder;
259 }
260 return NULL;
261 }
262
amdgpu_connector_edid(struct drm_connector * connector)263 struct edid *amdgpu_connector_edid(struct drm_connector *connector)
264 {
265 struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector);
266 struct drm_property_blob *edid_blob = connector->edid_blob_ptr;
267
268 if (amdgpu_connector->edid) {
269 return amdgpu_connector->edid;
270 } else if (edid_blob) {
271 struct edid *edid = kmemdup(edid_blob->data, edid_blob->length, GFP_KERNEL);
272 if (edid)
273 amdgpu_connector->edid = edid;
274 }
275 return amdgpu_connector->edid;
276 }
277
278 static struct edid *
amdgpu_connector_get_hardcoded_edid(struct amdgpu_device * adev)279 amdgpu_connector_get_hardcoded_edid(struct amdgpu_device *adev)
280 {
281 struct edid *edid;
282
283 if (adev->mode_info.bios_hardcoded_edid) {
284 edid = kmalloc(adev->mode_info.bios_hardcoded_edid_size, GFP_KERNEL);
285 if (edid) {
286 memcpy((unsigned char *)edid,
287 (unsigned char *)adev->mode_info.bios_hardcoded_edid,
288 adev->mode_info.bios_hardcoded_edid_size);
289 return edid;
290 }
291 }
292 return NULL;
293 }
294
amdgpu_connector_get_edid(struct drm_connector * connector)295 static void amdgpu_connector_get_edid(struct drm_connector *connector)
296 {
297 struct drm_device *dev = connector->dev;
298 struct amdgpu_device *adev = dev->dev_private;
299 struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector);
300
301 if (amdgpu_connector->edid)
302 return;
303
304 /* on hw with routers, select right port */
305 if (amdgpu_connector->router.ddc_valid)
306 amdgpu_i2c_router_select_ddc_port(amdgpu_connector);
307
308 if ((amdgpu_connector_encoder_get_dp_bridge_encoder_id(connector) !=
309 ENCODER_OBJECT_ID_NONE) &&
310 amdgpu_connector->ddc_bus->has_aux) {
311 amdgpu_connector->edid = drm_get_edid(connector,
312 &amdgpu_connector->ddc_bus->aux.ddc);
313 } else if ((connector->connector_type == DRM_MODE_CONNECTOR_DisplayPort) ||
314 (connector->connector_type == DRM_MODE_CONNECTOR_eDP)) {
315 struct amdgpu_connector_atom_dig *dig = amdgpu_connector->con_priv;
316
317 if ((dig->dp_sink_type == CONNECTOR_OBJECT_ID_DISPLAYPORT ||
318 dig->dp_sink_type == CONNECTOR_OBJECT_ID_eDP) &&
319 amdgpu_connector->ddc_bus->has_aux)
320 amdgpu_connector->edid = drm_get_edid(connector,
321 &amdgpu_connector->ddc_bus->aux.ddc);
322 else if (amdgpu_connector->ddc_bus)
323 amdgpu_connector->edid = drm_get_edid(connector,
324 &amdgpu_connector->ddc_bus->adapter);
325 } else if (amdgpu_connector->ddc_bus) {
326 amdgpu_connector->edid = drm_get_edid(connector,
327 &amdgpu_connector->ddc_bus->adapter);
328 }
329
330 if (!amdgpu_connector->edid) {
331 /* some laptops provide a hardcoded edid in rom for LCDs */
332 if (((connector->connector_type == DRM_MODE_CONNECTOR_LVDS) ||
333 (connector->connector_type == DRM_MODE_CONNECTOR_eDP)))
334 amdgpu_connector->edid = amdgpu_connector_get_hardcoded_edid(adev);
335 }
336 }
337
amdgpu_connector_free_edid(struct drm_connector * connector)338 static void amdgpu_connector_free_edid(struct drm_connector *connector)
339 {
340 struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector);
341
342 if (amdgpu_connector->edid) {
343 kfree(amdgpu_connector->edid);
344 amdgpu_connector->edid = NULL;
345 }
346 }
347
amdgpu_connector_ddc_get_modes(struct drm_connector * connector)348 static int amdgpu_connector_ddc_get_modes(struct drm_connector *connector)
349 {
350 struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector);
351 int ret;
352
353 if (amdgpu_connector->edid) {
354 drm_mode_connector_update_edid_property(connector, amdgpu_connector->edid);
355 ret = drm_add_edid_modes(connector, amdgpu_connector->edid);
356 drm_edid_to_eld(connector, amdgpu_connector->edid);
357 return ret;
358 }
359 drm_mode_connector_update_edid_property(connector, NULL);
360 return 0;
361 }
362
363 static struct drm_encoder *
amdgpu_connector_best_single_encoder(struct drm_connector * connector)364 amdgpu_connector_best_single_encoder(struct drm_connector *connector)
365 {
366 int enc_id = connector->encoder_ids[0];
367
368 /* pick the encoder ids */
369 if (enc_id)
370 return drm_encoder_find(connector->dev, enc_id);
371 return NULL;
372 }
373
amdgpu_get_native_mode(struct drm_connector * connector)374 static void amdgpu_get_native_mode(struct drm_connector *connector)
375 {
376 struct drm_encoder *encoder = amdgpu_connector_best_single_encoder(connector);
377 struct amdgpu_encoder *amdgpu_encoder;
378
379 if (encoder == NULL)
380 return;
381
382 amdgpu_encoder = to_amdgpu_encoder(encoder);
383
384 if (!list_empty(&connector->probed_modes)) {
385 struct drm_display_mode *preferred_mode =
386 list_first_entry(&connector->probed_modes,
387 struct drm_display_mode, head);
388
389 amdgpu_encoder->native_mode = *preferred_mode;
390 } else {
391 amdgpu_encoder->native_mode.clock = 0;
392 }
393 }
394
395 static struct drm_display_mode *
amdgpu_connector_lcd_native_mode(struct drm_encoder * encoder)396 amdgpu_connector_lcd_native_mode(struct drm_encoder *encoder)
397 {
398 struct drm_device *dev = encoder->dev;
399 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
400 struct drm_display_mode *mode = NULL;
401 struct drm_display_mode *native_mode = &amdgpu_encoder->native_mode;
402
403 if (native_mode->hdisplay != 0 &&
404 native_mode->vdisplay != 0 &&
405 native_mode->clock != 0) {
406 mode = drm_mode_duplicate(dev, native_mode);
407 mode->type = DRM_MODE_TYPE_PREFERRED | DRM_MODE_TYPE_DRIVER;
408 drm_mode_set_name(mode);
409
410 DRM_DEBUG_KMS("Adding native panel mode %s\n", mode->name);
411 } else if (native_mode->hdisplay != 0 &&
412 native_mode->vdisplay != 0) {
413 /* mac laptops without an edid */
414 /* Note that this is not necessarily the exact panel mode,
415 * but an approximation based on the cvt formula. For these
416 * systems we should ideally read the mode info out of the
417 * registers or add a mode table, but this works and is much
418 * simpler.
419 */
420 mode = drm_cvt_mode(dev, native_mode->hdisplay, native_mode->vdisplay, 60, true, false, false);
421 mode->type = DRM_MODE_TYPE_PREFERRED | DRM_MODE_TYPE_DRIVER;
422 DRM_DEBUG_KMS("Adding cvt approximation of native panel mode %s\n", mode->name);
423 }
424 return mode;
425 }
426
amdgpu_connector_add_common_modes(struct drm_encoder * encoder,struct drm_connector * connector)427 static void amdgpu_connector_add_common_modes(struct drm_encoder *encoder,
428 struct drm_connector *connector)
429 {
430 struct drm_device *dev = encoder->dev;
431 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
432 struct drm_display_mode *mode = NULL;
433 struct drm_display_mode *native_mode = &amdgpu_encoder->native_mode;
434 int i;
435 static const struct mode_size {
436 int w;
437 int h;
438 } common_modes[17] = {
439 { 640, 480},
440 { 720, 480},
441 { 800, 600},
442 { 848, 480},
443 {1024, 768},
444 {1152, 768},
445 {1280, 720},
446 {1280, 800},
447 {1280, 854},
448 {1280, 960},
449 {1280, 1024},
450 {1440, 900},
451 {1400, 1050},
452 {1680, 1050},
453 {1600, 1200},
454 {1920, 1080},
455 {1920, 1200}
456 };
457
458 for (i = 0; i < 17; i++) {
459 if (amdgpu_encoder->devices & (ATOM_DEVICE_TV_SUPPORT)) {
460 if (common_modes[i].w > 1024 ||
461 common_modes[i].h > 768)
462 continue;
463 }
464 if (amdgpu_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) {
465 if (common_modes[i].w > native_mode->hdisplay ||
466 common_modes[i].h > native_mode->vdisplay ||
467 (common_modes[i].w == native_mode->hdisplay &&
468 common_modes[i].h == native_mode->vdisplay))
469 continue;
470 }
471 if (common_modes[i].w < 320 || common_modes[i].h < 200)
472 continue;
473
474 mode = drm_cvt_mode(dev, common_modes[i].w, common_modes[i].h, 60, false, false, false);
475 drm_mode_probed_add(connector, mode);
476 }
477 }
478
amdgpu_connector_set_property(struct drm_connector * connector,struct drm_property * property,uint64_t val)479 static int amdgpu_connector_set_property(struct drm_connector *connector,
480 struct drm_property *property,
481 uint64_t val)
482 {
483 struct drm_device *dev = connector->dev;
484 struct amdgpu_device *adev = dev->dev_private;
485 struct drm_encoder *encoder;
486 struct amdgpu_encoder *amdgpu_encoder;
487
488 if (property == adev->mode_info.coherent_mode_property) {
489 struct amdgpu_encoder_atom_dig *dig;
490 bool new_coherent_mode;
491
492 /* need to find digital encoder on connector */
493 encoder = amdgpu_connector_find_encoder(connector, DRM_MODE_ENCODER_TMDS);
494 if (!encoder)
495 return 0;
496
497 amdgpu_encoder = to_amdgpu_encoder(encoder);
498
499 if (!amdgpu_encoder->enc_priv)
500 return 0;
501
502 dig = amdgpu_encoder->enc_priv;
503 new_coherent_mode = val ? true : false;
504 if (dig->coherent_mode != new_coherent_mode) {
505 dig->coherent_mode = new_coherent_mode;
506 amdgpu_connector_property_change_mode(&amdgpu_encoder->base);
507 }
508 }
509
510 if (property == adev->mode_info.audio_property) {
511 struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector);
512 /* need to find digital encoder on connector */
513 encoder = amdgpu_connector_find_encoder(connector, DRM_MODE_ENCODER_TMDS);
514 if (!encoder)
515 return 0;
516
517 amdgpu_encoder = to_amdgpu_encoder(encoder);
518
519 if (amdgpu_connector->audio != val) {
520 amdgpu_connector->audio = val;
521 amdgpu_connector_property_change_mode(&amdgpu_encoder->base);
522 }
523 }
524
525 if (property == adev->mode_info.dither_property) {
526 struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector);
527 /* need to find digital encoder on connector */
528 encoder = amdgpu_connector_find_encoder(connector, DRM_MODE_ENCODER_TMDS);
529 if (!encoder)
530 return 0;
531
532 amdgpu_encoder = to_amdgpu_encoder(encoder);
533
534 if (amdgpu_connector->dither != val) {
535 amdgpu_connector->dither = val;
536 amdgpu_connector_property_change_mode(&amdgpu_encoder->base);
537 }
538 }
539
540 if (property == adev->mode_info.underscan_property) {
541 /* need to find digital encoder on connector */
542 encoder = amdgpu_connector_find_encoder(connector, DRM_MODE_ENCODER_TMDS);
543 if (!encoder)
544 return 0;
545
546 amdgpu_encoder = to_amdgpu_encoder(encoder);
547
548 if (amdgpu_encoder->underscan_type != val) {
549 amdgpu_encoder->underscan_type = val;
550 amdgpu_connector_property_change_mode(&amdgpu_encoder->base);
551 }
552 }
553
554 if (property == adev->mode_info.underscan_hborder_property) {
555 /* need to find digital encoder on connector */
556 encoder = amdgpu_connector_find_encoder(connector, DRM_MODE_ENCODER_TMDS);
557 if (!encoder)
558 return 0;
559
560 amdgpu_encoder = to_amdgpu_encoder(encoder);
561
562 if (amdgpu_encoder->underscan_hborder != val) {
563 amdgpu_encoder->underscan_hborder = val;
564 amdgpu_connector_property_change_mode(&amdgpu_encoder->base);
565 }
566 }
567
568 if (property == adev->mode_info.underscan_vborder_property) {
569 /* need to find digital encoder on connector */
570 encoder = amdgpu_connector_find_encoder(connector, DRM_MODE_ENCODER_TMDS);
571 if (!encoder)
572 return 0;
573
574 amdgpu_encoder = to_amdgpu_encoder(encoder);
575
576 if (amdgpu_encoder->underscan_vborder != val) {
577 amdgpu_encoder->underscan_vborder = val;
578 amdgpu_connector_property_change_mode(&amdgpu_encoder->base);
579 }
580 }
581
582 if (property == adev->mode_info.load_detect_property) {
583 struct amdgpu_connector *amdgpu_connector =
584 to_amdgpu_connector(connector);
585
586 if (val == 0)
587 amdgpu_connector->dac_load_detect = false;
588 else
589 amdgpu_connector->dac_load_detect = true;
590 }
591
592 if (property == dev->mode_config.scaling_mode_property) {
593 enum amdgpu_rmx_type rmx_type;
594
595 if (connector->encoder) {
596 amdgpu_encoder = to_amdgpu_encoder(connector->encoder);
597 } else {
598 const struct drm_connector_helper_funcs *connector_funcs = connector->helper_private;
599 amdgpu_encoder = to_amdgpu_encoder(connector_funcs->best_encoder(connector));
600 }
601
602 switch (val) {
603 default:
604 case DRM_MODE_SCALE_NONE: rmx_type = RMX_OFF; break;
605 case DRM_MODE_SCALE_CENTER: rmx_type = RMX_CENTER; break;
606 case DRM_MODE_SCALE_ASPECT: rmx_type = RMX_ASPECT; break;
607 case DRM_MODE_SCALE_FULLSCREEN: rmx_type = RMX_FULL; break;
608 }
609 if (amdgpu_encoder->rmx_type == rmx_type)
610 return 0;
611
612 if ((rmx_type != DRM_MODE_SCALE_NONE) &&
613 (amdgpu_encoder->native_mode.clock == 0))
614 return 0;
615
616 amdgpu_encoder->rmx_type = rmx_type;
617
618 amdgpu_connector_property_change_mode(&amdgpu_encoder->base);
619 }
620
621 return 0;
622 }
623
624 static void
amdgpu_connector_fixup_lcd_native_mode(struct drm_encoder * encoder,struct drm_connector * connector)625 amdgpu_connector_fixup_lcd_native_mode(struct drm_encoder *encoder,
626 struct drm_connector *connector)
627 {
628 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
629 struct drm_display_mode *native_mode = &amdgpu_encoder->native_mode;
630 struct drm_display_mode *t, *mode;
631
632 /* If the EDID preferred mode doesn't match the native mode, use it */
633 list_for_each_entry_safe(mode, t, &connector->probed_modes, head) {
634 if (mode->type & DRM_MODE_TYPE_PREFERRED) {
635 if (mode->hdisplay != native_mode->hdisplay ||
636 mode->vdisplay != native_mode->vdisplay)
637 memcpy(native_mode, mode, sizeof(*mode));
638 }
639 }
640
641 /* Try to get native mode details from EDID if necessary */
642 if (!native_mode->clock) {
643 list_for_each_entry_safe(mode, t, &connector->probed_modes, head) {
644 if (mode->hdisplay == native_mode->hdisplay &&
645 mode->vdisplay == native_mode->vdisplay) {
646 *native_mode = *mode;
647 drm_mode_set_crtcinfo(native_mode, CRTC_INTERLACE_HALVE_V);
648 DRM_DEBUG_KMS("Determined LVDS native mode details from EDID\n");
649 break;
650 }
651 }
652 }
653
654 if (!native_mode->clock) {
655 DRM_DEBUG_KMS("No LVDS native mode details, disabling RMX\n");
656 amdgpu_encoder->rmx_type = RMX_OFF;
657 }
658 }
659
amdgpu_connector_lvds_get_modes(struct drm_connector * connector)660 static int amdgpu_connector_lvds_get_modes(struct drm_connector *connector)
661 {
662 struct drm_encoder *encoder;
663 int ret = 0;
664 struct drm_display_mode *mode;
665
666 amdgpu_connector_get_edid(connector);
667 ret = amdgpu_connector_ddc_get_modes(connector);
668 if (ret > 0) {
669 encoder = amdgpu_connector_best_single_encoder(connector);
670 if (encoder) {
671 amdgpu_connector_fixup_lcd_native_mode(encoder, connector);
672 /* add scaled modes */
673 amdgpu_connector_add_common_modes(encoder, connector);
674 }
675 return ret;
676 }
677
678 encoder = amdgpu_connector_best_single_encoder(connector);
679 if (!encoder)
680 return 0;
681
682 /* we have no EDID modes */
683 mode = amdgpu_connector_lcd_native_mode(encoder);
684 if (mode) {
685 ret = 1;
686 drm_mode_probed_add(connector, mode);
687 /* add the width/height from vbios tables if available */
688 connector->display_info.width_mm = mode->width_mm;
689 connector->display_info.height_mm = mode->height_mm;
690 /* add scaled modes */
691 amdgpu_connector_add_common_modes(encoder, connector);
692 }
693
694 return ret;
695 }
696
amdgpu_connector_lvds_mode_valid(struct drm_connector * connector,struct drm_display_mode * mode)697 static int amdgpu_connector_lvds_mode_valid(struct drm_connector *connector,
698 struct drm_display_mode *mode)
699 {
700 struct drm_encoder *encoder = amdgpu_connector_best_single_encoder(connector);
701
702 if ((mode->hdisplay < 320) || (mode->vdisplay < 240))
703 return MODE_PANEL;
704
705 if (encoder) {
706 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
707 struct drm_display_mode *native_mode = &amdgpu_encoder->native_mode;
708
709 /* AVIVO hardware supports downscaling modes larger than the panel
710 * to the panel size, but I'm not sure this is desirable.
711 */
712 if ((mode->hdisplay > native_mode->hdisplay) ||
713 (mode->vdisplay > native_mode->vdisplay))
714 return MODE_PANEL;
715
716 /* if scaling is disabled, block non-native modes */
717 if (amdgpu_encoder->rmx_type == RMX_OFF) {
718 if ((mode->hdisplay != native_mode->hdisplay) ||
719 (mode->vdisplay != native_mode->vdisplay))
720 return MODE_PANEL;
721 }
722 }
723
724 return MODE_OK;
725 }
726
727 static enum drm_connector_status
amdgpu_connector_lvds_detect(struct drm_connector * connector,bool force)728 amdgpu_connector_lvds_detect(struct drm_connector *connector, bool force)
729 {
730 struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector);
731 struct drm_encoder *encoder = amdgpu_connector_best_single_encoder(connector);
732 enum drm_connector_status ret = connector_status_disconnected;
733 int r;
734
735 if (!drm_kms_helper_is_poll_worker()) {
736 r = pm_runtime_get_sync(connector->dev->dev);
737 if (r < 0)
738 return connector_status_disconnected;
739 }
740
741 if (encoder) {
742 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
743 struct drm_display_mode *native_mode = &amdgpu_encoder->native_mode;
744
745 /* check if panel is valid */
746 if (native_mode->hdisplay >= 320 && native_mode->vdisplay >= 240)
747 ret = connector_status_connected;
748
749 }
750
751 /* check for edid as well */
752 amdgpu_connector_get_edid(connector);
753 if (amdgpu_connector->edid)
754 ret = connector_status_connected;
755 /* check acpi lid status ??? */
756
757 amdgpu_connector_update_scratch_regs(connector, ret);
758
759 if (!drm_kms_helper_is_poll_worker()) {
760 pm_runtime_mark_last_busy(connector->dev->dev);
761 pm_runtime_put_autosuspend(connector->dev->dev);
762 }
763
764 return ret;
765 }
766
amdgpu_connector_unregister(struct drm_connector * connector)767 static void amdgpu_connector_unregister(struct drm_connector *connector)
768 {
769 struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector);
770
771 if (amdgpu_connector->ddc_bus && amdgpu_connector->ddc_bus->has_aux) {
772 drm_dp_aux_unregister(&amdgpu_connector->ddc_bus->aux);
773 amdgpu_connector->ddc_bus->has_aux = false;
774 }
775 }
776
amdgpu_connector_destroy(struct drm_connector * connector)777 static void amdgpu_connector_destroy(struct drm_connector *connector)
778 {
779 struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector);
780
781 amdgpu_connector_free_edid(connector);
782 kfree(amdgpu_connector->con_priv);
783 drm_connector_unregister(connector);
784 drm_connector_cleanup(connector);
785 kfree(connector);
786 }
787
amdgpu_connector_set_lcd_property(struct drm_connector * connector,struct drm_property * property,uint64_t value)788 static int amdgpu_connector_set_lcd_property(struct drm_connector *connector,
789 struct drm_property *property,
790 uint64_t value)
791 {
792 struct drm_device *dev = connector->dev;
793 struct amdgpu_encoder *amdgpu_encoder;
794 enum amdgpu_rmx_type rmx_type;
795
796 DRM_DEBUG_KMS("\n");
797 if (property != dev->mode_config.scaling_mode_property)
798 return 0;
799
800 if (connector->encoder)
801 amdgpu_encoder = to_amdgpu_encoder(connector->encoder);
802 else {
803 const struct drm_connector_helper_funcs *connector_funcs = connector->helper_private;
804 amdgpu_encoder = to_amdgpu_encoder(connector_funcs->best_encoder(connector));
805 }
806
807 switch (value) {
808 case DRM_MODE_SCALE_NONE: rmx_type = RMX_OFF; break;
809 case DRM_MODE_SCALE_CENTER: rmx_type = RMX_CENTER; break;
810 case DRM_MODE_SCALE_ASPECT: rmx_type = RMX_ASPECT; break;
811 default:
812 case DRM_MODE_SCALE_FULLSCREEN: rmx_type = RMX_FULL; break;
813 }
814 if (amdgpu_encoder->rmx_type == rmx_type)
815 return 0;
816
817 amdgpu_encoder->rmx_type = rmx_type;
818
819 amdgpu_connector_property_change_mode(&amdgpu_encoder->base);
820 return 0;
821 }
822
823
824 static const struct drm_connector_helper_funcs amdgpu_connector_lvds_helper_funcs = {
825 .get_modes = amdgpu_connector_lvds_get_modes,
826 .mode_valid = amdgpu_connector_lvds_mode_valid,
827 .best_encoder = amdgpu_connector_best_single_encoder,
828 };
829
830 static const struct drm_connector_funcs amdgpu_connector_lvds_funcs = {
831 .dpms = drm_helper_connector_dpms,
832 .detect = amdgpu_connector_lvds_detect,
833 .fill_modes = drm_helper_probe_single_connector_modes,
834 .early_unregister = amdgpu_connector_unregister,
835 .destroy = amdgpu_connector_destroy,
836 .set_property = amdgpu_connector_set_lcd_property,
837 };
838
amdgpu_connector_vga_get_modes(struct drm_connector * connector)839 static int amdgpu_connector_vga_get_modes(struct drm_connector *connector)
840 {
841 int ret;
842
843 amdgpu_connector_get_edid(connector);
844 ret = amdgpu_connector_ddc_get_modes(connector);
845
846 return ret;
847 }
848
amdgpu_connector_vga_mode_valid(struct drm_connector * connector,struct drm_display_mode * mode)849 static int amdgpu_connector_vga_mode_valid(struct drm_connector *connector,
850 struct drm_display_mode *mode)
851 {
852 struct drm_device *dev = connector->dev;
853 struct amdgpu_device *adev = dev->dev_private;
854
855 /* XXX check mode bandwidth */
856
857 if ((mode->clock / 10) > adev->clock.max_pixel_clock)
858 return MODE_CLOCK_HIGH;
859
860 return MODE_OK;
861 }
862
863 static enum drm_connector_status
amdgpu_connector_vga_detect(struct drm_connector * connector,bool force)864 amdgpu_connector_vga_detect(struct drm_connector *connector, bool force)
865 {
866 struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector);
867 struct drm_encoder *encoder;
868 const struct drm_encoder_helper_funcs *encoder_funcs;
869 bool dret = false;
870 enum drm_connector_status ret = connector_status_disconnected;
871 int r;
872
873 if (!drm_kms_helper_is_poll_worker()) {
874 r = pm_runtime_get_sync(connector->dev->dev);
875 if (r < 0)
876 return connector_status_disconnected;
877 }
878
879 encoder = amdgpu_connector_best_single_encoder(connector);
880 if (!encoder)
881 ret = connector_status_disconnected;
882
883 if (amdgpu_connector->ddc_bus)
884 dret = amdgpu_ddc_probe(amdgpu_connector, false);
885 if (dret) {
886 amdgpu_connector->detected_by_load = false;
887 amdgpu_connector_free_edid(connector);
888 amdgpu_connector_get_edid(connector);
889
890 if (!amdgpu_connector->edid) {
891 DRM_ERROR("%s: probed a monitor but no|invalid EDID\n",
892 connector->name);
893 ret = connector_status_connected;
894 } else {
895 amdgpu_connector->use_digital =
896 !!(amdgpu_connector->edid->input & DRM_EDID_INPUT_DIGITAL);
897
898 /* some oems have boards with separate digital and analog connectors
899 * with a shared ddc line (often vga + hdmi)
900 */
901 if (amdgpu_connector->use_digital && amdgpu_connector->shared_ddc) {
902 amdgpu_connector_free_edid(connector);
903 ret = connector_status_disconnected;
904 } else {
905 ret = connector_status_connected;
906 }
907 }
908 } else {
909
910 /* if we aren't forcing don't do destructive polling */
911 if (!force) {
912 /* only return the previous status if we last
913 * detected a monitor via load.
914 */
915 if (amdgpu_connector->detected_by_load)
916 ret = connector->status;
917 goto out;
918 }
919
920 if (amdgpu_connector->dac_load_detect && encoder) {
921 encoder_funcs = encoder->helper_private;
922 ret = encoder_funcs->detect(encoder, connector);
923 if (ret != connector_status_disconnected)
924 amdgpu_connector->detected_by_load = true;
925 }
926 }
927
928 amdgpu_connector_update_scratch_regs(connector, ret);
929
930 out:
931 if (!drm_kms_helper_is_poll_worker()) {
932 pm_runtime_mark_last_busy(connector->dev->dev);
933 pm_runtime_put_autosuspend(connector->dev->dev);
934 }
935
936 return ret;
937 }
938
939 static const struct drm_connector_helper_funcs amdgpu_connector_vga_helper_funcs = {
940 .get_modes = amdgpu_connector_vga_get_modes,
941 .mode_valid = amdgpu_connector_vga_mode_valid,
942 .best_encoder = amdgpu_connector_best_single_encoder,
943 };
944
945 static const struct drm_connector_funcs amdgpu_connector_vga_funcs = {
946 .dpms = drm_helper_connector_dpms,
947 .detect = amdgpu_connector_vga_detect,
948 .fill_modes = drm_helper_probe_single_connector_modes,
949 .early_unregister = amdgpu_connector_unregister,
950 .destroy = amdgpu_connector_destroy,
951 .set_property = amdgpu_connector_set_property,
952 };
953
954 static bool
amdgpu_connector_check_hpd_status_unchanged(struct drm_connector * connector)955 amdgpu_connector_check_hpd_status_unchanged(struct drm_connector *connector)
956 {
957 struct drm_device *dev = connector->dev;
958 struct amdgpu_device *adev = dev->dev_private;
959 struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector);
960 enum drm_connector_status status;
961
962 if (amdgpu_connector->hpd.hpd != AMDGPU_HPD_NONE) {
963 if (amdgpu_display_hpd_sense(adev, amdgpu_connector->hpd.hpd))
964 status = connector_status_connected;
965 else
966 status = connector_status_disconnected;
967 if (connector->status == status)
968 return true;
969 }
970
971 return false;
972 }
973
974 /*
975 * DVI is complicated
976 * Do a DDC probe, if DDC probe passes, get the full EDID so
977 * we can do analog/digital monitor detection at this point.
978 * If the monitor is an analog monitor or we got no DDC,
979 * we need to find the DAC encoder object for this connector.
980 * If we got no DDC, we do load detection on the DAC encoder object.
981 * If we got analog DDC or load detection passes on the DAC encoder
982 * we have to check if this analog encoder is shared with anyone else (TV)
983 * if its shared we have to set the other connector to disconnected.
984 */
985 static enum drm_connector_status
amdgpu_connector_dvi_detect(struct drm_connector * connector,bool force)986 amdgpu_connector_dvi_detect(struct drm_connector *connector, bool force)
987 {
988 struct drm_device *dev = connector->dev;
989 struct amdgpu_device *adev = dev->dev_private;
990 struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector);
991 struct drm_encoder *encoder = NULL;
992 const struct drm_encoder_helper_funcs *encoder_funcs;
993 int i, r;
994 enum drm_connector_status ret = connector_status_disconnected;
995 bool dret = false, broken_edid = false;
996
997 if (!drm_kms_helper_is_poll_worker()) {
998 r = pm_runtime_get_sync(connector->dev->dev);
999 if (r < 0)
1000 return connector_status_disconnected;
1001 }
1002
1003 if (!force && amdgpu_connector_check_hpd_status_unchanged(connector)) {
1004 ret = connector->status;
1005 goto exit;
1006 }
1007
1008 if (amdgpu_connector->ddc_bus)
1009 dret = amdgpu_ddc_probe(amdgpu_connector, false);
1010 if (dret) {
1011 amdgpu_connector->detected_by_load = false;
1012 amdgpu_connector_free_edid(connector);
1013 amdgpu_connector_get_edid(connector);
1014
1015 if (!amdgpu_connector->edid) {
1016 DRM_ERROR("%s: probed a monitor but no|invalid EDID\n",
1017 connector->name);
1018 ret = connector_status_connected;
1019 broken_edid = true; /* defer use_digital to later */
1020 } else {
1021 amdgpu_connector->use_digital =
1022 !!(amdgpu_connector->edid->input & DRM_EDID_INPUT_DIGITAL);
1023
1024 /* some oems have boards with separate digital and analog connectors
1025 * with a shared ddc line (often vga + hdmi)
1026 */
1027 if ((!amdgpu_connector->use_digital) && amdgpu_connector->shared_ddc) {
1028 amdgpu_connector_free_edid(connector);
1029 ret = connector_status_disconnected;
1030 } else {
1031 ret = connector_status_connected;
1032 }
1033
1034 /* This gets complicated. We have boards with VGA + HDMI with a
1035 * shared DDC line and we have boards with DVI-D + HDMI with a shared
1036 * DDC line. The latter is more complex because with DVI<->HDMI adapters
1037 * you don't really know what's connected to which port as both are digital.
1038 */
1039 if (amdgpu_connector->shared_ddc && (ret == connector_status_connected)) {
1040 struct drm_connector *list_connector;
1041 struct amdgpu_connector *list_amdgpu_connector;
1042 list_for_each_entry(list_connector, &dev->mode_config.connector_list, head) {
1043 if (connector == list_connector)
1044 continue;
1045 list_amdgpu_connector = to_amdgpu_connector(list_connector);
1046 if (list_amdgpu_connector->shared_ddc &&
1047 (list_amdgpu_connector->ddc_bus->rec.i2c_id ==
1048 amdgpu_connector->ddc_bus->rec.i2c_id)) {
1049 /* cases where both connectors are digital */
1050 if (list_connector->connector_type != DRM_MODE_CONNECTOR_VGA) {
1051 /* hpd is our only option in this case */
1052 if (!amdgpu_display_hpd_sense(adev, amdgpu_connector->hpd.hpd)) {
1053 amdgpu_connector_free_edid(connector);
1054 ret = connector_status_disconnected;
1055 }
1056 }
1057 }
1058 }
1059 }
1060 }
1061 }
1062
1063 if ((ret == connector_status_connected) && (amdgpu_connector->use_digital == true))
1064 goto out;
1065
1066 /* DVI-D and HDMI-A are digital only */
1067 if ((connector->connector_type == DRM_MODE_CONNECTOR_DVID) ||
1068 (connector->connector_type == DRM_MODE_CONNECTOR_HDMIA))
1069 goto out;
1070
1071 /* if we aren't forcing don't do destructive polling */
1072 if (!force) {
1073 /* only return the previous status if we last
1074 * detected a monitor via load.
1075 */
1076 if (amdgpu_connector->detected_by_load)
1077 ret = connector->status;
1078 goto out;
1079 }
1080
1081 /* find analog encoder */
1082 if (amdgpu_connector->dac_load_detect) {
1083 for (i = 0; i < DRM_CONNECTOR_MAX_ENCODER; i++) {
1084 if (connector->encoder_ids[i] == 0)
1085 break;
1086
1087 encoder = drm_encoder_find(connector->dev, connector->encoder_ids[i]);
1088 if (!encoder)
1089 continue;
1090
1091 if (encoder->encoder_type != DRM_MODE_ENCODER_DAC &&
1092 encoder->encoder_type != DRM_MODE_ENCODER_TVDAC)
1093 continue;
1094
1095 encoder_funcs = encoder->helper_private;
1096 if (encoder_funcs->detect) {
1097 if (!broken_edid) {
1098 if (ret != connector_status_connected) {
1099 /* deal with analog monitors without DDC */
1100 ret = encoder_funcs->detect(encoder, connector);
1101 if (ret == connector_status_connected) {
1102 amdgpu_connector->use_digital = false;
1103 }
1104 if (ret != connector_status_disconnected)
1105 amdgpu_connector->detected_by_load = true;
1106 }
1107 } else {
1108 enum drm_connector_status lret;
1109 /* assume digital unless load detected otherwise */
1110 amdgpu_connector->use_digital = true;
1111 lret = encoder_funcs->detect(encoder, connector);
1112 DRM_DEBUG_KMS("load_detect %x returned: %x\n",encoder->encoder_type,lret);
1113 if (lret == connector_status_connected)
1114 amdgpu_connector->use_digital = false;
1115 }
1116 break;
1117 }
1118 }
1119 }
1120
1121 out:
1122 /* updated in get modes as well since we need to know if it's analog or digital */
1123 amdgpu_connector_update_scratch_regs(connector, ret);
1124
1125 exit:
1126 if (!drm_kms_helper_is_poll_worker()) {
1127 pm_runtime_mark_last_busy(connector->dev->dev);
1128 pm_runtime_put_autosuspend(connector->dev->dev);
1129 }
1130
1131 return ret;
1132 }
1133
1134 /* okay need to be smart in here about which encoder to pick */
1135 static struct drm_encoder *
amdgpu_connector_dvi_encoder(struct drm_connector * connector)1136 amdgpu_connector_dvi_encoder(struct drm_connector *connector)
1137 {
1138 int enc_id = connector->encoder_ids[0];
1139 struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector);
1140 struct drm_encoder *encoder;
1141 int i;
1142 for (i = 0; i < DRM_CONNECTOR_MAX_ENCODER; i++) {
1143 if (connector->encoder_ids[i] == 0)
1144 break;
1145
1146 encoder = drm_encoder_find(connector->dev, connector->encoder_ids[i]);
1147 if (!encoder)
1148 continue;
1149
1150 if (amdgpu_connector->use_digital == true) {
1151 if (encoder->encoder_type == DRM_MODE_ENCODER_TMDS)
1152 return encoder;
1153 } else {
1154 if (encoder->encoder_type == DRM_MODE_ENCODER_DAC ||
1155 encoder->encoder_type == DRM_MODE_ENCODER_TVDAC)
1156 return encoder;
1157 }
1158 }
1159
1160 /* see if we have a default encoder TODO */
1161
1162 /* then check use digitial */
1163 /* pick the first one */
1164 if (enc_id)
1165 return drm_encoder_find(connector->dev, enc_id);
1166 return NULL;
1167 }
1168
amdgpu_connector_dvi_force(struct drm_connector * connector)1169 static void amdgpu_connector_dvi_force(struct drm_connector *connector)
1170 {
1171 struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector);
1172 if (connector->force == DRM_FORCE_ON)
1173 amdgpu_connector->use_digital = false;
1174 if (connector->force == DRM_FORCE_ON_DIGITAL)
1175 amdgpu_connector->use_digital = true;
1176 }
1177
amdgpu_connector_dvi_mode_valid(struct drm_connector * connector,struct drm_display_mode * mode)1178 static int amdgpu_connector_dvi_mode_valid(struct drm_connector *connector,
1179 struct drm_display_mode *mode)
1180 {
1181 struct drm_device *dev = connector->dev;
1182 struct amdgpu_device *adev = dev->dev_private;
1183 struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector);
1184
1185 /* XXX check mode bandwidth */
1186
1187 if (amdgpu_connector->use_digital && (mode->clock > 165000)) {
1188 if ((amdgpu_connector->connector_object_id == CONNECTOR_OBJECT_ID_DUAL_LINK_DVI_I) ||
1189 (amdgpu_connector->connector_object_id == CONNECTOR_OBJECT_ID_DUAL_LINK_DVI_D) ||
1190 (amdgpu_connector->connector_object_id == CONNECTOR_OBJECT_ID_HDMI_TYPE_B)) {
1191 return MODE_OK;
1192 } else if (drm_detect_hdmi_monitor(amdgpu_connector_edid(connector))) {
1193 /* HDMI 1.3+ supports max clock of 340 Mhz */
1194 if (mode->clock > 340000)
1195 return MODE_CLOCK_HIGH;
1196 else
1197 return MODE_OK;
1198 } else {
1199 return MODE_CLOCK_HIGH;
1200 }
1201 }
1202
1203 /* check against the max pixel clock */
1204 if ((mode->clock / 10) > adev->clock.max_pixel_clock)
1205 return MODE_CLOCK_HIGH;
1206
1207 return MODE_OK;
1208 }
1209
1210 static const struct drm_connector_helper_funcs amdgpu_connector_dvi_helper_funcs = {
1211 .get_modes = amdgpu_connector_vga_get_modes,
1212 .mode_valid = amdgpu_connector_dvi_mode_valid,
1213 .best_encoder = amdgpu_connector_dvi_encoder,
1214 };
1215
1216 static const struct drm_connector_funcs amdgpu_connector_dvi_funcs = {
1217 .dpms = drm_helper_connector_dpms,
1218 .detect = amdgpu_connector_dvi_detect,
1219 .fill_modes = drm_helper_probe_single_connector_modes,
1220 .set_property = amdgpu_connector_set_property,
1221 .early_unregister = amdgpu_connector_unregister,
1222 .destroy = amdgpu_connector_destroy,
1223 .force = amdgpu_connector_dvi_force,
1224 };
1225
amdgpu_connector_dp_get_modes(struct drm_connector * connector)1226 static int amdgpu_connector_dp_get_modes(struct drm_connector *connector)
1227 {
1228 struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector);
1229 struct amdgpu_connector_atom_dig *amdgpu_dig_connector = amdgpu_connector->con_priv;
1230 struct drm_encoder *encoder = amdgpu_connector_best_single_encoder(connector);
1231 int ret;
1232
1233 if ((connector->connector_type == DRM_MODE_CONNECTOR_eDP) ||
1234 (connector->connector_type == DRM_MODE_CONNECTOR_LVDS)) {
1235 struct drm_display_mode *mode;
1236
1237 if (connector->connector_type == DRM_MODE_CONNECTOR_eDP) {
1238 if (!amdgpu_dig_connector->edp_on)
1239 amdgpu_atombios_encoder_set_edp_panel_power(connector,
1240 ATOM_TRANSMITTER_ACTION_POWER_ON);
1241 amdgpu_connector_get_edid(connector);
1242 ret = amdgpu_connector_ddc_get_modes(connector);
1243 if (!amdgpu_dig_connector->edp_on)
1244 amdgpu_atombios_encoder_set_edp_panel_power(connector,
1245 ATOM_TRANSMITTER_ACTION_POWER_OFF);
1246 } else {
1247 /* need to setup ddc on the bridge */
1248 if (amdgpu_connector_encoder_get_dp_bridge_encoder_id(connector) !=
1249 ENCODER_OBJECT_ID_NONE) {
1250 if (encoder)
1251 amdgpu_atombios_encoder_setup_ext_encoder_ddc(encoder);
1252 }
1253 amdgpu_connector_get_edid(connector);
1254 ret = amdgpu_connector_ddc_get_modes(connector);
1255 }
1256
1257 if (ret > 0) {
1258 if (encoder) {
1259 amdgpu_connector_fixup_lcd_native_mode(encoder, connector);
1260 /* add scaled modes */
1261 amdgpu_connector_add_common_modes(encoder, connector);
1262 }
1263 return ret;
1264 }
1265
1266 if (!encoder)
1267 return 0;
1268
1269 /* we have no EDID modes */
1270 mode = amdgpu_connector_lcd_native_mode(encoder);
1271 if (mode) {
1272 ret = 1;
1273 drm_mode_probed_add(connector, mode);
1274 /* add the width/height from vbios tables if available */
1275 connector->display_info.width_mm = mode->width_mm;
1276 connector->display_info.height_mm = mode->height_mm;
1277 /* add scaled modes */
1278 amdgpu_connector_add_common_modes(encoder, connector);
1279 }
1280 } else {
1281 /* need to setup ddc on the bridge */
1282 if (amdgpu_connector_encoder_get_dp_bridge_encoder_id(connector) !=
1283 ENCODER_OBJECT_ID_NONE) {
1284 if (encoder)
1285 amdgpu_atombios_encoder_setup_ext_encoder_ddc(encoder);
1286 }
1287 amdgpu_connector_get_edid(connector);
1288 ret = amdgpu_connector_ddc_get_modes(connector);
1289
1290 amdgpu_get_native_mode(connector);
1291 }
1292
1293 return ret;
1294 }
1295
amdgpu_connector_encoder_get_dp_bridge_encoder_id(struct drm_connector * connector)1296 u16 amdgpu_connector_encoder_get_dp_bridge_encoder_id(struct drm_connector *connector)
1297 {
1298 struct drm_encoder *encoder;
1299 struct amdgpu_encoder *amdgpu_encoder;
1300 int i;
1301
1302 for (i = 0; i < DRM_CONNECTOR_MAX_ENCODER; i++) {
1303 if (connector->encoder_ids[i] == 0)
1304 break;
1305
1306 encoder = drm_encoder_find(connector->dev,
1307 connector->encoder_ids[i]);
1308 if (!encoder)
1309 continue;
1310
1311 amdgpu_encoder = to_amdgpu_encoder(encoder);
1312
1313 switch (amdgpu_encoder->encoder_id) {
1314 case ENCODER_OBJECT_ID_TRAVIS:
1315 case ENCODER_OBJECT_ID_NUTMEG:
1316 return amdgpu_encoder->encoder_id;
1317 default:
1318 break;
1319 }
1320 }
1321
1322 return ENCODER_OBJECT_ID_NONE;
1323 }
1324
amdgpu_connector_encoder_is_hbr2(struct drm_connector * connector)1325 static bool amdgpu_connector_encoder_is_hbr2(struct drm_connector *connector)
1326 {
1327 struct drm_encoder *encoder;
1328 struct amdgpu_encoder *amdgpu_encoder;
1329 int i;
1330 bool found = false;
1331
1332 for (i = 0; i < DRM_CONNECTOR_MAX_ENCODER; i++) {
1333 if (connector->encoder_ids[i] == 0)
1334 break;
1335 encoder = drm_encoder_find(connector->dev,
1336 connector->encoder_ids[i]);
1337 if (!encoder)
1338 continue;
1339
1340 amdgpu_encoder = to_amdgpu_encoder(encoder);
1341 if (amdgpu_encoder->caps & ATOM_ENCODER_CAP_RECORD_HBR2)
1342 found = true;
1343 }
1344
1345 return found;
1346 }
1347
amdgpu_connector_is_dp12_capable(struct drm_connector * connector)1348 bool amdgpu_connector_is_dp12_capable(struct drm_connector *connector)
1349 {
1350 struct drm_device *dev = connector->dev;
1351 struct amdgpu_device *adev = dev->dev_private;
1352
1353 if ((adev->clock.default_dispclk >= 53900) &&
1354 amdgpu_connector_encoder_is_hbr2(connector)) {
1355 return true;
1356 }
1357
1358 return false;
1359 }
1360
1361 static enum drm_connector_status
amdgpu_connector_dp_detect(struct drm_connector * connector,bool force)1362 amdgpu_connector_dp_detect(struct drm_connector *connector, bool force)
1363 {
1364 struct drm_device *dev = connector->dev;
1365 struct amdgpu_device *adev = dev->dev_private;
1366 struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector);
1367 enum drm_connector_status ret = connector_status_disconnected;
1368 struct amdgpu_connector_atom_dig *amdgpu_dig_connector = amdgpu_connector->con_priv;
1369 struct drm_encoder *encoder = amdgpu_connector_best_single_encoder(connector);
1370 int r;
1371
1372 if (!drm_kms_helper_is_poll_worker()) {
1373 r = pm_runtime_get_sync(connector->dev->dev);
1374 if (r < 0)
1375 return connector_status_disconnected;
1376 }
1377
1378 if (!force && amdgpu_connector_check_hpd_status_unchanged(connector)) {
1379 ret = connector->status;
1380 goto out;
1381 }
1382
1383 amdgpu_connector_free_edid(connector);
1384
1385 if ((connector->connector_type == DRM_MODE_CONNECTOR_eDP) ||
1386 (connector->connector_type == DRM_MODE_CONNECTOR_LVDS)) {
1387 if (encoder) {
1388 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
1389 struct drm_display_mode *native_mode = &amdgpu_encoder->native_mode;
1390
1391 /* check if panel is valid */
1392 if (native_mode->hdisplay >= 320 && native_mode->vdisplay >= 240)
1393 ret = connector_status_connected;
1394 }
1395 /* eDP is always DP */
1396 amdgpu_dig_connector->dp_sink_type = CONNECTOR_OBJECT_ID_DISPLAYPORT;
1397 if (!amdgpu_dig_connector->edp_on)
1398 amdgpu_atombios_encoder_set_edp_panel_power(connector,
1399 ATOM_TRANSMITTER_ACTION_POWER_ON);
1400 if (!amdgpu_atombios_dp_get_dpcd(amdgpu_connector))
1401 ret = connector_status_connected;
1402 if (!amdgpu_dig_connector->edp_on)
1403 amdgpu_atombios_encoder_set_edp_panel_power(connector,
1404 ATOM_TRANSMITTER_ACTION_POWER_OFF);
1405 } else if (amdgpu_connector_encoder_get_dp_bridge_encoder_id(connector) !=
1406 ENCODER_OBJECT_ID_NONE) {
1407 /* DP bridges are always DP */
1408 amdgpu_dig_connector->dp_sink_type = CONNECTOR_OBJECT_ID_DISPLAYPORT;
1409 /* get the DPCD from the bridge */
1410 amdgpu_atombios_dp_get_dpcd(amdgpu_connector);
1411
1412 if (encoder) {
1413 /* setup ddc on the bridge */
1414 amdgpu_atombios_encoder_setup_ext_encoder_ddc(encoder);
1415 /* bridge chips are always aux */
1416 if (amdgpu_ddc_probe(amdgpu_connector, true)) /* try DDC */
1417 ret = connector_status_connected;
1418 else if (amdgpu_connector->dac_load_detect) { /* try load detection */
1419 const struct drm_encoder_helper_funcs *encoder_funcs = encoder->helper_private;
1420 ret = encoder_funcs->detect(encoder, connector);
1421 }
1422 }
1423 } else {
1424 amdgpu_dig_connector->dp_sink_type =
1425 amdgpu_atombios_dp_get_sinktype(amdgpu_connector);
1426 if (amdgpu_display_hpd_sense(adev, amdgpu_connector->hpd.hpd)) {
1427 ret = connector_status_connected;
1428 if (amdgpu_dig_connector->dp_sink_type == CONNECTOR_OBJECT_ID_DISPLAYPORT)
1429 amdgpu_atombios_dp_get_dpcd(amdgpu_connector);
1430 } else {
1431 if (amdgpu_dig_connector->dp_sink_type == CONNECTOR_OBJECT_ID_DISPLAYPORT) {
1432 if (!amdgpu_atombios_dp_get_dpcd(amdgpu_connector))
1433 ret = connector_status_connected;
1434 } else {
1435 /* try non-aux ddc (DP to DVI/HDMI/etc. adapter) */
1436 if (amdgpu_ddc_probe(amdgpu_connector, false))
1437 ret = connector_status_connected;
1438 }
1439 }
1440 }
1441
1442 amdgpu_connector_update_scratch_regs(connector, ret);
1443 out:
1444 if (!drm_kms_helper_is_poll_worker()) {
1445 pm_runtime_mark_last_busy(connector->dev->dev);
1446 pm_runtime_put_autosuspend(connector->dev->dev);
1447 }
1448
1449 return ret;
1450 }
1451
amdgpu_connector_dp_mode_valid(struct drm_connector * connector,struct drm_display_mode * mode)1452 static int amdgpu_connector_dp_mode_valid(struct drm_connector *connector,
1453 struct drm_display_mode *mode)
1454 {
1455 struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector);
1456 struct amdgpu_connector_atom_dig *amdgpu_dig_connector = amdgpu_connector->con_priv;
1457
1458 /* XXX check mode bandwidth */
1459
1460 if ((connector->connector_type == DRM_MODE_CONNECTOR_eDP) ||
1461 (connector->connector_type == DRM_MODE_CONNECTOR_LVDS)) {
1462 struct drm_encoder *encoder = amdgpu_connector_best_single_encoder(connector);
1463
1464 if ((mode->hdisplay < 320) || (mode->vdisplay < 240))
1465 return MODE_PANEL;
1466
1467 if (encoder) {
1468 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
1469 struct drm_display_mode *native_mode = &amdgpu_encoder->native_mode;
1470
1471 /* AVIVO hardware supports downscaling modes larger than the panel
1472 * to the panel size, but I'm not sure this is desirable.
1473 */
1474 if ((mode->hdisplay > native_mode->hdisplay) ||
1475 (mode->vdisplay > native_mode->vdisplay))
1476 return MODE_PANEL;
1477
1478 /* if scaling is disabled, block non-native modes */
1479 if (amdgpu_encoder->rmx_type == RMX_OFF) {
1480 if ((mode->hdisplay != native_mode->hdisplay) ||
1481 (mode->vdisplay != native_mode->vdisplay))
1482 return MODE_PANEL;
1483 }
1484 }
1485 return MODE_OK;
1486 } else {
1487 if ((amdgpu_dig_connector->dp_sink_type == CONNECTOR_OBJECT_ID_DISPLAYPORT) ||
1488 (amdgpu_dig_connector->dp_sink_type == CONNECTOR_OBJECT_ID_eDP)) {
1489 return amdgpu_atombios_dp_mode_valid_helper(connector, mode);
1490 } else {
1491 if (drm_detect_hdmi_monitor(amdgpu_connector_edid(connector))) {
1492 /* HDMI 1.3+ supports max clock of 340 Mhz */
1493 if (mode->clock > 340000)
1494 return MODE_CLOCK_HIGH;
1495 } else {
1496 if (mode->clock > 165000)
1497 return MODE_CLOCK_HIGH;
1498 }
1499 }
1500 }
1501
1502 return MODE_OK;
1503 }
1504
1505 static const struct drm_connector_helper_funcs amdgpu_connector_dp_helper_funcs = {
1506 .get_modes = amdgpu_connector_dp_get_modes,
1507 .mode_valid = amdgpu_connector_dp_mode_valid,
1508 .best_encoder = amdgpu_connector_dvi_encoder,
1509 };
1510
1511 static const struct drm_connector_funcs amdgpu_connector_dp_funcs = {
1512 .dpms = drm_helper_connector_dpms,
1513 .detect = amdgpu_connector_dp_detect,
1514 .fill_modes = drm_helper_probe_single_connector_modes,
1515 .set_property = amdgpu_connector_set_property,
1516 .early_unregister = amdgpu_connector_unregister,
1517 .destroy = amdgpu_connector_destroy,
1518 .force = amdgpu_connector_dvi_force,
1519 };
1520
1521 static const struct drm_connector_funcs amdgpu_connector_edp_funcs = {
1522 .dpms = drm_helper_connector_dpms,
1523 .detect = amdgpu_connector_dp_detect,
1524 .fill_modes = drm_helper_probe_single_connector_modes,
1525 .set_property = amdgpu_connector_set_lcd_property,
1526 .early_unregister = amdgpu_connector_unregister,
1527 .destroy = amdgpu_connector_destroy,
1528 .force = amdgpu_connector_dvi_force,
1529 };
1530
1531 void
amdgpu_connector_add(struct amdgpu_device * adev,uint32_t connector_id,uint32_t supported_device,int connector_type,struct amdgpu_i2c_bus_rec * i2c_bus,uint16_t connector_object_id,struct amdgpu_hpd * hpd,struct amdgpu_router * router)1532 amdgpu_connector_add(struct amdgpu_device *adev,
1533 uint32_t connector_id,
1534 uint32_t supported_device,
1535 int connector_type,
1536 struct amdgpu_i2c_bus_rec *i2c_bus,
1537 uint16_t connector_object_id,
1538 struct amdgpu_hpd *hpd,
1539 struct amdgpu_router *router)
1540 {
1541 struct drm_device *dev = adev->ddev;
1542 struct drm_connector *connector;
1543 struct amdgpu_connector *amdgpu_connector;
1544 struct amdgpu_connector_atom_dig *amdgpu_dig_connector;
1545 struct drm_encoder *encoder;
1546 struct amdgpu_encoder *amdgpu_encoder;
1547 uint32_t subpixel_order = SubPixelNone;
1548 bool shared_ddc = false;
1549 bool is_dp_bridge = false;
1550 bool has_aux = false;
1551
1552 if (connector_type == DRM_MODE_CONNECTOR_Unknown)
1553 return;
1554
1555 /* see if we already added it */
1556 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
1557 amdgpu_connector = to_amdgpu_connector(connector);
1558 if (amdgpu_connector->connector_id == connector_id) {
1559 amdgpu_connector->devices |= supported_device;
1560 return;
1561 }
1562 if (amdgpu_connector->ddc_bus && i2c_bus->valid) {
1563 if (amdgpu_connector->ddc_bus->rec.i2c_id == i2c_bus->i2c_id) {
1564 amdgpu_connector->shared_ddc = true;
1565 shared_ddc = true;
1566 }
1567 if (amdgpu_connector->router_bus && router->ddc_valid &&
1568 (amdgpu_connector->router.router_id == router->router_id)) {
1569 amdgpu_connector->shared_ddc = false;
1570 shared_ddc = false;
1571 }
1572 }
1573 }
1574
1575 /* check if it's a dp bridge */
1576 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
1577 amdgpu_encoder = to_amdgpu_encoder(encoder);
1578 if (amdgpu_encoder->devices & supported_device) {
1579 switch (amdgpu_encoder->encoder_id) {
1580 case ENCODER_OBJECT_ID_TRAVIS:
1581 case ENCODER_OBJECT_ID_NUTMEG:
1582 is_dp_bridge = true;
1583 break;
1584 default:
1585 break;
1586 }
1587 }
1588 }
1589
1590 amdgpu_connector = kzalloc(sizeof(struct amdgpu_connector), GFP_KERNEL);
1591 if (!amdgpu_connector)
1592 return;
1593
1594 connector = &amdgpu_connector->base;
1595
1596 amdgpu_connector->connector_id = connector_id;
1597 amdgpu_connector->devices = supported_device;
1598 amdgpu_connector->shared_ddc = shared_ddc;
1599 amdgpu_connector->connector_object_id = connector_object_id;
1600 amdgpu_connector->hpd = *hpd;
1601
1602 amdgpu_connector->router = *router;
1603 if (router->ddc_valid || router->cd_valid) {
1604 amdgpu_connector->router_bus = amdgpu_i2c_lookup(adev, &router->i2c_info);
1605 if (!amdgpu_connector->router_bus)
1606 DRM_ERROR("Failed to assign router i2c bus! Check dmesg for i2c errors.\n");
1607 }
1608
1609 if (is_dp_bridge) {
1610 amdgpu_dig_connector = kzalloc(sizeof(struct amdgpu_connector_atom_dig), GFP_KERNEL);
1611 if (!amdgpu_dig_connector)
1612 goto failed;
1613 amdgpu_connector->con_priv = amdgpu_dig_connector;
1614 if (i2c_bus->valid) {
1615 amdgpu_connector->ddc_bus = amdgpu_i2c_lookup(adev, i2c_bus);
1616 if (amdgpu_connector->ddc_bus)
1617 has_aux = true;
1618 else
1619 DRM_ERROR("DP: Failed to assign ddc bus! Check dmesg for i2c errors.\n");
1620 }
1621 switch (connector_type) {
1622 case DRM_MODE_CONNECTOR_VGA:
1623 case DRM_MODE_CONNECTOR_DVIA:
1624 default:
1625 drm_connector_init(dev, &amdgpu_connector->base,
1626 &amdgpu_connector_dp_funcs, connector_type);
1627 drm_connector_helper_add(&amdgpu_connector->base,
1628 &amdgpu_connector_dp_helper_funcs);
1629 connector->interlace_allowed = true;
1630 connector->doublescan_allowed = true;
1631 amdgpu_connector->dac_load_detect = true;
1632 drm_object_attach_property(&amdgpu_connector->base.base,
1633 adev->mode_info.load_detect_property,
1634 1);
1635 drm_object_attach_property(&amdgpu_connector->base.base,
1636 dev->mode_config.scaling_mode_property,
1637 DRM_MODE_SCALE_NONE);
1638 break;
1639 case DRM_MODE_CONNECTOR_DVII:
1640 case DRM_MODE_CONNECTOR_DVID:
1641 case DRM_MODE_CONNECTOR_HDMIA:
1642 case DRM_MODE_CONNECTOR_HDMIB:
1643 case DRM_MODE_CONNECTOR_DisplayPort:
1644 drm_connector_init(dev, &amdgpu_connector->base,
1645 &amdgpu_connector_dp_funcs, connector_type);
1646 drm_connector_helper_add(&amdgpu_connector->base,
1647 &amdgpu_connector_dp_helper_funcs);
1648 drm_object_attach_property(&amdgpu_connector->base.base,
1649 adev->mode_info.underscan_property,
1650 UNDERSCAN_OFF);
1651 drm_object_attach_property(&amdgpu_connector->base.base,
1652 adev->mode_info.underscan_hborder_property,
1653 0);
1654 drm_object_attach_property(&amdgpu_connector->base.base,
1655 adev->mode_info.underscan_vborder_property,
1656 0);
1657
1658 drm_object_attach_property(&amdgpu_connector->base.base,
1659 dev->mode_config.scaling_mode_property,
1660 DRM_MODE_SCALE_NONE);
1661
1662 drm_object_attach_property(&amdgpu_connector->base.base,
1663 adev->mode_info.dither_property,
1664 AMDGPU_FMT_DITHER_DISABLE);
1665
1666 if (amdgpu_audio != 0)
1667 drm_object_attach_property(&amdgpu_connector->base.base,
1668 adev->mode_info.audio_property,
1669 AMDGPU_AUDIO_AUTO);
1670
1671 subpixel_order = SubPixelHorizontalRGB;
1672 connector->interlace_allowed = true;
1673 if (connector_type == DRM_MODE_CONNECTOR_HDMIB)
1674 connector->doublescan_allowed = true;
1675 else
1676 connector->doublescan_allowed = false;
1677 if (connector_type == DRM_MODE_CONNECTOR_DVII) {
1678 amdgpu_connector->dac_load_detect = true;
1679 drm_object_attach_property(&amdgpu_connector->base.base,
1680 adev->mode_info.load_detect_property,
1681 1);
1682 }
1683 break;
1684 case DRM_MODE_CONNECTOR_LVDS:
1685 case DRM_MODE_CONNECTOR_eDP:
1686 drm_connector_init(dev, &amdgpu_connector->base,
1687 &amdgpu_connector_edp_funcs, connector_type);
1688 drm_connector_helper_add(&amdgpu_connector->base,
1689 &amdgpu_connector_dp_helper_funcs);
1690 drm_object_attach_property(&amdgpu_connector->base.base,
1691 dev->mode_config.scaling_mode_property,
1692 DRM_MODE_SCALE_FULLSCREEN);
1693 subpixel_order = SubPixelHorizontalRGB;
1694 connector->interlace_allowed = false;
1695 connector->doublescan_allowed = false;
1696 break;
1697 }
1698 } else {
1699 switch (connector_type) {
1700 case DRM_MODE_CONNECTOR_VGA:
1701 drm_connector_init(dev, &amdgpu_connector->base, &amdgpu_connector_vga_funcs, connector_type);
1702 drm_connector_helper_add(&amdgpu_connector->base, &amdgpu_connector_vga_helper_funcs);
1703 if (i2c_bus->valid) {
1704 amdgpu_connector->ddc_bus = amdgpu_i2c_lookup(adev, i2c_bus);
1705 if (!amdgpu_connector->ddc_bus)
1706 DRM_ERROR("VGA: Failed to assign ddc bus! Check dmesg for i2c errors.\n");
1707 }
1708 amdgpu_connector->dac_load_detect = true;
1709 drm_object_attach_property(&amdgpu_connector->base.base,
1710 adev->mode_info.load_detect_property,
1711 1);
1712 drm_object_attach_property(&amdgpu_connector->base.base,
1713 dev->mode_config.scaling_mode_property,
1714 DRM_MODE_SCALE_NONE);
1715 /* no HPD on analog connectors */
1716 amdgpu_connector->hpd.hpd = AMDGPU_HPD_NONE;
1717 connector->interlace_allowed = true;
1718 connector->doublescan_allowed = true;
1719 break;
1720 case DRM_MODE_CONNECTOR_DVIA:
1721 drm_connector_init(dev, &amdgpu_connector->base, &amdgpu_connector_vga_funcs, connector_type);
1722 drm_connector_helper_add(&amdgpu_connector->base, &amdgpu_connector_vga_helper_funcs);
1723 if (i2c_bus->valid) {
1724 amdgpu_connector->ddc_bus = amdgpu_i2c_lookup(adev, i2c_bus);
1725 if (!amdgpu_connector->ddc_bus)
1726 DRM_ERROR("DVIA: Failed to assign ddc bus! Check dmesg for i2c errors.\n");
1727 }
1728 amdgpu_connector->dac_load_detect = true;
1729 drm_object_attach_property(&amdgpu_connector->base.base,
1730 adev->mode_info.load_detect_property,
1731 1);
1732 drm_object_attach_property(&amdgpu_connector->base.base,
1733 dev->mode_config.scaling_mode_property,
1734 DRM_MODE_SCALE_NONE);
1735 /* no HPD on analog connectors */
1736 amdgpu_connector->hpd.hpd = AMDGPU_HPD_NONE;
1737 connector->interlace_allowed = true;
1738 connector->doublescan_allowed = true;
1739 break;
1740 case DRM_MODE_CONNECTOR_DVII:
1741 case DRM_MODE_CONNECTOR_DVID:
1742 amdgpu_dig_connector = kzalloc(sizeof(struct amdgpu_connector_atom_dig), GFP_KERNEL);
1743 if (!amdgpu_dig_connector)
1744 goto failed;
1745 amdgpu_connector->con_priv = amdgpu_dig_connector;
1746 drm_connector_init(dev, &amdgpu_connector->base, &amdgpu_connector_dvi_funcs, connector_type);
1747 drm_connector_helper_add(&amdgpu_connector->base, &amdgpu_connector_dvi_helper_funcs);
1748 if (i2c_bus->valid) {
1749 amdgpu_connector->ddc_bus = amdgpu_i2c_lookup(adev, i2c_bus);
1750 if (!amdgpu_connector->ddc_bus)
1751 DRM_ERROR("DVI: Failed to assign ddc bus! Check dmesg for i2c errors.\n");
1752 }
1753 subpixel_order = SubPixelHorizontalRGB;
1754 drm_object_attach_property(&amdgpu_connector->base.base,
1755 adev->mode_info.coherent_mode_property,
1756 1);
1757 drm_object_attach_property(&amdgpu_connector->base.base,
1758 adev->mode_info.underscan_property,
1759 UNDERSCAN_OFF);
1760 drm_object_attach_property(&amdgpu_connector->base.base,
1761 adev->mode_info.underscan_hborder_property,
1762 0);
1763 drm_object_attach_property(&amdgpu_connector->base.base,
1764 adev->mode_info.underscan_vborder_property,
1765 0);
1766 drm_object_attach_property(&amdgpu_connector->base.base,
1767 dev->mode_config.scaling_mode_property,
1768 DRM_MODE_SCALE_NONE);
1769
1770 if (amdgpu_audio != 0) {
1771 drm_object_attach_property(&amdgpu_connector->base.base,
1772 adev->mode_info.audio_property,
1773 AMDGPU_AUDIO_AUTO);
1774 }
1775 drm_object_attach_property(&amdgpu_connector->base.base,
1776 adev->mode_info.dither_property,
1777 AMDGPU_FMT_DITHER_DISABLE);
1778 if (connector_type == DRM_MODE_CONNECTOR_DVII) {
1779 amdgpu_connector->dac_load_detect = true;
1780 drm_object_attach_property(&amdgpu_connector->base.base,
1781 adev->mode_info.load_detect_property,
1782 1);
1783 }
1784 connector->interlace_allowed = true;
1785 if (connector_type == DRM_MODE_CONNECTOR_DVII)
1786 connector->doublescan_allowed = true;
1787 else
1788 connector->doublescan_allowed = false;
1789 break;
1790 case DRM_MODE_CONNECTOR_HDMIA:
1791 case DRM_MODE_CONNECTOR_HDMIB:
1792 amdgpu_dig_connector = kzalloc(sizeof(struct amdgpu_connector_atom_dig), GFP_KERNEL);
1793 if (!amdgpu_dig_connector)
1794 goto failed;
1795 amdgpu_connector->con_priv = amdgpu_dig_connector;
1796 drm_connector_init(dev, &amdgpu_connector->base, &amdgpu_connector_dvi_funcs, connector_type);
1797 drm_connector_helper_add(&amdgpu_connector->base, &amdgpu_connector_dvi_helper_funcs);
1798 if (i2c_bus->valid) {
1799 amdgpu_connector->ddc_bus = amdgpu_i2c_lookup(adev, i2c_bus);
1800 if (!amdgpu_connector->ddc_bus)
1801 DRM_ERROR("HDMI: Failed to assign ddc bus! Check dmesg for i2c errors.\n");
1802 }
1803 drm_object_attach_property(&amdgpu_connector->base.base,
1804 adev->mode_info.coherent_mode_property,
1805 1);
1806 drm_object_attach_property(&amdgpu_connector->base.base,
1807 adev->mode_info.underscan_property,
1808 UNDERSCAN_OFF);
1809 drm_object_attach_property(&amdgpu_connector->base.base,
1810 adev->mode_info.underscan_hborder_property,
1811 0);
1812 drm_object_attach_property(&amdgpu_connector->base.base,
1813 adev->mode_info.underscan_vborder_property,
1814 0);
1815 drm_object_attach_property(&amdgpu_connector->base.base,
1816 dev->mode_config.scaling_mode_property,
1817 DRM_MODE_SCALE_NONE);
1818 if (amdgpu_audio != 0) {
1819 drm_object_attach_property(&amdgpu_connector->base.base,
1820 adev->mode_info.audio_property,
1821 AMDGPU_AUDIO_AUTO);
1822 }
1823 drm_object_attach_property(&amdgpu_connector->base.base,
1824 adev->mode_info.dither_property,
1825 AMDGPU_FMT_DITHER_DISABLE);
1826 subpixel_order = SubPixelHorizontalRGB;
1827 connector->interlace_allowed = true;
1828 if (connector_type == DRM_MODE_CONNECTOR_HDMIB)
1829 connector->doublescan_allowed = true;
1830 else
1831 connector->doublescan_allowed = false;
1832 break;
1833 case DRM_MODE_CONNECTOR_DisplayPort:
1834 amdgpu_dig_connector = kzalloc(sizeof(struct amdgpu_connector_atom_dig), GFP_KERNEL);
1835 if (!amdgpu_dig_connector)
1836 goto failed;
1837 amdgpu_connector->con_priv = amdgpu_dig_connector;
1838 drm_connector_init(dev, &amdgpu_connector->base, &amdgpu_connector_dp_funcs, connector_type);
1839 drm_connector_helper_add(&amdgpu_connector->base, &amdgpu_connector_dp_helper_funcs);
1840 if (i2c_bus->valid) {
1841 amdgpu_connector->ddc_bus = amdgpu_i2c_lookup(adev, i2c_bus);
1842 if (amdgpu_connector->ddc_bus)
1843 has_aux = true;
1844 else
1845 DRM_ERROR("DP: Failed to assign ddc bus! Check dmesg for i2c errors.\n");
1846 }
1847 subpixel_order = SubPixelHorizontalRGB;
1848 drm_object_attach_property(&amdgpu_connector->base.base,
1849 adev->mode_info.coherent_mode_property,
1850 1);
1851 drm_object_attach_property(&amdgpu_connector->base.base,
1852 adev->mode_info.underscan_property,
1853 UNDERSCAN_OFF);
1854 drm_object_attach_property(&amdgpu_connector->base.base,
1855 adev->mode_info.underscan_hborder_property,
1856 0);
1857 drm_object_attach_property(&amdgpu_connector->base.base,
1858 adev->mode_info.underscan_vborder_property,
1859 0);
1860 drm_object_attach_property(&amdgpu_connector->base.base,
1861 dev->mode_config.scaling_mode_property,
1862 DRM_MODE_SCALE_NONE);
1863 if (amdgpu_audio != 0) {
1864 drm_object_attach_property(&amdgpu_connector->base.base,
1865 adev->mode_info.audio_property,
1866 AMDGPU_AUDIO_AUTO);
1867 }
1868 drm_object_attach_property(&amdgpu_connector->base.base,
1869 adev->mode_info.dither_property,
1870 AMDGPU_FMT_DITHER_DISABLE);
1871 connector->interlace_allowed = true;
1872 /* in theory with a DP to VGA converter... */
1873 connector->doublescan_allowed = false;
1874 break;
1875 case DRM_MODE_CONNECTOR_eDP:
1876 amdgpu_dig_connector = kzalloc(sizeof(struct amdgpu_connector_atom_dig), GFP_KERNEL);
1877 if (!amdgpu_dig_connector)
1878 goto failed;
1879 amdgpu_connector->con_priv = amdgpu_dig_connector;
1880 drm_connector_init(dev, &amdgpu_connector->base, &amdgpu_connector_edp_funcs, connector_type);
1881 drm_connector_helper_add(&amdgpu_connector->base, &amdgpu_connector_dp_helper_funcs);
1882 if (i2c_bus->valid) {
1883 amdgpu_connector->ddc_bus = amdgpu_i2c_lookup(adev, i2c_bus);
1884 if (amdgpu_connector->ddc_bus)
1885 has_aux = true;
1886 else
1887 DRM_ERROR("DP: Failed to assign ddc bus! Check dmesg for i2c errors.\n");
1888 }
1889 drm_object_attach_property(&amdgpu_connector->base.base,
1890 dev->mode_config.scaling_mode_property,
1891 DRM_MODE_SCALE_FULLSCREEN);
1892 subpixel_order = SubPixelHorizontalRGB;
1893 connector->interlace_allowed = false;
1894 connector->doublescan_allowed = false;
1895 break;
1896 case DRM_MODE_CONNECTOR_LVDS:
1897 amdgpu_dig_connector = kzalloc(sizeof(struct amdgpu_connector_atom_dig), GFP_KERNEL);
1898 if (!amdgpu_dig_connector)
1899 goto failed;
1900 amdgpu_connector->con_priv = amdgpu_dig_connector;
1901 drm_connector_init(dev, &amdgpu_connector->base, &amdgpu_connector_lvds_funcs, connector_type);
1902 drm_connector_helper_add(&amdgpu_connector->base, &amdgpu_connector_lvds_helper_funcs);
1903 if (i2c_bus->valid) {
1904 amdgpu_connector->ddc_bus = amdgpu_i2c_lookup(adev, i2c_bus);
1905 if (!amdgpu_connector->ddc_bus)
1906 DRM_ERROR("LVDS: Failed to assign ddc bus! Check dmesg for i2c errors.\n");
1907 }
1908 drm_object_attach_property(&amdgpu_connector->base.base,
1909 dev->mode_config.scaling_mode_property,
1910 DRM_MODE_SCALE_FULLSCREEN);
1911 subpixel_order = SubPixelHorizontalRGB;
1912 connector->interlace_allowed = false;
1913 connector->doublescan_allowed = false;
1914 break;
1915 }
1916 }
1917
1918 if (amdgpu_connector->hpd.hpd == AMDGPU_HPD_NONE) {
1919 if (i2c_bus->valid) {
1920 connector->polled = DRM_CONNECTOR_POLL_CONNECT |
1921 DRM_CONNECTOR_POLL_DISCONNECT;
1922 }
1923 } else
1924 connector->polled = DRM_CONNECTOR_POLL_HPD;
1925
1926 connector->display_info.subpixel_order = subpixel_order;
1927 drm_connector_register(connector);
1928
1929 if (has_aux)
1930 amdgpu_atombios_dp_aux_init(amdgpu_connector);
1931
1932 return;
1933
1934 failed:
1935 drm_connector_cleanup(connector);
1936 kfree(connector);
1937 }
1938