1 /*
2 * Copyright 2011 Advanced Micro Devices, Inc.
3 * All Rights Reserved.
4 *
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the
7 * "Software"), to deal in the Software without restriction, including
8 * without limitation the rights to use, copy, modify, merge, publish,
9 * distribute, sub license, and/or sell copies of the Software, and to
10 * permit persons to whom the Software is furnished to do so, subject to
11 * the following conditions:
12 *
13 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
14 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
15 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
16 * THE COPYRIGHT HOLDERS, AUTHORS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM,
17 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
18 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
19 * USE OR OTHER DEALINGS IN THE SOFTWARE.
20 *
21 * The above copyright notice and this permission notice (including the
22 * next paragraph) shall be included in all copies or substantial portions
23 * of the Software.
24 *
25 */
26 /*
27 * Authors:
28 * Christian König <deathsimple@vodafone.de>
29 */
30
31 #include <linux/firmware.h>
32 #include <linux/module.h>
33 #include <drm/drmP.h>
34 #include <drm/drm.h>
35
36 #include "amdgpu.h"
37 #include "amdgpu_pm.h"
38 #include "amdgpu_uvd.h"
39 #include "cikd.h"
40 #include "uvd/uvd_4_2_d.h"
41
42 /* 1 second timeout */
43 #define UVD_IDLE_TIMEOUT msecs_to_jiffies(1000)
44
45 /* Firmware versions for VI */
46 #define FW_1_65_10 ((1 << 24) | (65 << 16) | (10 << 8))
47 #define FW_1_87_11 ((1 << 24) | (87 << 16) | (11 << 8))
48 #define FW_1_87_12 ((1 << 24) | (87 << 16) | (12 << 8))
49 #define FW_1_37_15 ((1 << 24) | (37 << 16) | (15 << 8))
50
51 /* Polaris10/11 firmware version */
52 #define FW_1_66_16 ((1 << 24) | (66 << 16) | (16 << 8))
53
54 /* Firmware Names */
55 #ifdef CONFIG_DRM_AMDGPU_CIK
56 #define FIRMWARE_BONAIRE "radeon/bonaire_uvd.bin"
57 #define FIRMWARE_KABINI "radeon/kabini_uvd.bin"
58 #define FIRMWARE_KAVERI "radeon/kaveri_uvd.bin"
59 #define FIRMWARE_HAWAII "radeon/hawaii_uvd.bin"
60 #define FIRMWARE_MULLINS "radeon/mullins_uvd.bin"
61 #endif
62 #define FIRMWARE_TONGA "amdgpu/tonga_uvd.bin"
63 #define FIRMWARE_CARRIZO "amdgpu/carrizo_uvd.bin"
64 #define FIRMWARE_FIJI "amdgpu/fiji_uvd.bin"
65 #define FIRMWARE_STONEY "amdgpu/stoney_uvd.bin"
66 #define FIRMWARE_POLARIS10 "amdgpu/polaris10_uvd.bin"
67 #define FIRMWARE_POLARIS11 "amdgpu/polaris11_uvd.bin"
68 #define FIRMWARE_POLARIS12 "amdgpu/polaris12_uvd.bin"
69
70 #define FIRMWARE_VEGA10 "amdgpu/vega10_uvd.bin"
71
72 #define mmUVD_GPCOM_VCPU_DATA0_VEGA10 (0x03c4 + 0x7e00)
73 #define mmUVD_GPCOM_VCPU_DATA1_VEGA10 (0x03c5 + 0x7e00)
74 #define mmUVD_GPCOM_VCPU_CMD_VEGA10 (0x03c3 + 0x7e00)
75 #define mmUVD_NO_OP_VEGA10 (0x03ff + 0x7e00)
76 #define mmUVD_ENGINE_CNTL_VEGA10 (0x03c6 + 0x7e00)
77
78 /**
79 * amdgpu_uvd_cs_ctx - Command submission parser context
80 *
81 * Used for emulating virtual memory support on UVD 4.2.
82 */
83 struct amdgpu_uvd_cs_ctx {
84 struct amdgpu_cs_parser *parser;
85 unsigned reg, count;
86 unsigned data0, data1;
87 unsigned idx;
88 unsigned ib_idx;
89
90 /* does the IB has a msg command */
91 bool has_msg_cmd;
92
93 /* minimum buffer sizes */
94 unsigned *buf_sizes;
95 };
96
97 #ifdef CONFIG_DRM_AMDGPU_CIK
98 MODULE_FIRMWARE(FIRMWARE_BONAIRE);
99 MODULE_FIRMWARE(FIRMWARE_KABINI);
100 MODULE_FIRMWARE(FIRMWARE_KAVERI);
101 MODULE_FIRMWARE(FIRMWARE_HAWAII);
102 MODULE_FIRMWARE(FIRMWARE_MULLINS);
103 #endif
104 MODULE_FIRMWARE(FIRMWARE_TONGA);
105 MODULE_FIRMWARE(FIRMWARE_CARRIZO);
106 MODULE_FIRMWARE(FIRMWARE_FIJI);
107 MODULE_FIRMWARE(FIRMWARE_STONEY);
108 MODULE_FIRMWARE(FIRMWARE_POLARIS10);
109 MODULE_FIRMWARE(FIRMWARE_POLARIS11);
110 MODULE_FIRMWARE(FIRMWARE_POLARIS12);
111
112 MODULE_FIRMWARE(FIRMWARE_VEGA10);
113
114 static void amdgpu_uvd_idle_work_handler(struct work_struct *work);
115
amdgpu_uvd_sw_init(struct amdgpu_device * adev)116 int amdgpu_uvd_sw_init(struct amdgpu_device *adev)
117 {
118 struct amdgpu_ring *ring;
119 struct amd_sched_rq *rq;
120 unsigned long bo_size;
121 const char *fw_name;
122 const struct common_firmware_header *hdr;
123 unsigned version_major, version_minor, family_id;
124 int i, r;
125
126 INIT_DELAYED_WORK(&adev->uvd.idle_work, amdgpu_uvd_idle_work_handler);
127
128 switch (adev->asic_type) {
129 #ifdef CONFIG_DRM_AMDGPU_CIK
130 case CHIP_BONAIRE:
131 fw_name = FIRMWARE_BONAIRE;
132 break;
133 case CHIP_KABINI:
134 fw_name = FIRMWARE_KABINI;
135 break;
136 case CHIP_KAVERI:
137 fw_name = FIRMWARE_KAVERI;
138 break;
139 case CHIP_HAWAII:
140 fw_name = FIRMWARE_HAWAII;
141 break;
142 case CHIP_MULLINS:
143 fw_name = FIRMWARE_MULLINS;
144 break;
145 #endif
146 case CHIP_TONGA:
147 fw_name = FIRMWARE_TONGA;
148 break;
149 case CHIP_FIJI:
150 fw_name = FIRMWARE_FIJI;
151 break;
152 case CHIP_CARRIZO:
153 fw_name = FIRMWARE_CARRIZO;
154 break;
155 case CHIP_STONEY:
156 fw_name = FIRMWARE_STONEY;
157 break;
158 case CHIP_POLARIS10:
159 fw_name = FIRMWARE_POLARIS10;
160 break;
161 case CHIP_POLARIS11:
162 fw_name = FIRMWARE_POLARIS11;
163 break;
164 case CHIP_VEGA10:
165 fw_name = FIRMWARE_VEGA10;
166 break;
167 case CHIP_POLARIS12:
168 fw_name = FIRMWARE_POLARIS12;
169 break;
170 default:
171 return -EINVAL;
172 }
173
174 r = request_firmware(&adev->uvd.fw, fw_name, adev->dev);
175 if (r) {
176 dev_err(adev->dev, "amdgpu_uvd: Can't load firmware \"%s\"\n",
177 fw_name);
178 return r;
179 }
180
181 r = amdgpu_ucode_validate(adev->uvd.fw);
182 if (r) {
183 dev_err(adev->dev, "amdgpu_uvd: Can't validate firmware \"%s\"\n",
184 fw_name);
185 release_firmware(adev->uvd.fw);
186 adev->uvd.fw = NULL;
187 return r;
188 }
189
190 /* Set the default UVD handles that the firmware can handle */
191 adev->uvd.max_handles = AMDGPU_DEFAULT_UVD_HANDLES;
192
193 hdr = (const struct common_firmware_header *)adev->uvd.fw->data;
194 family_id = le32_to_cpu(hdr->ucode_version) & 0xff;
195 version_major = (le32_to_cpu(hdr->ucode_version) >> 24) & 0xff;
196 version_minor = (le32_to_cpu(hdr->ucode_version) >> 8) & 0xff;
197 DRM_INFO("Found UVD firmware Version: %hu.%hu Family ID: %hu\n",
198 version_major, version_minor, family_id);
199
200 /*
201 * Limit the number of UVD handles depending on microcode major
202 * and minor versions. The firmware version which has 40 UVD
203 * instances support is 1.80. So all subsequent versions should
204 * also have the same support.
205 */
206 if ((version_major > 0x01) ||
207 ((version_major == 0x01) && (version_minor >= 0x50)))
208 adev->uvd.max_handles = AMDGPU_MAX_UVD_HANDLES;
209
210 adev->uvd.fw_version = ((version_major << 24) | (version_minor << 16) |
211 (family_id << 8));
212
213 if ((adev->asic_type == CHIP_POLARIS10 ||
214 adev->asic_type == CHIP_POLARIS11) &&
215 (adev->uvd.fw_version < FW_1_66_16))
216 DRM_ERROR("POLARIS10/11 UVD firmware version %hu.%hu is too old.\n",
217 version_major, version_minor);
218
219 bo_size = AMDGPU_UVD_STACK_SIZE + AMDGPU_UVD_HEAP_SIZE
220 + AMDGPU_UVD_SESSION_SIZE * adev->uvd.max_handles;
221 if (adev->firmware.load_type != AMDGPU_FW_LOAD_PSP)
222 bo_size += AMDGPU_GPU_PAGE_ALIGN(le32_to_cpu(hdr->ucode_size_bytes) + 8);
223
224 r = amdgpu_bo_create_kernel(adev, bo_size, PAGE_SIZE,
225 AMDGPU_GEM_DOMAIN_VRAM, &adev->uvd.vcpu_bo,
226 &adev->uvd.gpu_addr, &adev->uvd.cpu_addr);
227 if (r) {
228 dev_err(adev->dev, "(%d) failed to allocate UVD bo\n", r);
229 return r;
230 }
231
232 ring = &adev->uvd.ring;
233 rq = &ring->sched.sched_rq[AMD_SCHED_PRIORITY_NORMAL];
234 r = amd_sched_entity_init(&ring->sched, &adev->uvd.entity,
235 rq, amdgpu_sched_jobs);
236 if (r != 0) {
237 DRM_ERROR("Failed setting up UVD run queue.\n");
238 return r;
239 }
240
241 for (i = 0; i < adev->uvd.max_handles; ++i) {
242 atomic_set(&adev->uvd.handles[i], 0);
243 adev->uvd.filp[i] = NULL;
244 }
245
246 /* from uvd v5.0 HW addressing capacity increased to 64 bits */
247 if (!amdgpu_ip_block_version_cmp(adev, AMD_IP_BLOCK_TYPE_UVD, 5, 0))
248 adev->uvd.address_64_bit = true;
249
250 switch (adev->asic_type) {
251 case CHIP_TONGA:
252 adev->uvd.use_ctx_buf = adev->uvd.fw_version >= FW_1_65_10;
253 break;
254 case CHIP_CARRIZO:
255 adev->uvd.use_ctx_buf = adev->uvd.fw_version >= FW_1_87_11;
256 break;
257 case CHIP_FIJI:
258 adev->uvd.use_ctx_buf = adev->uvd.fw_version >= FW_1_87_12;
259 break;
260 case CHIP_STONEY:
261 adev->uvd.use_ctx_buf = adev->uvd.fw_version >= FW_1_37_15;
262 break;
263 default:
264 adev->uvd.use_ctx_buf = adev->asic_type >= CHIP_POLARIS10;
265 }
266
267 return 0;
268 }
269
amdgpu_uvd_sw_fini(struct amdgpu_device * adev)270 int amdgpu_uvd_sw_fini(struct amdgpu_device *adev)
271 {
272 kfree(adev->uvd.saved_bo);
273
274 amd_sched_entity_fini(&adev->uvd.ring.sched, &adev->uvd.entity);
275
276 amdgpu_bo_free_kernel(&adev->uvd.vcpu_bo,
277 &adev->uvd.gpu_addr,
278 (void **)&adev->uvd.cpu_addr);
279
280 amdgpu_ring_fini(&adev->uvd.ring);
281
282 release_firmware(adev->uvd.fw);
283
284 return 0;
285 }
286
amdgpu_uvd_suspend(struct amdgpu_device * adev)287 int amdgpu_uvd_suspend(struct amdgpu_device *adev)
288 {
289 unsigned size;
290 void *ptr;
291 int i;
292
293 if (adev->uvd.vcpu_bo == NULL)
294 return 0;
295
296 /* only valid for physical mode */
297 if (adev->asic_type < CHIP_POLARIS10) {
298 for (i = 0; i < adev->uvd.max_handles; ++i)
299 if (atomic_read(&adev->uvd.handles[i]))
300 break;
301
302 if (i == adev->uvd.max_handles)
303 return 0;
304 }
305
306 cancel_delayed_work_sync(&adev->uvd.idle_work);
307
308 size = amdgpu_bo_size(adev->uvd.vcpu_bo);
309 ptr = adev->uvd.cpu_addr;
310
311 adev->uvd.saved_bo = kmalloc(size, GFP_KERNEL);
312 if (!adev->uvd.saved_bo)
313 return -ENOMEM;
314
315 memcpy_fromio(adev->uvd.saved_bo, ptr, size);
316
317 return 0;
318 }
319
amdgpu_uvd_resume(struct amdgpu_device * adev)320 int amdgpu_uvd_resume(struct amdgpu_device *adev)
321 {
322 unsigned size;
323 void *ptr;
324
325 if (adev->uvd.vcpu_bo == NULL)
326 return -EINVAL;
327
328 size = amdgpu_bo_size(adev->uvd.vcpu_bo);
329 ptr = adev->uvd.cpu_addr;
330
331 if (adev->uvd.saved_bo != NULL) {
332 memcpy_toio(ptr, adev->uvd.saved_bo, size);
333 kfree(adev->uvd.saved_bo);
334 adev->uvd.saved_bo = NULL;
335 } else {
336 const struct common_firmware_header *hdr;
337 unsigned offset;
338
339 hdr = (const struct common_firmware_header *)adev->uvd.fw->data;
340 if (adev->firmware.load_type != AMDGPU_FW_LOAD_PSP) {
341 offset = le32_to_cpu(hdr->ucode_array_offset_bytes);
342 memcpy_toio(adev->uvd.cpu_addr, adev->uvd.fw->data + offset,
343 le32_to_cpu(hdr->ucode_size_bytes));
344 size -= le32_to_cpu(hdr->ucode_size_bytes);
345 ptr += le32_to_cpu(hdr->ucode_size_bytes);
346 }
347 memset_io(ptr, 0, size);
348 }
349
350 return 0;
351 }
352
amdgpu_uvd_free_handles(struct amdgpu_device * adev,struct drm_file * filp)353 void amdgpu_uvd_free_handles(struct amdgpu_device *adev, struct drm_file *filp)
354 {
355 struct amdgpu_ring *ring = &adev->uvd.ring;
356 int i, r;
357
358 for (i = 0; i < adev->uvd.max_handles; ++i) {
359 uint32_t handle = atomic_read(&adev->uvd.handles[i]);
360 if (handle != 0 && adev->uvd.filp[i] == filp) {
361 struct dma_fence *fence;
362
363 r = amdgpu_uvd_get_destroy_msg(ring, handle,
364 false, &fence);
365 if (r) {
366 DRM_ERROR("Error destroying UVD (%d)!\n", r);
367 continue;
368 }
369
370 dma_fence_wait(fence, false);
371 dma_fence_put(fence);
372
373 adev->uvd.filp[i] = NULL;
374 atomic_set(&adev->uvd.handles[i], 0);
375 }
376 }
377 }
378
amdgpu_uvd_force_into_uvd_segment(struct amdgpu_bo * abo)379 static void amdgpu_uvd_force_into_uvd_segment(struct amdgpu_bo *abo)
380 {
381 int i;
382 for (i = 0; i < abo->placement.num_placement; ++i) {
383 abo->placements[i].fpfn = 0 >> PAGE_SHIFT;
384 abo->placements[i].lpfn = (256 * 1024 * 1024) >> PAGE_SHIFT;
385 }
386 }
387
amdgpu_uvd_get_addr_from_ctx(struct amdgpu_uvd_cs_ctx * ctx)388 static u64 amdgpu_uvd_get_addr_from_ctx(struct amdgpu_uvd_cs_ctx *ctx)
389 {
390 uint32_t lo, hi;
391 uint64_t addr;
392
393 lo = amdgpu_get_ib_value(ctx->parser, ctx->ib_idx, ctx->data0);
394 hi = amdgpu_get_ib_value(ctx->parser, ctx->ib_idx, ctx->data1);
395 addr = ((uint64_t)lo) | (((uint64_t)hi) << 32);
396
397 return addr;
398 }
399
400 /**
401 * amdgpu_uvd_cs_pass1 - first parsing round
402 *
403 * @ctx: UVD parser context
404 *
405 * Make sure UVD message and feedback buffers are in VRAM and
406 * nobody is violating an 256MB boundary.
407 */
amdgpu_uvd_cs_pass1(struct amdgpu_uvd_cs_ctx * ctx)408 static int amdgpu_uvd_cs_pass1(struct amdgpu_uvd_cs_ctx *ctx)
409 {
410 struct amdgpu_bo_va_mapping *mapping;
411 struct amdgpu_bo *bo;
412 uint32_t cmd;
413 uint64_t addr = amdgpu_uvd_get_addr_from_ctx(ctx);
414 int r = 0;
415
416 mapping = amdgpu_cs_find_mapping(ctx->parser, addr, &bo);
417 if (mapping == NULL) {
418 DRM_ERROR("Can't find BO for addr 0x%08Lx\n", addr);
419 return -EINVAL;
420 }
421
422 if (!ctx->parser->adev->uvd.address_64_bit) {
423 /* check if it's a message or feedback command */
424 cmd = amdgpu_get_ib_value(ctx->parser, ctx->ib_idx, ctx->idx) >> 1;
425 if (cmd == 0x0 || cmd == 0x3) {
426 /* yes, force it into VRAM */
427 uint32_t domain = AMDGPU_GEM_DOMAIN_VRAM;
428 amdgpu_ttm_placement_from_domain(bo, domain);
429 }
430 amdgpu_uvd_force_into_uvd_segment(bo);
431
432 r = ttm_bo_validate(&bo->tbo, &bo->placement, false, false);
433 }
434
435 return r;
436 }
437
438 /**
439 * amdgpu_uvd_cs_msg_decode - handle UVD decode message
440 *
441 * @msg: pointer to message structure
442 * @buf_sizes: returned buffer sizes
443 *
444 * Peek into the decode message and calculate the necessary buffer sizes.
445 */
amdgpu_uvd_cs_msg_decode(struct amdgpu_device * adev,uint32_t * msg,unsigned buf_sizes[])446 static int amdgpu_uvd_cs_msg_decode(struct amdgpu_device *adev, uint32_t *msg,
447 unsigned buf_sizes[])
448 {
449 unsigned stream_type = msg[4];
450 unsigned width = msg[6];
451 unsigned height = msg[7];
452 unsigned dpb_size = msg[9];
453 unsigned pitch = msg[28];
454 unsigned level = msg[57];
455
456 unsigned width_in_mb = width / 16;
457 unsigned height_in_mb = ALIGN(height / 16, 2);
458 unsigned fs_in_mb = width_in_mb * height_in_mb;
459
460 unsigned image_size, tmp, min_dpb_size, num_dpb_buffer;
461 unsigned min_ctx_size = ~0;
462
463 image_size = width * height;
464 image_size += image_size / 2;
465 image_size = ALIGN(image_size, 1024);
466
467 switch (stream_type) {
468 case 0: /* H264 */
469 switch(level) {
470 case 30:
471 num_dpb_buffer = 8100 / fs_in_mb;
472 break;
473 case 31:
474 num_dpb_buffer = 18000 / fs_in_mb;
475 break;
476 case 32:
477 num_dpb_buffer = 20480 / fs_in_mb;
478 break;
479 case 41:
480 num_dpb_buffer = 32768 / fs_in_mb;
481 break;
482 case 42:
483 num_dpb_buffer = 34816 / fs_in_mb;
484 break;
485 case 50:
486 num_dpb_buffer = 110400 / fs_in_mb;
487 break;
488 case 51:
489 num_dpb_buffer = 184320 / fs_in_mb;
490 break;
491 default:
492 num_dpb_buffer = 184320 / fs_in_mb;
493 break;
494 }
495 num_dpb_buffer++;
496 if (num_dpb_buffer > 17)
497 num_dpb_buffer = 17;
498
499 /* reference picture buffer */
500 min_dpb_size = image_size * num_dpb_buffer;
501
502 /* macroblock context buffer */
503 min_dpb_size += width_in_mb * height_in_mb * num_dpb_buffer * 192;
504
505 /* IT surface buffer */
506 min_dpb_size += width_in_mb * height_in_mb * 32;
507 break;
508
509 case 1: /* VC1 */
510
511 /* reference picture buffer */
512 min_dpb_size = image_size * 3;
513
514 /* CONTEXT_BUFFER */
515 min_dpb_size += width_in_mb * height_in_mb * 128;
516
517 /* IT surface buffer */
518 min_dpb_size += width_in_mb * 64;
519
520 /* DB surface buffer */
521 min_dpb_size += width_in_mb * 128;
522
523 /* BP */
524 tmp = max(width_in_mb, height_in_mb);
525 min_dpb_size += ALIGN(tmp * 7 * 16, 64);
526 break;
527
528 case 3: /* MPEG2 */
529
530 /* reference picture buffer */
531 min_dpb_size = image_size * 3;
532 break;
533
534 case 4: /* MPEG4 */
535
536 /* reference picture buffer */
537 min_dpb_size = image_size * 3;
538
539 /* CM */
540 min_dpb_size += width_in_mb * height_in_mb * 64;
541
542 /* IT surface buffer */
543 min_dpb_size += ALIGN(width_in_mb * height_in_mb * 32, 64);
544 break;
545
546 case 7: /* H264 Perf */
547 switch(level) {
548 case 30:
549 num_dpb_buffer = 8100 / fs_in_mb;
550 break;
551 case 31:
552 num_dpb_buffer = 18000 / fs_in_mb;
553 break;
554 case 32:
555 num_dpb_buffer = 20480 / fs_in_mb;
556 break;
557 case 41:
558 num_dpb_buffer = 32768 / fs_in_mb;
559 break;
560 case 42:
561 num_dpb_buffer = 34816 / fs_in_mb;
562 break;
563 case 50:
564 num_dpb_buffer = 110400 / fs_in_mb;
565 break;
566 case 51:
567 num_dpb_buffer = 184320 / fs_in_mb;
568 break;
569 default:
570 num_dpb_buffer = 184320 / fs_in_mb;
571 break;
572 }
573 num_dpb_buffer++;
574 if (num_dpb_buffer > 17)
575 num_dpb_buffer = 17;
576
577 /* reference picture buffer */
578 min_dpb_size = image_size * num_dpb_buffer;
579
580 if (!adev->uvd.use_ctx_buf){
581 /* macroblock context buffer */
582 min_dpb_size +=
583 width_in_mb * height_in_mb * num_dpb_buffer * 192;
584
585 /* IT surface buffer */
586 min_dpb_size += width_in_mb * height_in_mb * 32;
587 } else {
588 /* macroblock context buffer */
589 min_ctx_size =
590 width_in_mb * height_in_mb * num_dpb_buffer * 192;
591 }
592 break;
593
594 case 8: /* MJPEG */
595 min_dpb_size = 0;
596 break;
597
598 case 16: /* H265 */
599 image_size = (ALIGN(width, 16) * ALIGN(height, 16) * 3) / 2;
600 image_size = ALIGN(image_size, 256);
601
602 num_dpb_buffer = (le32_to_cpu(msg[59]) & 0xff) + 2;
603 min_dpb_size = image_size * num_dpb_buffer;
604 min_ctx_size = ((width + 255) / 16) * ((height + 255) / 16)
605 * 16 * num_dpb_buffer + 52 * 1024;
606 break;
607
608 default:
609 DRM_ERROR("UVD codec not handled %d!\n", stream_type);
610 return -EINVAL;
611 }
612
613 if (width > pitch) {
614 DRM_ERROR("Invalid UVD decoding target pitch!\n");
615 return -EINVAL;
616 }
617
618 if (dpb_size < min_dpb_size) {
619 DRM_ERROR("Invalid dpb_size in UVD message (%d / %d)!\n",
620 dpb_size, min_dpb_size);
621 return -EINVAL;
622 }
623
624 buf_sizes[0x1] = dpb_size;
625 buf_sizes[0x2] = image_size;
626 buf_sizes[0x4] = min_ctx_size;
627 return 0;
628 }
629
630 /**
631 * amdgpu_uvd_cs_msg - handle UVD message
632 *
633 * @ctx: UVD parser context
634 * @bo: buffer object containing the message
635 * @offset: offset into the buffer object
636 *
637 * Peek into the UVD message and extract the session id.
638 * Make sure that we don't open up to many sessions.
639 */
amdgpu_uvd_cs_msg(struct amdgpu_uvd_cs_ctx * ctx,struct amdgpu_bo * bo,unsigned offset)640 static int amdgpu_uvd_cs_msg(struct amdgpu_uvd_cs_ctx *ctx,
641 struct amdgpu_bo *bo, unsigned offset)
642 {
643 struct amdgpu_device *adev = ctx->parser->adev;
644 int32_t *msg, msg_type, handle;
645 void *ptr;
646 long r;
647 int i;
648
649 if (offset & 0x3F) {
650 DRM_ERROR("UVD messages must be 64 byte aligned!\n");
651 return -EINVAL;
652 }
653
654 r = amdgpu_bo_kmap(bo, &ptr);
655 if (r) {
656 DRM_ERROR("Failed mapping the UVD message (%ld)!\n", r);
657 return r;
658 }
659
660 msg = ptr + offset;
661
662 msg_type = msg[1];
663 handle = msg[2];
664
665 if (handle == 0) {
666 DRM_ERROR("Invalid UVD handle!\n");
667 return -EINVAL;
668 }
669
670 switch (msg_type) {
671 case 0:
672 /* it's a create msg, calc image size (width * height) */
673 amdgpu_bo_kunmap(bo);
674
675 /* try to alloc a new handle */
676 for (i = 0; i < adev->uvd.max_handles; ++i) {
677 if (atomic_read(&adev->uvd.handles[i]) == handle) {
678 DRM_ERROR("Handle 0x%x already in use!\n", handle);
679 return -EINVAL;
680 }
681
682 if (!atomic_cmpxchg(&adev->uvd.handles[i], 0, handle)) {
683 adev->uvd.filp[i] = ctx->parser->filp;
684 return 0;
685 }
686 }
687
688 DRM_ERROR("No more free UVD handles!\n");
689 return -ENOSPC;
690
691 case 1:
692 /* it's a decode msg, calc buffer sizes */
693 r = amdgpu_uvd_cs_msg_decode(adev, msg, ctx->buf_sizes);
694 amdgpu_bo_kunmap(bo);
695 if (r)
696 return r;
697
698 /* validate the handle */
699 for (i = 0; i < adev->uvd.max_handles; ++i) {
700 if (atomic_read(&adev->uvd.handles[i]) == handle) {
701 if (adev->uvd.filp[i] != ctx->parser->filp) {
702 DRM_ERROR("UVD handle collision detected!\n");
703 return -EINVAL;
704 }
705 return 0;
706 }
707 }
708
709 DRM_ERROR("Invalid UVD handle 0x%x!\n", handle);
710 return -ENOENT;
711
712 case 2:
713 /* it's a destroy msg, free the handle */
714 for (i = 0; i < adev->uvd.max_handles; ++i)
715 atomic_cmpxchg(&adev->uvd.handles[i], handle, 0);
716 amdgpu_bo_kunmap(bo);
717 return 0;
718
719 default:
720 DRM_ERROR("Illegal UVD message type (%d)!\n", msg_type);
721 return -EINVAL;
722 }
723 BUG();
724 return -EINVAL;
725 }
726
727 /**
728 * amdgpu_uvd_cs_pass2 - second parsing round
729 *
730 * @ctx: UVD parser context
731 *
732 * Patch buffer addresses, make sure buffer sizes are correct.
733 */
amdgpu_uvd_cs_pass2(struct amdgpu_uvd_cs_ctx * ctx)734 static int amdgpu_uvd_cs_pass2(struct amdgpu_uvd_cs_ctx *ctx)
735 {
736 struct amdgpu_bo_va_mapping *mapping;
737 struct amdgpu_bo *bo;
738 uint32_t cmd;
739 uint64_t start, end;
740 uint64_t addr = amdgpu_uvd_get_addr_from_ctx(ctx);
741 int r;
742
743 mapping = amdgpu_cs_find_mapping(ctx->parser, addr, &bo);
744 if (mapping == NULL) {
745 DRM_ERROR("Can't find BO for addr 0x%08Lx\n", addr);
746 return -EINVAL;
747 }
748
749 start = amdgpu_bo_gpu_offset(bo);
750
751 end = (mapping->last + 1 - mapping->start);
752 end = end * AMDGPU_GPU_PAGE_SIZE + start;
753
754 addr -= mapping->start * AMDGPU_GPU_PAGE_SIZE;
755 start += addr;
756
757 amdgpu_set_ib_value(ctx->parser, ctx->ib_idx, ctx->data0,
758 lower_32_bits(start));
759 amdgpu_set_ib_value(ctx->parser, ctx->ib_idx, ctx->data1,
760 upper_32_bits(start));
761
762 cmd = amdgpu_get_ib_value(ctx->parser, ctx->ib_idx, ctx->idx) >> 1;
763 if (cmd < 0x4) {
764 if ((end - start) < ctx->buf_sizes[cmd]) {
765 DRM_ERROR("buffer (%d) to small (%d / %d)!\n", cmd,
766 (unsigned)(end - start),
767 ctx->buf_sizes[cmd]);
768 return -EINVAL;
769 }
770
771 } else if (cmd == 0x206) {
772 if ((end - start) < ctx->buf_sizes[4]) {
773 DRM_ERROR("buffer (%d) to small (%d / %d)!\n", cmd,
774 (unsigned)(end - start),
775 ctx->buf_sizes[4]);
776 return -EINVAL;
777 }
778 } else if ((cmd != 0x100) && (cmd != 0x204)) {
779 DRM_ERROR("invalid UVD command %X!\n", cmd);
780 return -EINVAL;
781 }
782
783 if (!ctx->parser->adev->uvd.address_64_bit) {
784 if ((start >> 28) != ((end - 1) >> 28)) {
785 DRM_ERROR("reloc %LX-%LX crossing 256MB boundary!\n",
786 start, end);
787 return -EINVAL;
788 }
789
790 if ((cmd == 0 || cmd == 0x3) &&
791 (start >> 28) != (ctx->parser->adev->uvd.gpu_addr >> 28)) {
792 DRM_ERROR("msg/fb buffer %LX-%LX out of 256MB segment!\n",
793 start, end);
794 return -EINVAL;
795 }
796 }
797
798 if (cmd == 0) {
799 ctx->has_msg_cmd = true;
800 r = amdgpu_uvd_cs_msg(ctx, bo, addr);
801 if (r)
802 return r;
803 } else if (!ctx->has_msg_cmd) {
804 DRM_ERROR("Message needed before other commands are send!\n");
805 return -EINVAL;
806 }
807
808 return 0;
809 }
810
811 /**
812 * amdgpu_uvd_cs_reg - parse register writes
813 *
814 * @ctx: UVD parser context
815 * @cb: callback function
816 *
817 * Parse the register writes, call cb on each complete command.
818 */
amdgpu_uvd_cs_reg(struct amdgpu_uvd_cs_ctx * ctx,int (* cb)(struct amdgpu_uvd_cs_ctx * ctx))819 static int amdgpu_uvd_cs_reg(struct amdgpu_uvd_cs_ctx *ctx,
820 int (*cb)(struct amdgpu_uvd_cs_ctx *ctx))
821 {
822 struct amdgpu_ib *ib = &ctx->parser->job->ibs[ctx->ib_idx];
823 int i, r;
824
825 ctx->idx++;
826 for (i = 0; i <= ctx->count; ++i) {
827 unsigned reg = ctx->reg + i;
828
829 if (ctx->idx >= ib->length_dw) {
830 DRM_ERROR("Register command after end of CS!\n");
831 return -EINVAL;
832 }
833
834 switch (reg) {
835 case mmUVD_GPCOM_VCPU_DATA0:
836 ctx->data0 = ctx->idx;
837 break;
838 case mmUVD_GPCOM_VCPU_DATA1:
839 ctx->data1 = ctx->idx;
840 break;
841 case mmUVD_GPCOM_VCPU_CMD:
842 r = cb(ctx);
843 if (r)
844 return r;
845 break;
846 case mmUVD_ENGINE_CNTL:
847 case mmUVD_NO_OP:
848 break;
849 default:
850 DRM_ERROR("Invalid reg 0x%X!\n", reg);
851 return -EINVAL;
852 }
853 ctx->idx++;
854 }
855 return 0;
856 }
857
858 /**
859 * amdgpu_uvd_cs_packets - parse UVD packets
860 *
861 * @ctx: UVD parser context
862 * @cb: callback function
863 *
864 * Parse the command stream packets.
865 */
amdgpu_uvd_cs_packets(struct amdgpu_uvd_cs_ctx * ctx,int (* cb)(struct amdgpu_uvd_cs_ctx * ctx))866 static int amdgpu_uvd_cs_packets(struct amdgpu_uvd_cs_ctx *ctx,
867 int (*cb)(struct amdgpu_uvd_cs_ctx *ctx))
868 {
869 struct amdgpu_ib *ib = &ctx->parser->job->ibs[ctx->ib_idx];
870 int r;
871
872 for (ctx->idx = 0 ; ctx->idx < ib->length_dw; ) {
873 uint32_t cmd = amdgpu_get_ib_value(ctx->parser, ctx->ib_idx, ctx->idx);
874 unsigned type = CP_PACKET_GET_TYPE(cmd);
875 switch (type) {
876 case PACKET_TYPE0:
877 ctx->reg = CP_PACKET0_GET_REG(cmd);
878 ctx->count = CP_PACKET_GET_COUNT(cmd);
879 r = amdgpu_uvd_cs_reg(ctx, cb);
880 if (r)
881 return r;
882 break;
883 case PACKET_TYPE2:
884 ++ctx->idx;
885 break;
886 default:
887 DRM_ERROR("Unknown packet type %d !\n", type);
888 return -EINVAL;
889 }
890 }
891 return 0;
892 }
893
894 /**
895 * amdgpu_uvd_ring_parse_cs - UVD command submission parser
896 *
897 * @parser: Command submission parser context
898 *
899 * Parse the command stream, patch in addresses as necessary.
900 */
amdgpu_uvd_ring_parse_cs(struct amdgpu_cs_parser * parser,uint32_t ib_idx)901 int amdgpu_uvd_ring_parse_cs(struct amdgpu_cs_parser *parser, uint32_t ib_idx)
902 {
903 struct amdgpu_uvd_cs_ctx ctx = {};
904 unsigned buf_sizes[] = {
905 [0x00000000] = 2048,
906 [0x00000001] = 0xFFFFFFFF,
907 [0x00000002] = 0xFFFFFFFF,
908 [0x00000003] = 2048,
909 [0x00000004] = 0xFFFFFFFF,
910 };
911 struct amdgpu_ib *ib = &parser->job->ibs[ib_idx];
912 int r;
913
914 parser->job->vm = NULL;
915 ib->gpu_addr = amdgpu_sa_bo_gpu_addr(ib->sa_bo);
916
917 if (ib->length_dw % 16) {
918 DRM_ERROR("UVD IB length (%d) not 16 dwords aligned!\n",
919 ib->length_dw);
920 return -EINVAL;
921 }
922
923 r = amdgpu_cs_sysvm_access_required(parser);
924 if (r)
925 return r;
926
927 ctx.parser = parser;
928 ctx.buf_sizes = buf_sizes;
929 ctx.ib_idx = ib_idx;
930
931 /* first round only required on chips without UVD 64 bit address support */
932 if (!parser->adev->uvd.address_64_bit) {
933 /* first round, make sure the buffers are actually in the UVD segment */
934 r = amdgpu_uvd_cs_packets(&ctx, amdgpu_uvd_cs_pass1);
935 if (r)
936 return r;
937 }
938
939 /* second round, patch buffer addresses into the command stream */
940 r = amdgpu_uvd_cs_packets(&ctx, amdgpu_uvd_cs_pass2);
941 if (r)
942 return r;
943
944 if (!ctx.has_msg_cmd) {
945 DRM_ERROR("UVD-IBs need a msg command!\n");
946 return -EINVAL;
947 }
948
949 return 0;
950 }
951
amdgpu_uvd_send_msg(struct amdgpu_ring * ring,struct amdgpu_bo * bo,bool direct,struct dma_fence ** fence)952 static int amdgpu_uvd_send_msg(struct amdgpu_ring *ring, struct amdgpu_bo *bo,
953 bool direct, struct dma_fence **fence)
954 {
955 struct ttm_validate_buffer tv;
956 struct ww_acquire_ctx ticket;
957 struct list_head head;
958 struct amdgpu_job *job;
959 struct amdgpu_ib *ib;
960 struct dma_fence *f = NULL;
961 struct amdgpu_device *adev = ring->adev;
962 uint64_t addr;
963 uint32_t data[4];
964 int i, r;
965
966 memset(&tv, 0, sizeof(tv));
967 tv.bo = &bo->tbo;
968
969 INIT_LIST_HEAD(&head);
970 list_add(&tv.head, &head);
971
972 r = ttm_eu_reserve_buffers(&ticket, &head, true, NULL);
973 if (r)
974 return r;
975
976 if (!ring->adev->uvd.address_64_bit) {
977 amdgpu_ttm_placement_from_domain(bo, AMDGPU_GEM_DOMAIN_VRAM);
978 amdgpu_uvd_force_into_uvd_segment(bo);
979 }
980
981 r = ttm_bo_validate(&bo->tbo, &bo->placement, true, false);
982 if (r)
983 goto err;
984
985 r = amdgpu_job_alloc_with_ib(adev, 64, &job);
986 if (r)
987 goto err;
988
989 if (adev->asic_type >= CHIP_VEGA10) {
990 data[0] = PACKET0(mmUVD_GPCOM_VCPU_DATA0_VEGA10, 0);
991 data[1] = PACKET0(mmUVD_GPCOM_VCPU_DATA1_VEGA10, 0);
992 data[2] = PACKET0(mmUVD_GPCOM_VCPU_CMD_VEGA10, 0);
993 data[3] = PACKET0(mmUVD_NO_OP_VEGA10, 0);
994 } else {
995 data[0] = PACKET0(mmUVD_GPCOM_VCPU_DATA0, 0);
996 data[1] = PACKET0(mmUVD_GPCOM_VCPU_DATA1, 0);
997 data[2] = PACKET0(mmUVD_GPCOM_VCPU_CMD, 0);
998 data[3] = PACKET0(mmUVD_NO_OP, 0);
999 }
1000
1001 ib = &job->ibs[0];
1002 addr = amdgpu_bo_gpu_offset(bo);
1003 ib->ptr[0] = data[0];
1004 ib->ptr[1] = addr;
1005 ib->ptr[2] = data[1];
1006 ib->ptr[3] = addr >> 32;
1007 ib->ptr[4] = data[2];
1008 ib->ptr[5] = 0;
1009 for (i = 6; i < 16; i += 2) {
1010 ib->ptr[i] = data[3];
1011 ib->ptr[i+1] = 0;
1012 }
1013 ib->length_dw = 16;
1014
1015 if (direct) {
1016 r = amdgpu_ib_schedule(ring, 1, ib, NULL, &f);
1017 job->fence = dma_fence_get(f);
1018 if (r)
1019 goto err_free;
1020
1021 amdgpu_job_free(job);
1022 } else {
1023 r = amdgpu_job_submit(job, ring, &adev->uvd.entity,
1024 AMDGPU_FENCE_OWNER_UNDEFINED, &f);
1025 if (r)
1026 goto err_free;
1027 }
1028
1029 ttm_eu_fence_buffer_objects(&ticket, &head, f);
1030
1031 if (fence)
1032 *fence = dma_fence_get(f);
1033 amdgpu_bo_unref(&bo);
1034 dma_fence_put(f);
1035
1036 return 0;
1037
1038 err_free:
1039 amdgpu_job_free(job);
1040
1041 err:
1042 ttm_eu_backoff_reservation(&ticket, &head);
1043 return r;
1044 }
1045
1046 /* multiple fence commands without any stream commands in between can
1047 crash the vcpu so just try to emmit a dummy create/destroy msg to
1048 avoid this */
amdgpu_uvd_get_create_msg(struct amdgpu_ring * ring,uint32_t handle,struct dma_fence ** fence)1049 int amdgpu_uvd_get_create_msg(struct amdgpu_ring *ring, uint32_t handle,
1050 struct dma_fence **fence)
1051 {
1052 struct amdgpu_device *adev = ring->adev;
1053 struct amdgpu_bo *bo;
1054 uint32_t *msg;
1055 int r, i;
1056
1057 r = amdgpu_bo_create(adev, 1024, PAGE_SIZE, true,
1058 AMDGPU_GEM_DOMAIN_VRAM,
1059 AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED |
1060 AMDGPU_GEM_CREATE_VRAM_CONTIGUOUS,
1061 NULL, NULL, 0, &bo);
1062 if (r)
1063 return r;
1064
1065 r = amdgpu_bo_reserve(bo, false);
1066 if (r) {
1067 amdgpu_bo_unref(&bo);
1068 return r;
1069 }
1070
1071 r = amdgpu_bo_kmap(bo, (void **)&msg);
1072 if (r) {
1073 amdgpu_bo_unreserve(bo);
1074 amdgpu_bo_unref(&bo);
1075 return r;
1076 }
1077
1078 /* stitch together an UVD create msg */
1079 msg[0] = cpu_to_le32(0x00000de4);
1080 msg[1] = cpu_to_le32(0x00000000);
1081 msg[2] = cpu_to_le32(handle);
1082 msg[3] = cpu_to_le32(0x00000000);
1083 msg[4] = cpu_to_le32(0x00000000);
1084 msg[5] = cpu_to_le32(0x00000000);
1085 msg[6] = cpu_to_le32(0x00000000);
1086 msg[7] = cpu_to_le32(0x00000780);
1087 msg[8] = cpu_to_le32(0x00000440);
1088 msg[9] = cpu_to_le32(0x00000000);
1089 msg[10] = cpu_to_le32(0x01b37000);
1090 for (i = 11; i < 1024; ++i)
1091 msg[i] = cpu_to_le32(0x0);
1092
1093 amdgpu_bo_kunmap(bo);
1094 amdgpu_bo_unreserve(bo);
1095
1096 return amdgpu_uvd_send_msg(ring, bo, true, fence);
1097 }
1098
amdgpu_uvd_get_destroy_msg(struct amdgpu_ring * ring,uint32_t handle,bool direct,struct dma_fence ** fence)1099 int amdgpu_uvd_get_destroy_msg(struct amdgpu_ring *ring, uint32_t handle,
1100 bool direct, struct dma_fence **fence)
1101 {
1102 struct amdgpu_device *adev = ring->adev;
1103 struct amdgpu_bo *bo;
1104 uint32_t *msg;
1105 int r, i;
1106
1107 r = amdgpu_bo_create(adev, 1024, PAGE_SIZE, true,
1108 AMDGPU_GEM_DOMAIN_VRAM,
1109 AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED |
1110 AMDGPU_GEM_CREATE_VRAM_CONTIGUOUS,
1111 NULL, NULL, 0, &bo);
1112 if (r)
1113 return r;
1114
1115 r = amdgpu_bo_reserve(bo, false);
1116 if (r) {
1117 amdgpu_bo_unref(&bo);
1118 return r;
1119 }
1120
1121 r = amdgpu_bo_kmap(bo, (void **)&msg);
1122 if (r) {
1123 amdgpu_bo_unreserve(bo);
1124 amdgpu_bo_unref(&bo);
1125 return r;
1126 }
1127
1128 /* stitch together an UVD destroy msg */
1129 msg[0] = cpu_to_le32(0x00000de4);
1130 msg[1] = cpu_to_le32(0x00000002);
1131 msg[2] = cpu_to_le32(handle);
1132 msg[3] = cpu_to_le32(0x00000000);
1133 for (i = 4; i < 1024; ++i)
1134 msg[i] = cpu_to_le32(0x0);
1135
1136 amdgpu_bo_kunmap(bo);
1137 amdgpu_bo_unreserve(bo);
1138
1139 return amdgpu_uvd_send_msg(ring, bo, direct, fence);
1140 }
1141
amdgpu_uvd_idle_work_handler(struct work_struct * work)1142 static void amdgpu_uvd_idle_work_handler(struct work_struct *work)
1143 {
1144 struct amdgpu_device *adev =
1145 container_of(work, struct amdgpu_device, uvd.idle_work.work);
1146 unsigned fences = amdgpu_fence_count_emitted(&adev->uvd.ring);
1147
1148 if (amdgpu_sriov_vf(adev))
1149 return;
1150
1151 if (fences == 0) {
1152 if (adev->pm.dpm_enabled) {
1153 amdgpu_dpm_enable_uvd(adev, false);
1154 } else {
1155 amdgpu_asic_set_uvd_clocks(adev, 0, 0);
1156 /* shutdown the UVD block */
1157 amdgpu_set_powergating_state(adev, AMD_IP_BLOCK_TYPE_UVD,
1158 AMD_PG_STATE_GATE);
1159 amdgpu_set_clockgating_state(adev, AMD_IP_BLOCK_TYPE_UVD,
1160 AMD_CG_STATE_GATE);
1161 }
1162 } else {
1163 schedule_delayed_work(&adev->uvd.idle_work, UVD_IDLE_TIMEOUT);
1164 }
1165 }
1166
amdgpu_uvd_ring_begin_use(struct amdgpu_ring * ring)1167 void amdgpu_uvd_ring_begin_use(struct amdgpu_ring *ring)
1168 {
1169 struct amdgpu_device *adev = ring->adev;
1170 bool set_clocks = !cancel_delayed_work_sync(&adev->uvd.idle_work);
1171
1172 if (amdgpu_sriov_vf(adev))
1173 return;
1174
1175 if (set_clocks) {
1176 if (adev->pm.dpm_enabled) {
1177 amdgpu_dpm_enable_uvd(adev, true);
1178 } else {
1179 amdgpu_asic_set_uvd_clocks(adev, 53300, 40000);
1180 amdgpu_set_clockgating_state(adev, AMD_IP_BLOCK_TYPE_UVD,
1181 AMD_CG_STATE_UNGATE);
1182 amdgpu_set_powergating_state(adev, AMD_IP_BLOCK_TYPE_UVD,
1183 AMD_PG_STATE_UNGATE);
1184 }
1185 }
1186 }
1187
amdgpu_uvd_ring_end_use(struct amdgpu_ring * ring)1188 void amdgpu_uvd_ring_end_use(struct amdgpu_ring *ring)
1189 {
1190 schedule_delayed_work(&ring->adev->uvd.idle_work, UVD_IDLE_TIMEOUT);
1191 }
1192
1193 /**
1194 * amdgpu_uvd_ring_test_ib - test ib execution
1195 *
1196 * @ring: amdgpu_ring pointer
1197 *
1198 * Test if we can successfully execute an IB
1199 */
amdgpu_uvd_ring_test_ib(struct amdgpu_ring * ring,long timeout)1200 int amdgpu_uvd_ring_test_ib(struct amdgpu_ring *ring, long timeout)
1201 {
1202 struct dma_fence *fence;
1203 long r;
1204
1205 r = amdgpu_uvd_get_create_msg(ring, 1, NULL);
1206 if (r) {
1207 DRM_ERROR("amdgpu: failed to get create msg (%ld).\n", r);
1208 goto error;
1209 }
1210
1211 r = amdgpu_uvd_get_destroy_msg(ring, 1, true, &fence);
1212 if (r) {
1213 DRM_ERROR("amdgpu: failed to get destroy ib (%ld).\n", r);
1214 goto error;
1215 }
1216
1217 r = dma_fence_wait_timeout(fence, false, timeout);
1218 if (r == 0) {
1219 DRM_ERROR("amdgpu: IB test timed out.\n");
1220 r = -ETIMEDOUT;
1221 } else if (r < 0) {
1222 DRM_ERROR("amdgpu: fence wait failed (%ld).\n", r);
1223 } else {
1224 DRM_INFO("ib test on ring %d succeeded\n", ring->idx);
1225 r = 0;
1226 }
1227
1228 dma_fence_put(fence);
1229
1230 error:
1231 return r;
1232 }
1233
1234 /**
1235 * amdgpu_uvd_used_handles - returns used UVD handles
1236 *
1237 * @adev: amdgpu_device pointer
1238 *
1239 * Returns the number of UVD handles in use
1240 */
amdgpu_uvd_used_handles(struct amdgpu_device * adev)1241 uint32_t amdgpu_uvd_used_handles(struct amdgpu_device *adev)
1242 {
1243 unsigned i;
1244 uint32_t used_handles = 0;
1245
1246 for (i = 0; i < adev->uvd.max_handles; ++i) {
1247 /*
1248 * Handles can be freed in any order, and not
1249 * necessarily linear. So we need to count
1250 * all non-zero handles.
1251 */
1252 if (atomic_read(&adev->uvd.handles[i]))
1253 used_handles++;
1254 }
1255
1256 return used_handles;
1257 }
1258