1 /*
2 * Copyright 2016 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 */
23 #include <linux/firmware.h>
24 #include <linux/slab.h>
25 #include <linux/module.h>
26 #include <drm/drmP.h>
27 #include "amdgpu.h"
28 #include "amdgpu_atombios.h"
29 #include "amdgpu_ih.h"
30 #include "amdgpu_uvd.h"
31 #include "amdgpu_vce.h"
32 #include "amdgpu_ucode.h"
33 #include "amdgpu_psp.h"
34 #include "atom.h"
35 #include "amd_pcie.h"
36
37 #include "vega10/soc15ip.h"
38 #include "vega10/UVD/uvd_7_0_offset.h"
39 #include "vega10/GC/gc_9_0_offset.h"
40 #include "vega10/GC/gc_9_0_sh_mask.h"
41 #include "vega10/SDMA0/sdma0_4_0_offset.h"
42 #include "vega10/SDMA1/sdma1_4_0_offset.h"
43 #include "vega10/HDP/hdp_4_0_offset.h"
44 #include "vega10/HDP/hdp_4_0_sh_mask.h"
45 #include "vega10/MP/mp_9_0_offset.h"
46 #include "vega10/MP/mp_9_0_sh_mask.h"
47 #include "vega10/SMUIO/smuio_9_0_offset.h"
48 #include "vega10/SMUIO/smuio_9_0_sh_mask.h"
49
50 #include "soc15.h"
51 #include "soc15_common.h"
52 #include "gfx_v9_0.h"
53 #include "gmc_v9_0.h"
54 #include "gfxhub_v1_0.h"
55 #include "mmhub_v1_0.h"
56 #include "vega10_ih.h"
57 #include "sdma_v4_0.h"
58 #include "uvd_v7_0.h"
59 #include "vce_v4_0.h"
60 #include "vcn_v1_0.h"
61 #include "amdgpu_powerplay.h"
62 #include "dce_virtual.h"
63 #include "mxgpu_ai.h"
64
65 #define mmFabricConfigAccessControl 0x0410
66 #define mmFabricConfigAccessControl_BASE_IDX 0
67 #define mmFabricConfigAccessControl_DEFAULT 0x00000000
68 //FabricConfigAccessControl
69 #define FabricConfigAccessControl__CfgRegInstAccEn__SHIFT 0x0
70 #define FabricConfigAccessControl__CfgRegInstAccRegLock__SHIFT 0x1
71 #define FabricConfigAccessControl__CfgRegInstID__SHIFT 0x10
72 #define FabricConfigAccessControl__CfgRegInstAccEn_MASK 0x00000001L
73 #define FabricConfigAccessControl__CfgRegInstAccRegLock_MASK 0x00000002L
74 #define FabricConfigAccessControl__CfgRegInstID_MASK 0x00FF0000L
75
76
77 #define mmDF_PIE_AON0_DfGlobalClkGater 0x00fc
78 #define mmDF_PIE_AON0_DfGlobalClkGater_BASE_IDX 0
79 //DF_PIE_AON0_DfGlobalClkGater
80 #define DF_PIE_AON0_DfGlobalClkGater__MGCGMode__SHIFT 0x0
81 #define DF_PIE_AON0_DfGlobalClkGater__MGCGMode_MASK 0x0000000FL
82
83 enum {
84 DF_MGCG_DISABLE = 0,
85 DF_MGCG_ENABLE_00_CYCLE_DELAY =1,
86 DF_MGCG_ENABLE_01_CYCLE_DELAY =2,
87 DF_MGCG_ENABLE_15_CYCLE_DELAY =13,
88 DF_MGCG_ENABLE_31_CYCLE_DELAY =14,
89 DF_MGCG_ENABLE_63_CYCLE_DELAY =15
90 };
91
92 #define mmMP0_MISC_CGTT_CTRL0 0x01b9
93 #define mmMP0_MISC_CGTT_CTRL0_BASE_IDX 0
94 #define mmMP0_MISC_LIGHT_SLEEP_CTRL 0x01ba
95 #define mmMP0_MISC_LIGHT_SLEEP_CTRL_BASE_IDX 0
96
97 /*
98 * Indirect registers accessor
99 */
soc15_pcie_rreg(struct amdgpu_device * adev,u32 reg)100 static u32 soc15_pcie_rreg(struct amdgpu_device *adev, u32 reg)
101 {
102 unsigned long flags, address, data;
103 u32 r;
104 struct nbio_pcie_index_data *nbio_pcie_id;
105
106 if (adev->flags & AMD_IS_APU)
107 nbio_pcie_id = &nbio_v7_0_pcie_index_data;
108 else
109 nbio_pcie_id = &nbio_v6_1_pcie_index_data;
110
111 address = nbio_pcie_id->index_offset;
112 data = nbio_pcie_id->data_offset;
113
114 spin_lock_irqsave(&adev->pcie_idx_lock, flags);
115 WREG32(address, reg);
116 (void)RREG32(address);
117 r = RREG32(data);
118 spin_unlock_irqrestore(&adev->pcie_idx_lock, flags);
119 return r;
120 }
121
soc15_pcie_wreg(struct amdgpu_device * adev,u32 reg,u32 v)122 static void soc15_pcie_wreg(struct amdgpu_device *adev, u32 reg, u32 v)
123 {
124 unsigned long flags, address, data;
125 struct nbio_pcie_index_data *nbio_pcie_id;
126
127 if (adev->flags & AMD_IS_APU)
128 nbio_pcie_id = &nbio_v7_0_pcie_index_data;
129 else
130 nbio_pcie_id = &nbio_v6_1_pcie_index_data;
131
132 address = nbio_pcie_id->index_offset;
133 data = nbio_pcie_id->data_offset;
134
135 spin_lock_irqsave(&adev->pcie_idx_lock, flags);
136 WREG32(address, reg);
137 (void)RREG32(address);
138 WREG32(data, v);
139 (void)RREG32(data);
140 spin_unlock_irqrestore(&adev->pcie_idx_lock, flags);
141 }
142
soc15_uvd_ctx_rreg(struct amdgpu_device * adev,u32 reg)143 static u32 soc15_uvd_ctx_rreg(struct amdgpu_device *adev, u32 reg)
144 {
145 unsigned long flags, address, data;
146 u32 r;
147
148 address = SOC15_REG_OFFSET(UVD, 0, mmUVD_CTX_INDEX);
149 data = SOC15_REG_OFFSET(UVD, 0, mmUVD_CTX_DATA);
150
151 spin_lock_irqsave(&adev->uvd_ctx_idx_lock, flags);
152 WREG32(address, ((reg) & 0x1ff));
153 r = RREG32(data);
154 spin_unlock_irqrestore(&adev->uvd_ctx_idx_lock, flags);
155 return r;
156 }
157
soc15_uvd_ctx_wreg(struct amdgpu_device * adev,u32 reg,u32 v)158 static void soc15_uvd_ctx_wreg(struct amdgpu_device *adev, u32 reg, u32 v)
159 {
160 unsigned long flags, address, data;
161
162 address = SOC15_REG_OFFSET(UVD, 0, mmUVD_CTX_INDEX);
163 data = SOC15_REG_OFFSET(UVD, 0, mmUVD_CTX_DATA);
164
165 spin_lock_irqsave(&adev->uvd_ctx_idx_lock, flags);
166 WREG32(address, ((reg) & 0x1ff));
167 WREG32(data, (v));
168 spin_unlock_irqrestore(&adev->uvd_ctx_idx_lock, flags);
169 }
170
soc15_didt_rreg(struct amdgpu_device * adev,u32 reg)171 static u32 soc15_didt_rreg(struct amdgpu_device *adev, u32 reg)
172 {
173 unsigned long flags, address, data;
174 u32 r;
175
176 address = SOC15_REG_OFFSET(GC, 0, mmDIDT_IND_INDEX);
177 data = SOC15_REG_OFFSET(GC, 0, mmDIDT_IND_DATA);
178
179 spin_lock_irqsave(&adev->didt_idx_lock, flags);
180 WREG32(address, (reg));
181 r = RREG32(data);
182 spin_unlock_irqrestore(&adev->didt_idx_lock, flags);
183 return r;
184 }
185
soc15_didt_wreg(struct amdgpu_device * adev,u32 reg,u32 v)186 static void soc15_didt_wreg(struct amdgpu_device *adev, u32 reg, u32 v)
187 {
188 unsigned long flags, address, data;
189
190 address = SOC15_REG_OFFSET(GC, 0, mmDIDT_IND_INDEX);
191 data = SOC15_REG_OFFSET(GC, 0, mmDIDT_IND_DATA);
192
193 spin_lock_irqsave(&adev->didt_idx_lock, flags);
194 WREG32(address, (reg));
195 WREG32(data, (v));
196 spin_unlock_irqrestore(&adev->didt_idx_lock, flags);
197 }
198
soc15_gc_cac_rreg(struct amdgpu_device * adev,u32 reg)199 static u32 soc15_gc_cac_rreg(struct amdgpu_device *adev, u32 reg)
200 {
201 unsigned long flags;
202 u32 r;
203
204 spin_lock_irqsave(&adev->gc_cac_idx_lock, flags);
205 WREG32_SOC15(GC, 0, mmGC_CAC_IND_INDEX, (reg));
206 r = RREG32_SOC15(GC, 0, mmGC_CAC_IND_DATA);
207 spin_unlock_irqrestore(&adev->gc_cac_idx_lock, flags);
208 return r;
209 }
210
soc15_gc_cac_wreg(struct amdgpu_device * adev,u32 reg,u32 v)211 static void soc15_gc_cac_wreg(struct amdgpu_device *adev, u32 reg, u32 v)
212 {
213 unsigned long flags;
214
215 spin_lock_irqsave(&adev->gc_cac_idx_lock, flags);
216 WREG32_SOC15(GC, 0, mmGC_CAC_IND_INDEX, (reg));
217 WREG32_SOC15(GC, 0, mmGC_CAC_IND_DATA, (v));
218 spin_unlock_irqrestore(&adev->gc_cac_idx_lock, flags);
219 }
220
soc15_se_cac_rreg(struct amdgpu_device * adev,u32 reg)221 static u32 soc15_se_cac_rreg(struct amdgpu_device *adev, u32 reg)
222 {
223 unsigned long flags;
224 u32 r;
225
226 spin_lock_irqsave(&adev->se_cac_idx_lock, flags);
227 WREG32_SOC15(GC, 0, mmSE_CAC_IND_INDEX, (reg));
228 r = RREG32_SOC15(GC, 0, mmSE_CAC_IND_DATA);
229 spin_unlock_irqrestore(&adev->se_cac_idx_lock, flags);
230 return r;
231 }
232
soc15_se_cac_wreg(struct amdgpu_device * adev,u32 reg,u32 v)233 static void soc15_se_cac_wreg(struct amdgpu_device *adev, u32 reg, u32 v)
234 {
235 unsigned long flags;
236
237 spin_lock_irqsave(&adev->se_cac_idx_lock, flags);
238 WREG32_SOC15(GC, 0, mmSE_CAC_IND_INDEX, (reg));
239 WREG32_SOC15(GC, 0, mmSE_CAC_IND_DATA, (v));
240 spin_unlock_irqrestore(&adev->se_cac_idx_lock, flags);
241 }
242
soc15_get_config_memsize(struct amdgpu_device * adev)243 static u32 soc15_get_config_memsize(struct amdgpu_device *adev)
244 {
245 if (adev->flags & AMD_IS_APU)
246 return nbio_v7_0_get_memsize(adev);
247 else
248 return nbio_v6_1_get_memsize(adev);
249 }
250
251 static const u32 vega10_golden_init[] =
252 {
253 };
254
255 static const u32 raven_golden_init[] =
256 {
257 };
258
soc15_init_golden_registers(struct amdgpu_device * adev)259 static void soc15_init_golden_registers(struct amdgpu_device *adev)
260 {
261 /* Some of the registers might be dependent on GRBM_GFX_INDEX */
262 mutex_lock(&adev->grbm_idx_mutex);
263
264 switch (adev->asic_type) {
265 case CHIP_VEGA10:
266 amdgpu_program_register_sequence(adev,
267 vega10_golden_init,
268 (const u32)ARRAY_SIZE(vega10_golden_init));
269 break;
270 case CHIP_RAVEN:
271 amdgpu_program_register_sequence(adev,
272 raven_golden_init,
273 (const u32)ARRAY_SIZE(raven_golden_init));
274 break;
275 default:
276 break;
277 }
278 mutex_unlock(&adev->grbm_idx_mutex);
279 }
soc15_get_xclk(struct amdgpu_device * adev)280 static u32 soc15_get_xclk(struct amdgpu_device *adev)
281 {
282 u32 reference_clock = adev->clock.spll.reference_freq;
283
284 if (adev->asic_type == CHIP_RAVEN)
285 return reference_clock / 4;
286
287 return reference_clock;
288 }
289
290
soc15_grbm_select(struct amdgpu_device * adev,u32 me,u32 pipe,u32 queue,u32 vmid)291 void soc15_grbm_select(struct amdgpu_device *adev,
292 u32 me, u32 pipe, u32 queue, u32 vmid)
293 {
294 u32 grbm_gfx_cntl = 0;
295 grbm_gfx_cntl = REG_SET_FIELD(grbm_gfx_cntl, GRBM_GFX_CNTL, PIPEID, pipe);
296 grbm_gfx_cntl = REG_SET_FIELD(grbm_gfx_cntl, GRBM_GFX_CNTL, MEID, me);
297 grbm_gfx_cntl = REG_SET_FIELD(grbm_gfx_cntl, GRBM_GFX_CNTL, VMID, vmid);
298 grbm_gfx_cntl = REG_SET_FIELD(grbm_gfx_cntl, GRBM_GFX_CNTL, QUEUEID, queue);
299
300 WREG32(SOC15_REG_OFFSET(GC, 0, mmGRBM_GFX_CNTL), grbm_gfx_cntl);
301 }
302
soc15_vga_set_state(struct amdgpu_device * adev,bool state)303 static void soc15_vga_set_state(struct amdgpu_device *adev, bool state)
304 {
305 /* todo */
306 }
307
soc15_read_disabled_bios(struct amdgpu_device * adev)308 static bool soc15_read_disabled_bios(struct amdgpu_device *adev)
309 {
310 /* todo */
311 return false;
312 }
313
soc15_read_bios_from_rom(struct amdgpu_device * adev,u8 * bios,u32 length_bytes)314 static bool soc15_read_bios_from_rom(struct amdgpu_device *adev,
315 u8 *bios, u32 length_bytes)
316 {
317 u32 *dw_ptr;
318 u32 i, length_dw;
319
320 if (bios == NULL)
321 return false;
322 if (length_bytes == 0)
323 return false;
324 /* APU vbios image is part of sbios image */
325 if (adev->flags & AMD_IS_APU)
326 return false;
327
328 dw_ptr = (u32 *)bios;
329 length_dw = ALIGN(length_bytes, 4) / 4;
330
331 /* set rom index to 0 */
332 WREG32(SOC15_REG_OFFSET(SMUIO, 0, mmROM_INDEX), 0);
333 /* read out the rom data */
334 for (i = 0; i < length_dw; i++)
335 dw_ptr[i] = RREG32(SOC15_REG_OFFSET(SMUIO, 0, mmROM_DATA));
336
337 return true;
338 }
339
340 static struct amdgpu_allowed_register_entry soc15_allowed_read_registers[] = {
341 { SOC15_REG_OFFSET(GC, 0, mmGRBM_STATUS)},
342 { SOC15_REG_OFFSET(GC, 0, mmGRBM_STATUS2)},
343 { SOC15_REG_OFFSET(GC, 0, mmGRBM_STATUS_SE0)},
344 { SOC15_REG_OFFSET(GC, 0, mmGRBM_STATUS_SE1)},
345 { SOC15_REG_OFFSET(GC, 0, mmGRBM_STATUS_SE2)},
346 { SOC15_REG_OFFSET(GC, 0, mmGRBM_STATUS_SE3)},
347 { SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_STATUS_REG)},
348 { SOC15_REG_OFFSET(SDMA1, 0, mmSDMA1_STATUS_REG)},
349 { SOC15_REG_OFFSET(GC, 0, mmCP_STAT)},
350 { SOC15_REG_OFFSET(GC, 0, mmCP_STALLED_STAT1)},
351 { SOC15_REG_OFFSET(GC, 0, mmCP_STALLED_STAT2)},
352 { SOC15_REG_OFFSET(GC, 0, mmCP_STALLED_STAT3)},
353 { SOC15_REG_OFFSET(GC, 0, mmCP_CPF_BUSY_STAT)},
354 { SOC15_REG_OFFSET(GC, 0, mmCP_CPF_STALLED_STAT1)},
355 { SOC15_REG_OFFSET(GC, 0, mmCP_CPF_STATUS)},
356 { SOC15_REG_OFFSET(GC, 0, mmCP_CPC_STALLED_STAT1)},
357 { SOC15_REG_OFFSET(GC, 0, mmCP_CPC_STATUS)},
358 { SOC15_REG_OFFSET(GC, 0, mmGB_ADDR_CONFIG)},
359 };
360
soc15_read_indexed_register(struct amdgpu_device * adev,u32 se_num,u32 sh_num,u32 reg_offset)361 static uint32_t soc15_read_indexed_register(struct amdgpu_device *adev, u32 se_num,
362 u32 sh_num, u32 reg_offset)
363 {
364 uint32_t val;
365
366 mutex_lock(&adev->grbm_idx_mutex);
367 if (se_num != 0xffffffff || sh_num != 0xffffffff)
368 amdgpu_gfx_select_se_sh(adev, se_num, sh_num, 0xffffffff);
369
370 val = RREG32(reg_offset);
371
372 if (se_num != 0xffffffff || sh_num != 0xffffffff)
373 amdgpu_gfx_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff);
374 mutex_unlock(&adev->grbm_idx_mutex);
375 return val;
376 }
377
soc15_get_register_value(struct amdgpu_device * adev,bool indexed,u32 se_num,u32 sh_num,u32 reg_offset)378 static uint32_t soc15_get_register_value(struct amdgpu_device *adev,
379 bool indexed, u32 se_num,
380 u32 sh_num, u32 reg_offset)
381 {
382 if (indexed) {
383 return soc15_read_indexed_register(adev, se_num, sh_num, reg_offset);
384 } else {
385 switch (reg_offset) {
386 case SOC15_REG_OFFSET(GC, 0, mmGB_ADDR_CONFIG):
387 return adev->gfx.config.gb_addr_config;
388 default:
389 return RREG32(reg_offset);
390 }
391 }
392 }
393
soc15_read_register(struct amdgpu_device * adev,u32 se_num,u32 sh_num,u32 reg_offset,u32 * value)394 static int soc15_read_register(struct amdgpu_device *adev, u32 se_num,
395 u32 sh_num, u32 reg_offset, u32 *value)
396 {
397 uint32_t i;
398
399 *value = 0;
400 for (i = 0; i < ARRAY_SIZE(soc15_allowed_read_registers); i++) {
401 if (reg_offset != soc15_allowed_read_registers[i].reg_offset)
402 continue;
403
404 *value = soc15_get_register_value(adev,
405 soc15_allowed_read_registers[i].grbm_indexed,
406 se_num, sh_num, reg_offset);
407 return 0;
408 }
409 return -EINVAL;
410 }
411
soc15_gpu_pci_config_reset(struct amdgpu_device * adev)412 static void soc15_gpu_pci_config_reset(struct amdgpu_device *adev)
413 {
414 u32 i;
415
416 dev_info(adev->dev, "GPU pci config reset\n");
417
418 /* disable BM */
419 pci_clear_master(adev->pdev);
420 /* reset */
421 amdgpu_pci_config_reset(adev);
422
423 udelay(100);
424
425 /* wait for asic to come out of reset */
426 for (i = 0; i < adev->usec_timeout; i++) {
427 u32 memsize = (adev->flags & AMD_IS_APU) ?
428 nbio_v7_0_get_memsize(adev) :
429 nbio_v6_1_get_memsize(adev);
430 if (memsize != 0xffffffff)
431 break;
432 udelay(1);
433 }
434
435 }
436
soc15_asic_reset(struct amdgpu_device * adev)437 static int soc15_asic_reset(struct amdgpu_device *adev)
438 {
439 amdgpu_atombios_scratch_regs_engine_hung(adev, true);
440
441 soc15_gpu_pci_config_reset(adev);
442
443 amdgpu_atombios_scratch_regs_engine_hung(adev, false);
444
445 return 0;
446 }
447
448 /*static int soc15_set_uvd_clock(struct amdgpu_device *adev, u32 clock,
449 u32 cntl_reg, u32 status_reg)
450 {
451 return 0;
452 }*/
453
soc15_set_uvd_clocks(struct amdgpu_device * adev,u32 vclk,u32 dclk)454 static int soc15_set_uvd_clocks(struct amdgpu_device *adev, u32 vclk, u32 dclk)
455 {
456 /*int r;
457
458 r = soc15_set_uvd_clock(adev, vclk, ixCG_VCLK_CNTL, ixCG_VCLK_STATUS);
459 if (r)
460 return r;
461
462 r = soc15_set_uvd_clock(adev, dclk, ixCG_DCLK_CNTL, ixCG_DCLK_STATUS);
463 */
464 return 0;
465 }
466
soc15_set_vce_clocks(struct amdgpu_device * adev,u32 evclk,u32 ecclk)467 static int soc15_set_vce_clocks(struct amdgpu_device *adev, u32 evclk, u32 ecclk)
468 {
469 /* todo */
470
471 return 0;
472 }
473
soc15_pcie_gen3_enable(struct amdgpu_device * adev)474 static void soc15_pcie_gen3_enable(struct amdgpu_device *adev)
475 {
476 if (pci_is_root_bus(adev->pdev->bus))
477 return;
478
479 if (amdgpu_pcie_gen2 == 0)
480 return;
481
482 if (adev->flags & AMD_IS_APU)
483 return;
484
485 if (!(adev->pm.pcie_gen_mask & (CAIL_PCIE_LINK_SPEED_SUPPORT_GEN2 |
486 CAIL_PCIE_LINK_SPEED_SUPPORT_GEN3)))
487 return;
488
489 /* todo */
490 }
491
soc15_program_aspm(struct amdgpu_device * adev)492 static void soc15_program_aspm(struct amdgpu_device *adev)
493 {
494
495 if (amdgpu_aspm == 0)
496 return;
497
498 /* todo */
499 }
500
soc15_enable_doorbell_aperture(struct amdgpu_device * adev,bool enable)501 static void soc15_enable_doorbell_aperture(struct amdgpu_device *adev,
502 bool enable)
503 {
504 if (adev->flags & AMD_IS_APU) {
505 nbio_v7_0_enable_doorbell_aperture(adev, enable);
506 } else {
507 nbio_v6_1_enable_doorbell_aperture(adev, enable);
508 nbio_v6_1_enable_doorbell_selfring_aperture(adev, enable);
509 }
510 }
511
512 static const struct amdgpu_ip_block_version vega10_common_ip_block =
513 {
514 .type = AMD_IP_BLOCK_TYPE_COMMON,
515 .major = 2,
516 .minor = 0,
517 .rev = 0,
518 .funcs = &soc15_common_ip_funcs,
519 };
520
soc15_set_ip_blocks(struct amdgpu_device * adev)521 int soc15_set_ip_blocks(struct amdgpu_device *adev)
522 {
523 nbio_v6_1_detect_hw_virt(adev);
524
525 if (amdgpu_sriov_vf(adev))
526 adev->virt.ops = &xgpu_ai_virt_ops;
527
528 switch (adev->asic_type) {
529 case CHIP_VEGA10:
530 amdgpu_ip_block_add(adev, &vega10_common_ip_block);
531 amdgpu_ip_block_add(adev, &gmc_v9_0_ip_block);
532 amdgpu_ip_block_add(adev, &vega10_ih_ip_block);
533 if (amdgpu_fw_load_type == 2 || amdgpu_fw_load_type == -1)
534 amdgpu_ip_block_add(adev, &psp_v3_1_ip_block);
535 if (!amdgpu_sriov_vf(adev))
536 amdgpu_ip_block_add(adev, &amdgpu_pp_ip_block);
537 if (adev->enable_virtual_display || amdgpu_sriov_vf(adev))
538 amdgpu_ip_block_add(adev, &dce_virtual_ip_block);
539 amdgpu_ip_block_add(adev, &gfx_v9_0_ip_block);
540 amdgpu_ip_block_add(adev, &sdma_v4_0_ip_block);
541 amdgpu_ip_block_add(adev, &uvd_v7_0_ip_block);
542 amdgpu_ip_block_add(adev, &vce_v4_0_ip_block);
543 break;
544 case CHIP_RAVEN:
545 amdgpu_ip_block_add(adev, &vega10_common_ip_block);
546 amdgpu_ip_block_add(adev, &gmc_v9_0_ip_block);
547 amdgpu_ip_block_add(adev, &vega10_ih_ip_block);
548 amdgpu_ip_block_add(adev, &psp_v10_0_ip_block);
549 amdgpu_ip_block_add(adev, &amdgpu_pp_ip_block);
550 if (adev->enable_virtual_display || amdgpu_sriov_vf(adev))
551 amdgpu_ip_block_add(adev, &dce_virtual_ip_block);
552 amdgpu_ip_block_add(adev, &gfx_v9_0_ip_block);
553 amdgpu_ip_block_add(adev, &sdma_v4_0_ip_block);
554 amdgpu_ip_block_add(adev, &vcn_v1_0_ip_block);
555 break;
556 default:
557 return -EINVAL;
558 }
559
560 return 0;
561 }
562
soc15_get_rev_id(struct amdgpu_device * adev)563 static uint32_t soc15_get_rev_id(struct amdgpu_device *adev)
564 {
565 if (adev->flags & AMD_IS_APU)
566 return nbio_v7_0_get_rev_id(adev);
567 else
568 return nbio_v6_1_get_rev_id(adev);
569 }
570
571 static const struct amdgpu_asic_funcs soc15_asic_funcs =
572 {
573 .read_disabled_bios = &soc15_read_disabled_bios,
574 .read_bios_from_rom = &soc15_read_bios_from_rom,
575 .read_register = &soc15_read_register,
576 .reset = &soc15_asic_reset,
577 .set_vga_state = &soc15_vga_set_state,
578 .get_xclk = &soc15_get_xclk,
579 .set_uvd_clocks = &soc15_set_uvd_clocks,
580 .set_vce_clocks = &soc15_set_vce_clocks,
581 .get_config_memsize = &soc15_get_config_memsize,
582 };
583
soc15_common_early_init(void * handle)584 static int soc15_common_early_init(void *handle)
585 {
586 bool psp_enabled = false;
587 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
588
589 adev->smc_rreg = NULL;
590 adev->smc_wreg = NULL;
591 adev->pcie_rreg = &soc15_pcie_rreg;
592 adev->pcie_wreg = &soc15_pcie_wreg;
593 adev->uvd_ctx_rreg = &soc15_uvd_ctx_rreg;
594 adev->uvd_ctx_wreg = &soc15_uvd_ctx_wreg;
595 adev->didt_rreg = &soc15_didt_rreg;
596 adev->didt_wreg = &soc15_didt_wreg;
597 adev->gc_cac_rreg = &soc15_gc_cac_rreg;
598 adev->gc_cac_wreg = &soc15_gc_cac_wreg;
599 adev->se_cac_rreg = &soc15_se_cac_rreg;
600 adev->se_cac_wreg = &soc15_se_cac_wreg;
601
602 adev->asic_funcs = &soc15_asic_funcs;
603
604 if (amdgpu_get_ip_block(adev, AMD_IP_BLOCK_TYPE_PSP) &&
605 (amdgpu_ip_block_mask & (1 << AMD_IP_BLOCK_TYPE_PSP)))
606 psp_enabled = true;
607
608 /*
609 * nbio need be used for both sdma and gfx9, but only
610 * initializes once
611 */
612 switch(adev->asic_type) {
613 case CHIP_VEGA10:
614 nbio_v6_1_init(adev);
615 break;
616 case CHIP_RAVEN:
617 nbio_v7_0_init(adev);
618 break;
619 default:
620 return -EINVAL;
621 }
622
623 adev->rev_id = soc15_get_rev_id(adev);
624 adev->external_rev_id = 0xFF;
625 switch (adev->asic_type) {
626 case CHIP_VEGA10:
627 adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG |
628 AMD_CG_SUPPORT_GFX_MGLS |
629 AMD_CG_SUPPORT_GFX_RLC_LS |
630 AMD_CG_SUPPORT_GFX_CP_LS |
631 AMD_CG_SUPPORT_GFX_3D_CGCG |
632 AMD_CG_SUPPORT_GFX_3D_CGLS |
633 AMD_CG_SUPPORT_GFX_CGCG |
634 AMD_CG_SUPPORT_GFX_CGLS |
635 AMD_CG_SUPPORT_BIF_MGCG |
636 AMD_CG_SUPPORT_BIF_LS |
637 AMD_CG_SUPPORT_HDP_LS |
638 AMD_CG_SUPPORT_DRM_MGCG |
639 AMD_CG_SUPPORT_DRM_LS |
640 AMD_CG_SUPPORT_ROM_MGCG |
641 AMD_CG_SUPPORT_DF_MGCG |
642 AMD_CG_SUPPORT_SDMA_MGCG |
643 AMD_CG_SUPPORT_SDMA_LS |
644 AMD_CG_SUPPORT_MC_MGCG |
645 AMD_CG_SUPPORT_MC_LS;
646 adev->pg_flags = 0;
647 adev->external_rev_id = 0x1;
648 break;
649 case CHIP_RAVEN:
650 adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG |
651 AMD_CG_SUPPORT_GFX_MGLS |
652 AMD_CG_SUPPORT_GFX_RLC_LS |
653 AMD_CG_SUPPORT_GFX_CP_LS |
654 AMD_CG_SUPPORT_GFX_3D_CGCG |
655 AMD_CG_SUPPORT_GFX_3D_CGLS |
656 AMD_CG_SUPPORT_GFX_CGCG |
657 AMD_CG_SUPPORT_GFX_CGLS |
658 AMD_CG_SUPPORT_BIF_MGCG |
659 AMD_CG_SUPPORT_BIF_LS |
660 AMD_CG_SUPPORT_HDP_MGCG |
661 AMD_CG_SUPPORT_HDP_LS |
662 AMD_CG_SUPPORT_DRM_MGCG |
663 AMD_CG_SUPPORT_DRM_LS |
664 AMD_CG_SUPPORT_ROM_MGCG |
665 AMD_CG_SUPPORT_MC_MGCG |
666 AMD_CG_SUPPORT_MC_LS |
667 AMD_CG_SUPPORT_SDMA_MGCG |
668 AMD_CG_SUPPORT_SDMA_LS;
669 adev->pg_flags = AMD_PG_SUPPORT_SDMA;
670
671 adev->external_rev_id = 0x1;
672 break;
673 default:
674 /* FIXME: not supported yet */
675 return -EINVAL;
676 }
677
678 if (amdgpu_sriov_vf(adev)) {
679 amdgpu_virt_init_setting(adev);
680 xgpu_ai_mailbox_set_irq_funcs(adev);
681 }
682
683 adev->firmware.load_type = amdgpu_ucode_get_load_type(adev, amdgpu_fw_load_type);
684
685 amdgpu_get_pcie_info(adev);
686
687 return 0;
688 }
689
soc15_common_late_init(void * handle)690 static int soc15_common_late_init(void *handle)
691 {
692 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
693
694 if (amdgpu_sriov_vf(adev))
695 xgpu_ai_mailbox_get_irq(adev);
696
697 return 0;
698 }
699
soc15_common_sw_init(void * handle)700 static int soc15_common_sw_init(void *handle)
701 {
702 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
703
704 if (amdgpu_sriov_vf(adev))
705 xgpu_ai_mailbox_add_irq_id(adev);
706
707 return 0;
708 }
709
soc15_common_sw_fini(void * handle)710 static int soc15_common_sw_fini(void *handle)
711 {
712 return 0;
713 }
714
soc15_common_hw_init(void * handle)715 static int soc15_common_hw_init(void *handle)
716 {
717 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
718
719 /* move the golden regs per IP block */
720 soc15_init_golden_registers(adev);
721 /* enable pcie gen2/3 link */
722 soc15_pcie_gen3_enable(adev);
723 /* enable aspm */
724 soc15_program_aspm(adev);
725 /* setup nbio registers */
726 if (!(adev->flags & AMD_IS_APU))
727 nbio_v6_1_init_registers(adev);
728 /* enable the doorbell aperture */
729 soc15_enable_doorbell_aperture(adev, true);
730
731 return 0;
732 }
733
soc15_common_hw_fini(void * handle)734 static int soc15_common_hw_fini(void *handle)
735 {
736 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
737
738 /* disable the doorbell aperture */
739 soc15_enable_doorbell_aperture(adev, false);
740 if (amdgpu_sriov_vf(adev))
741 xgpu_ai_mailbox_put_irq(adev);
742
743 return 0;
744 }
745
soc15_common_suspend(void * handle)746 static int soc15_common_suspend(void *handle)
747 {
748 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
749
750 return soc15_common_hw_fini(adev);
751 }
752
soc15_common_resume(void * handle)753 static int soc15_common_resume(void *handle)
754 {
755 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
756
757 return soc15_common_hw_init(adev);
758 }
759
soc15_common_is_idle(void * handle)760 static bool soc15_common_is_idle(void *handle)
761 {
762 return true;
763 }
764
soc15_common_wait_for_idle(void * handle)765 static int soc15_common_wait_for_idle(void *handle)
766 {
767 return 0;
768 }
769
soc15_common_soft_reset(void * handle)770 static int soc15_common_soft_reset(void *handle)
771 {
772 return 0;
773 }
774
soc15_update_hdp_light_sleep(struct amdgpu_device * adev,bool enable)775 static void soc15_update_hdp_light_sleep(struct amdgpu_device *adev, bool enable)
776 {
777 uint32_t def, data;
778
779 def = data = RREG32(SOC15_REG_OFFSET(HDP, 0, mmHDP_MEM_POWER_LS));
780
781 if (enable && (adev->cg_flags & AMD_CG_SUPPORT_HDP_LS))
782 data |= HDP_MEM_POWER_LS__LS_ENABLE_MASK;
783 else
784 data &= ~HDP_MEM_POWER_LS__LS_ENABLE_MASK;
785
786 if (def != data)
787 WREG32(SOC15_REG_OFFSET(HDP, 0, mmHDP_MEM_POWER_LS), data);
788 }
789
soc15_update_drm_clock_gating(struct amdgpu_device * adev,bool enable)790 static void soc15_update_drm_clock_gating(struct amdgpu_device *adev, bool enable)
791 {
792 uint32_t def, data;
793
794 def = data = RREG32(SOC15_REG_OFFSET(MP0, 0, mmMP0_MISC_CGTT_CTRL0));
795
796 if (enable && (adev->cg_flags & AMD_CG_SUPPORT_DRM_MGCG))
797 data &= ~(0x01000000 |
798 0x02000000 |
799 0x04000000 |
800 0x08000000 |
801 0x10000000 |
802 0x20000000 |
803 0x40000000 |
804 0x80000000);
805 else
806 data |= (0x01000000 |
807 0x02000000 |
808 0x04000000 |
809 0x08000000 |
810 0x10000000 |
811 0x20000000 |
812 0x40000000 |
813 0x80000000);
814
815 if (def != data)
816 WREG32(SOC15_REG_OFFSET(MP0, 0, mmMP0_MISC_CGTT_CTRL0), data);
817 }
818
soc15_update_drm_light_sleep(struct amdgpu_device * adev,bool enable)819 static void soc15_update_drm_light_sleep(struct amdgpu_device *adev, bool enable)
820 {
821 uint32_t def, data;
822
823 def = data = RREG32(SOC15_REG_OFFSET(MP0, 0, mmMP0_MISC_LIGHT_SLEEP_CTRL));
824
825 if (enable && (adev->cg_flags & AMD_CG_SUPPORT_DRM_LS))
826 data |= 1;
827 else
828 data &= ~1;
829
830 if (def != data)
831 WREG32(SOC15_REG_OFFSET(MP0, 0, mmMP0_MISC_LIGHT_SLEEP_CTRL), data);
832 }
833
soc15_update_rom_medium_grain_clock_gating(struct amdgpu_device * adev,bool enable)834 static void soc15_update_rom_medium_grain_clock_gating(struct amdgpu_device *adev,
835 bool enable)
836 {
837 uint32_t def, data;
838
839 def = data = RREG32(SOC15_REG_OFFSET(SMUIO, 0, mmCGTT_ROM_CLK_CTRL0));
840
841 if (enable && (adev->cg_flags & AMD_CG_SUPPORT_ROM_MGCG))
842 data &= ~(CGTT_ROM_CLK_CTRL0__SOFT_OVERRIDE0_MASK |
843 CGTT_ROM_CLK_CTRL0__SOFT_OVERRIDE1_MASK);
844 else
845 data |= CGTT_ROM_CLK_CTRL0__SOFT_OVERRIDE0_MASK |
846 CGTT_ROM_CLK_CTRL0__SOFT_OVERRIDE1_MASK;
847
848 if (def != data)
849 WREG32(SOC15_REG_OFFSET(SMUIO, 0, mmCGTT_ROM_CLK_CTRL0), data);
850 }
851
soc15_update_df_medium_grain_clock_gating(struct amdgpu_device * adev,bool enable)852 static void soc15_update_df_medium_grain_clock_gating(struct amdgpu_device *adev,
853 bool enable)
854 {
855 uint32_t data;
856
857 /* Put DF on broadcast mode */
858 data = RREG32(SOC15_REG_OFFSET(DF, 0, mmFabricConfigAccessControl));
859 data &= ~FabricConfigAccessControl__CfgRegInstAccEn_MASK;
860 WREG32(SOC15_REG_OFFSET(DF, 0, mmFabricConfigAccessControl), data);
861
862 if (enable && (adev->cg_flags & AMD_CG_SUPPORT_DF_MGCG)) {
863 data = RREG32(SOC15_REG_OFFSET(DF, 0, mmDF_PIE_AON0_DfGlobalClkGater));
864 data &= ~DF_PIE_AON0_DfGlobalClkGater__MGCGMode_MASK;
865 data |= DF_MGCG_ENABLE_15_CYCLE_DELAY;
866 WREG32(SOC15_REG_OFFSET(DF, 0, mmDF_PIE_AON0_DfGlobalClkGater), data);
867 } else {
868 data = RREG32(SOC15_REG_OFFSET(DF, 0, mmDF_PIE_AON0_DfGlobalClkGater));
869 data &= ~DF_PIE_AON0_DfGlobalClkGater__MGCGMode_MASK;
870 data |= DF_MGCG_DISABLE;
871 WREG32(SOC15_REG_OFFSET(DF, 0, mmDF_PIE_AON0_DfGlobalClkGater), data);
872 }
873
874 WREG32(SOC15_REG_OFFSET(DF, 0, mmFabricConfigAccessControl),
875 mmFabricConfigAccessControl_DEFAULT);
876 }
877
soc15_common_set_clockgating_state(void * handle,enum amd_clockgating_state state)878 static int soc15_common_set_clockgating_state(void *handle,
879 enum amd_clockgating_state state)
880 {
881 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
882
883 if (amdgpu_sriov_vf(adev))
884 return 0;
885
886 switch (adev->asic_type) {
887 case CHIP_VEGA10:
888 nbio_v6_1_update_medium_grain_clock_gating(adev,
889 state == AMD_CG_STATE_GATE ? true : false);
890 nbio_v6_1_update_medium_grain_light_sleep(adev,
891 state == AMD_CG_STATE_GATE ? true : false);
892 soc15_update_hdp_light_sleep(adev,
893 state == AMD_CG_STATE_GATE ? true : false);
894 soc15_update_drm_clock_gating(adev,
895 state == AMD_CG_STATE_GATE ? true : false);
896 soc15_update_drm_light_sleep(adev,
897 state == AMD_CG_STATE_GATE ? true : false);
898 soc15_update_rom_medium_grain_clock_gating(adev,
899 state == AMD_CG_STATE_GATE ? true : false);
900 soc15_update_df_medium_grain_clock_gating(adev,
901 state == AMD_CG_STATE_GATE ? true : false);
902 break;
903 case CHIP_RAVEN:
904 nbio_v7_0_update_medium_grain_clock_gating(adev,
905 state == AMD_CG_STATE_GATE ? true : false);
906 nbio_v6_1_update_medium_grain_light_sleep(adev,
907 state == AMD_CG_STATE_GATE ? true : false);
908 soc15_update_hdp_light_sleep(adev,
909 state == AMD_CG_STATE_GATE ? true : false);
910 soc15_update_drm_clock_gating(adev,
911 state == AMD_CG_STATE_GATE ? true : false);
912 soc15_update_drm_light_sleep(adev,
913 state == AMD_CG_STATE_GATE ? true : false);
914 soc15_update_rom_medium_grain_clock_gating(adev,
915 state == AMD_CG_STATE_GATE ? true : false);
916 break;
917 default:
918 break;
919 }
920 return 0;
921 }
922
soc15_common_get_clockgating_state(void * handle,u32 * flags)923 static void soc15_common_get_clockgating_state(void *handle, u32 *flags)
924 {
925 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
926 int data;
927
928 if (amdgpu_sriov_vf(adev))
929 *flags = 0;
930
931 nbio_v6_1_get_clockgating_state(adev, flags);
932
933 /* AMD_CG_SUPPORT_HDP_LS */
934 data = RREG32(SOC15_REG_OFFSET(HDP, 0, mmHDP_MEM_POWER_LS));
935 if (data & HDP_MEM_POWER_LS__LS_ENABLE_MASK)
936 *flags |= AMD_CG_SUPPORT_HDP_LS;
937
938 /* AMD_CG_SUPPORT_DRM_MGCG */
939 data = RREG32(SOC15_REG_OFFSET(MP0, 0, mmMP0_MISC_CGTT_CTRL0));
940 if (!(data & 0x01000000))
941 *flags |= AMD_CG_SUPPORT_DRM_MGCG;
942
943 /* AMD_CG_SUPPORT_DRM_LS */
944 data = RREG32(SOC15_REG_OFFSET(MP0, 0, mmMP0_MISC_LIGHT_SLEEP_CTRL));
945 if (data & 0x1)
946 *flags |= AMD_CG_SUPPORT_DRM_LS;
947
948 /* AMD_CG_SUPPORT_ROM_MGCG */
949 data = RREG32(SOC15_REG_OFFSET(SMUIO, 0, mmCGTT_ROM_CLK_CTRL0));
950 if (!(data & CGTT_ROM_CLK_CTRL0__SOFT_OVERRIDE0_MASK))
951 *flags |= AMD_CG_SUPPORT_ROM_MGCG;
952
953 /* AMD_CG_SUPPORT_DF_MGCG */
954 data = RREG32(SOC15_REG_OFFSET(DF, 0, mmDF_PIE_AON0_DfGlobalClkGater));
955 if (data & DF_MGCG_ENABLE_15_CYCLE_DELAY)
956 *flags |= AMD_CG_SUPPORT_DF_MGCG;
957 }
958
soc15_common_set_powergating_state(void * handle,enum amd_powergating_state state)959 static int soc15_common_set_powergating_state(void *handle,
960 enum amd_powergating_state state)
961 {
962 /* todo */
963 return 0;
964 }
965
966 const struct amd_ip_funcs soc15_common_ip_funcs = {
967 .name = "soc15_common",
968 .early_init = soc15_common_early_init,
969 .late_init = soc15_common_late_init,
970 .sw_init = soc15_common_sw_init,
971 .sw_fini = soc15_common_sw_fini,
972 .hw_init = soc15_common_hw_init,
973 .hw_fini = soc15_common_hw_fini,
974 .suspend = soc15_common_suspend,
975 .resume = soc15_common_resume,
976 .is_idle = soc15_common_is_idle,
977 .wait_for_idle = soc15_common_wait_for_idle,
978 .soft_reset = soc15_common_soft_reset,
979 .set_clockgating_state = soc15_common_set_clockgating_state,
980 .set_powergating_state = soc15_common_set_powergating_state,
981 .get_clockgating_state= soc15_common_get_clockgating_state,
982 };
983