1 /* 2 * Copyright (C) 2017 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included 12 * in all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS 15 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN 18 * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN 19 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. 20 */ 21 #ifndef _soc15ip_new_HEADER 22 #define _soc15ip_new_HEADER 23 24 // HW ID 25 #define MP1_HWID 1 26 #define MP2_HWID 2 27 #define THM_HWID 3 28 #define SMUIO_HWID 4 29 #define FUSE_HWID 5 30 #define CLKA_HWID 6 31 #define PWR_HWID 10 32 #define GC_HWID 11 33 #define UVD_HWID 12 34 #define VCN_HWID UVD_HWID 35 #define AUDIO_AZ_HWID 13 36 #define ACP_HWID 14 37 #define DCI_HWID 15 38 #define DMU_HWID 271 39 #define DCO_HWID 16 40 #define DIO_HWID 272 41 #define XDMA_HWID 17 42 #define DCEAZ_HWID 18 43 #define DAZ_HWID 274 44 #define SDPMUX_HWID 19 45 #define NTB_HWID 20 46 #define IOHC_HWID 24 47 #define L2IMU_HWID 28 48 #define VCE_HWID 32 49 #define MMHUB_HWID 34 50 #define ATHUB_HWID 35 51 #define DBGU_NBIO_HWID 36 52 #define DFX_HWID 37 53 #define DBGU0_HWID 38 54 #define DBGU1_HWID 39 55 #define OSSSYS_HWID 40 56 #define HDP_HWID 41 57 #define SDMA0_HWID 42 58 #define SDMA1_HWID 43 59 #define ISP_HWID 44 60 #define DBGU_IO_HWID 45 61 #define DF_HWID 46 62 #define CLKB_HWID 47 63 #define FCH_HWID 48 64 #define DFX_DAP_HWID 49 65 #define L1IMU_PCIE_HWID 50 66 #define L1IMU_NBIF_HWID 51 67 #define L1IMU_IOAGR_HWID 52 68 #define L1IMU3_HWID 53 69 #define L1IMU4_HWID 54 70 #define L1IMU5_HWID 55 71 #define L1IMU6_HWID 56 72 #define L1IMU7_HWID 57 73 #define L1IMU8_HWID 58 74 #define L1IMU9_HWID 59 75 #define L1IMU10_HWID 60 76 #define L1IMU11_HWID 61 77 #define L1IMU12_HWID 62 78 #define L1IMU13_HWID 63 79 #define L1IMU14_HWID 64 80 #define L1IMU15_HWID 65 81 #define WAFLC_HWID 66 82 #define FCH_USB_PD_HWID 67 83 #define PCIE_HWID 70 84 #define PCS_HWID 80 85 #define DDCL_HWID 89 86 #define SST_HWID 90 87 #define IOAGR_HWID 100 88 #define NBIF_HWID 108 89 #define IOAPIC_HWID 124 90 #define SYSTEMHUB_HWID 128 91 #define NTBCCP_HWID 144 92 #define UMC_HWID 150 93 #define SATA_HWID 168 94 #define USB_HWID 170 95 #define CCXSEC_HWID 176 96 #define XGBE_HWID 216 97 #define MP0_HWID 254 98 99 #define MAX_INSTANCE 5 100 #define MAX_SEGMENT 5 101 102 103 struct IP_BASE_INSTANCE 104 { 105 unsigned int segment[MAX_SEGMENT]; 106 }; 107 108 struct IP_BASE 109 { 110 struct IP_BASE_INSTANCE instance[MAX_INSTANCE]; 111 }; 112 113 114 static const struct IP_BASE NBIF_BASE = { { { { 0x00000000, 0x00000014, 0x00000D20, 0x00010400, 0 } }, 115 { { 0, 0, 0, 0, 0 } }, 116 { { 0, 0, 0, 0, 0 } }, 117 { { 0, 0, 0, 0, 0 } }, 118 { { 0, 0, 0, 0, 0 } } } }; 119 static const struct IP_BASE NBIO_BASE = { { { { 0x00000000, 0x00000014, 0x00000D20, 0x00010400, 0 } }, 120 { { 0, 0, 0, 0, 0 } }, 121 { { 0, 0, 0, 0, 0 } }, 122 { { 0, 0, 0, 0, 0 } }, 123 { { 0, 0, 0, 0, 0 } } } }; 124 static const struct IP_BASE DCE_BASE = { { { { 0x00000012, 0x000000C0, 0x000034C0, 0, 0 } }, 125 { { 0, 0, 0, 0, 0 } }, 126 { { 0, 0, 0, 0, 0 } }, 127 { { 0, 0, 0, 0, 0 } }, 128 { { 0, 0, 0, 0, 0 } } } }; 129 static const struct IP_BASE DCN_BASE = { { { { 0x00000012, 0x000000C0, 0x000034C0, 0, 0 } }, 130 { { 0, 0, 0, 0, 0 } }, 131 { { 0, 0, 0, 0, 0 } }, 132 { { 0, 0, 0, 0, 0 } }, 133 { { 0, 0, 0, 0, 0 } } } }; 134 static const struct IP_BASE MP0_BASE = { { { { 0x00016000, 0, 0, 0, 0 } }, 135 { { 0, 0, 0, 0, 0 } }, 136 { { 0, 0, 0, 0, 0 } }, 137 { { 0, 0, 0, 0, 0 } }, 138 { { 0, 0, 0, 0, 0 } } } }; 139 static const struct IP_BASE MP1_BASE = { { { { 0x00016000, 0, 0, 0, 0 } }, 140 { { 0, 0, 0, 0, 0 } }, 141 { { 0, 0, 0, 0, 0 } }, 142 { { 0, 0, 0, 0, 0 } }, 143 { { 0, 0, 0, 0, 0 } } } }; 144 static const struct IP_BASE MP2_BASE = { { { { 0x00016000, 0, 0, 0, 0 } }, 145 { { 0, 0, 0, 0, 0 } }, 146 { { 0, 0, 0, 0, 0 } }, 147 { { 0, 0, 0, 0, 0 } }, 148 { { 0, 0, 0, 0, 0 } } } }; 149 static const struct IP_BASE DF_BASE = { { { { 0x00007000, 0, 0, 0, 0 } }, 150 { { 0, 0, 0, 0, 0 } }, 151 { { 0, 0, 0, 0, 0 } }, 152 { { 0, 0, 0, 0, 0 } }, 153 { { 0, 0, 0, 0, 0 } } } }; 154 static const struct IP_BASE UVD_BASE = { { { { 0x00007800, 0x00007E00, 0, 0, 0 } }, 155 { { 0, 0, 0, 0, 0 } }, 156 { { 0, 0, 0, 0, 0 } }, 157 { { 0, 0, 0, 0, 0 } }, 158 { { 0, 0, 0, 0, 0 } } } }; //note: GLN does not use the first segment 159 static const struct IP_BASE VCN_BASE = { { { { 0x00007800, 0x00007E00, 0, 0, 0 } }, 160 { { 0, 0, 0, 0, 0 } }, 161 { { 0, 0, 0, 0, 0 } }, 162 { { 0, 0, 0, 0, 0 } }, 163 { { 0, 0, 0, 0, 0 } } } }; //note: GLN does not use the first segment 164 static const struct IP_BASE DBGU_BASE = { { { { 0x00000180, 0x000001A0, 0, 0, 0 } }, 165 { { 0, 0, 0, 0, 0 } }, 166 { { 0, 0, 0, 0, 0 } }, 167 { { 0, 0, 0, 0, 0 } }, 168 { { 0, 0, 0, 0, 0 } } } }; // not exist 169 static const struct IP_BASE DBGU_NBIO_BASE = { { { { 0x000001C0, 0, 0, 0, 0 } }, 170 { { 0, 0, 0, 0, 0 } }, 171 { { 0, 0, 0, 0, 0 } }, 172 { { 0, 0, 0, 0, 0 } }, 173 { { 0, 0, 0, 0, 0 } } } }; // not exist 174 static const struct IP_BASE DBGU_IO_BASE = { { { { 0x000001E0, 0, 0, 0, 0 } }, 175 { { 0, 0, 0, 0, 0 } }, 176 { { 0, 0, 0, 0, 0 } }, 177 { { 0, 0, 0, 0, 0 } }, 178 { { 0, 0, 0, 0, 0 } } } }; // not exist 179 static const struct IP_BASE DFX_DAP_BASE = { { { { 0x000005A0, 0, 0, 0, 0 } }, 180 { { 0, 0, 0, 0, 0 } }, 181 { { 0, 0, 0, 0, 0 } }, 182 { { 0, 0, 0, 0, 0 } }, 183 { { 0, 0, 0, 0, 0 } } } }; // not exist 184 static const struct IP_BASE DFX_BASE = { { { { 0x00000580, 0, 0, 0, 0 } }, 185 { { 0, 0, 0, 0, 0 } }, 186 { { 0, 0, 0, 0, 0 } }, 187 { { 0, 0, 0, 0, 0 } }, 188 { { 0, 0, 0, 0, 0 } } } }; // this file does not contain registers 189 static const struct IP_BASE ISP_BASE = { { { { 0x00018000, 0, 0, 0, 0 } }, 190 { { 0, 0, 0, 0, 0 } }, 191 { { 0, 0, 0, 0, 0 } }, 192 { { 0, 0, 0, 0, 0 } }, 193 { { 0, 0, 0, 0, 0 } } } }; // not exist 194 static const struct IP_BASE SYSTEMHUB_BASE = { { { { 0x00000EA0, 0, 0, 0, 0 } }, 195 { { 0, 0, 0, 0, 0 } }, 196 { { 0, 0, 0, 0, 0 } }, 197 { { 0, 0, 0, 0, 0 } }, 198 { { 0, 0, 0, 0, 0 } } } }; // not exist 199 static const struct IP_BASE L2IMU_BASE = { { { { 0x00007DC0, 0, 0, 0, 0 } }, 200 { { 0, 0, 0, 0, 0 } }, 201 { { 0, 0, 0, 0, 0 } }, 202 { { 0, 0, 0, 0, 0 } }, 203 { { 0, 0, 0, 0, 0 } } } }; 204 static const struct IP_BASE IOHC_BASE = { { { { 0x00010000, 0, 0, 0, 0 } }, 205 { { 0, 0, 0, 0, 0 } }, 206 { { 0, 0, 0, 0, 0 } }, 207 { { 0, 0, 0, 0, 0 } }, 208 { { 0, 0, 0, 0, 0 } } } }; 209 static const struct IP_BASE ATHUB_BASE = { { { { 0x00000C20, 0, 0, 0, 0 } }, 210 { { 0, 0, 0, 0, 0 } }, 211 { { 0, 0, 0, 0, 0 } }, 212 { { 0, 0, 0, 0, 0 } }, 213 { { 0, 0, 0, 0, 0 } } } }; 214 static const struct IP_BASE VCE_BASE = { { { { 0x00007E00, 0x00048800, 0, 0, 0 } }, 215 { { 0, 0, 0, 0, 0 } }, 216 { { 0, 0, 0, 0, 0 } }, 217 { { 0, 0, 0, 0, 0 } }, 218 { { 0, 0, 0, 0, 0 } } } }; 219 static const struct IP_BASE GC_BASE = { { { { 0x00002000, 0x0000A000, 0, 0, 0 } }, 220 { { 0, 0, 0, 0, 0 } }, 221 { { 0, 0, 0, 0, 0 } }, 222 { { 0, 0, 0, 0, 0 } }, 223 { { 0, 0, 0, 0, 0 } } } }; 224 static const struct IP_BASE MMHUB_BASE = { { { { 0x0001A000, 0, 0, 0, 0 } }, 225 { { 0, 0, 0, 0, 0 } }, 226 { { 0, 0, 0, 0, 0 } }, 227 { { 0, 0, 0, 0, 0 } }, 228 { { 0, 0, 0, 0, 0 } } } }; 229 static const struct IP_BASE RSMU_BASE = { { { { 0x00012000, 0, 0, 0, 0 } }, 230 { { 0, 0, 0, 0, 0 } }, 231 { { 0, 0, 0, 0, 0 } }, 232 { { 0, 0, 0, 0, 0 } }, 233 { { 0, 0, 0, 0, 0 } } } }; 234 static const struct IP_BASE HDP_BASE = { { { { 0x00000F20, 0, 0, 0, 0 } }, 235 { { 0, 0, 0, 0, 0 } }, 236 { { 0, 0, 0, 0, 0 } }, 237 { { 0, 0, 0, 0, 0 } }, 238 { { 0, 0, 0, 0, 0 } } } }; 239 static const struct IP_BASE OSSSYS_BASE = { { { { 0x000010A0, 0, 0, 0, 0 } }, 240 { { 0, 0, 0, 0, 0 } }, 241 { { 0, 0, 0, 0, 0 } }, 242 { { 0, 0, 0, 0, 0 } }, 243 { { 0, 0, 0, 0, 0 } } } }; 244 static const struct IP_BASE SDMA0_BASE = { { { { 0x00001260, 0, 0, 0, 0 } }, 245 { { 0, 0, 0, 0, 0 } }, 246 { { 0, 0, 0, 0, 0 } }, 247 { { 0, 0, 0, 0, 0 } }, 248 { { 0, 0, 0, 0, 0 } } } }; 249 static const struct IP_BASE SDMA1_BASE = { { { { 0x00001460, 0, 0, 0, 0 } }, 250 { { 0, 0, 0, 0, 0 } }, 251 { { 0, 0, 0, 0, 0 } }, 252 { { 0, 0, 0, 0, 0 } }, 253 { { 0, 0, 0, 0, 0 } } } }; 254 static const struct IP_BASE XDMA_BASE = { { { { 0x00003400, 0, 0, 0, 0 } }, 255 { { 0, 0, 0, 0, 0 } }, 256 { { 0, 0, 0, 0, 0 } }, 257 { { 0, 0, 0, 0, 0 } }, 258 { { 0, 0, 0, 0, 0 } } } }; 259 static const struct IP_BASE UMC_BASE = { { { { 0x00014000, 0, 0, 0, 0 } }, 260 { { 0, 0, 0, 0, 0 } }, 261 { { 0, 0, 0, 0, 0 } }, 262 { { 0, 0, 0, 0, 0 } }, 263 { { 0, 0, 0, 0, 0 } } } }; 264 static const struct IP_BASE THM_BASE = { { { { 0x00016600, 0, 0, 0, 0 } }, 265 { { 0, 0, 0, 0, 0 } }, 266 { { 0, 0, 0, 0, 0 } }, 267 { { 0, 0, 0, 0, 0 } }, 268 { { 0, 0, 0, 0, 0 } } } }; 269 static const struct IP_BASE SMUIO_BASE = { { { { 0x00016800, 0, 0, 0, 0 } }, 270 { { 0, 0, 0, 0, 0 } }, 271 { { 0, 0, 0, 0, 0 } }, 272 { { 0, 0, 0, 0, 0 } }, 273 { { 0, 0, 0, 0, 0 } } } }; 274 static const struct IP_BASE PWR_BASE = { { { { 0x00016A00, 0, 0, 0, 0 } }, 275 { { 0, 0, 0, 0, 0 } }, 276 { { 0, 0, 0, 0, 0 } }, 277 { { 0, 0, 0, 0, 0 } }, 278 { { 0, 0, 0, 0, 0 } } } }; 279 static const struct IP_BASE CLK_BASE = { { { { 0x00016C00, 0, 0, 0, 0 } }, 280 { { 0x00016E00, 0, 0, 0, 0 } }, 281 { { 0x00017000, 0, 0, 0, 0 } }, 282 { { 0x00017200, 0, 0, 0, 0 } }, 283 { { 0x00017E00, 0, 0, 0, 0 } } } }; 284 static const struct IP_BASE FUSE_BASE = { { { { 0x00017400, 0, 0, 0, 0 } }, 285 { { 0, 0, 0, 0, 0 } }, 286 { { 0, 0, 0, 0, 0 } }, 287 { { 0, 0, 0, 0, 0 } }, 288 { { 0, 0, 0, 0, 0 } } } }; 289 290 291 #define NBIF_BASE__INST0_SEG0 0x00000000 292 #define NBIF_BASE__INST0_SEG1 0x00000014 293 #define NBIF_BASE__INST0_SEG2 0x00000D20 294 #define NBIF_BASE__INST0_SEG3 0x00010400 295 #define NBIF_BASE__INST0_SEG4 0 296 297 #define NBIF_BASE__INST1_SEG0 0 298 #define NBIF_BASE__INST1_SEG1 0 299 #define NBIF_BASE__INST1_SEG2 0 300 #define NBIF_BASE__INST1_SEG3 0 301 #define NBIF_BASE__INST1_SEG4 0 302 303 #define NBIF_BASE__INST2_SEG0 0 304 #define NBIF_BASE__INST2_SEG1 0 305 #define NBIF_BASE__INST2_SEG2 0 306 #define NBIF_BASE__INST2_SEG3 0 307 #define NBIF_BASE__INST2_SEG4 0 308 309 #define NBIF_BASE__INST3_SEG0 0 310 #define NBIF_BASE__INST3_SEG1 0 311 #define NBIF_BASE__INST3_SEG2 0 312 #define NBIF_BASE__INST3_SEG3 0 313 #define NBIF_BASE__INST3_SEG4 0 314 315 #define NBIF_BASE__INST4_SEG0 0 316 #define NBIF_BASE__INST4_SEG1 0 317 #define NBIF_BASE__INST4_SEG2 0 318 #define NBIF_BASE__INST4_SEG3 0 319 #define NBIF_BASE__INST4_SEG4 0 320 321 #define NBIO_BASE__INST0_SEG0 0x00000000 322 #define NBIO_BASE__INST0_SEG1 0x00000014 323 #define NBIO_BASE__INST0_SEG2 0x00000D20 324 #define NBIO_BASE__INST0_SEG3 0x00010400 325 #define NBIO_BASE__INST0_SEG4 0 326 327 #define NBIO_BASE__INST1_SEG0 0 328 #define NBIO_BASE__INST1_SEG1 0 329 #define NBIO_BASE__INST1_SEG2 0 330 #define NBIO_BASE__INST1_SEG3 0 331 #define NBIO_BASE__INST1_SEG4 0 332 333 #define NBIO_BASE__INST2_SEG0 0 334 #define NBIO_BASE__INST2_SEG1 0 335 #define NBIO_BASE__INST2_SEG2 0 336 #define NBIO_BASE__INST2_SEG3 0 337 #define NBIO_BASE__INST2_SEG4 0 338 339 #define NBIO_BASE__INST3_SEG0 0 340 #define NBIO_BASE__INST3_SEG1 0 341 #define NBIO_BASE__INST3_SEG2 0 342 #define NBIO_BASE__INST3_SEG3 0 343 #define NBIO_BASE__INST3_SEG4 0 344 345 #define NBIO_BASE__INST4_SEG0 0 346 #define NBIO_BASE__INST4_SEG1 0 347 #define NBIO_BASE__INST4_SEG2 0 348 #define NBIO_BASE__INST4_SEG3 0 349 #define NBIO_BASE__INST4_SEG4 0 350 351 #define DCE_BASE__INST0_SEG0 0x00000012 352 #define DCE_BASE__INST0_SEG1 0x000000C0 353 #define DCE_BASE__INST0_SEG2 0x000034C0 354 #define DCE_BASE__INST0_SEG3 0 355 #define DCE_BASE__INST0_SEG4 0 356 357 #define DCE_BASE__INST1_SEG0 0 358 #define DCE_BASE__INST1_SEG1 0 359 #define DCE_BASE__INST1_SEG2 0 360 #define DCE_BASE__INST1_SEG3 0 361 #define DCE_BASE__INST1_SEG4 0 362 363 #define DCE_BASE__INST2_SEG0 0 364 #define DCE_BASE__INST2_SEG1 0 365 #define DCE_BASE__INST2_SEG2 0 366 #define DCE_BASE__INST2_SEG3 0 367 #define DCE_BASE__INST2_SEG4 0 368 369 #define DCE_BASE__INST3_SEG0 0 370 #define DCE_BASE__INST3_SEG1 0 371 #define DCE_BASE__INST3_SEG2 0 372 #define DCE_BASE__INST3_SEG3 0 373 #define DCE_BASE__INST3_SEG4 0 374 375 #define DCE_BASE__INST4_SEG0 0 376 #define DCE_BASE__INST4_SEG1 0 377 #define DCE_BASE__INST4_SEG2 0 378 #define DCE_BASE__INST4_SEG3 0 379 #define DCE_BASE__INST4_SEG4 0 380 381 #define DCN_BASE__INST0_SEG0 0x00000012 382 #define DCN_BASE__INST0_SEG1 0x000000C0 383 #define DCN_BASE__INST0_SEG2 0x000034C0 384 #define DCN_BASE__INST0_SEG3 0 385 #define DCN_BASE__INST0_SEG4 0 386 387 #define DCN_BASE__INST1_SEG0 0 388 #define DCN_BASE__INST1_SEG1 0 389 #define DCN_BASE__INST1_SEG2 0 390 #define DCN_BASE__INST1_SEG3 0 391 #define DCN_BASE__INST1_SEG4 0 392 393 #define DCN_BASE__INST2_SEG0 0 394 #define DCN_BASE__INST2_SEG1 0 395 #define DCN_BASE__INST2_SEG2 0 396 #define DCN_BASE__INST2_SEG3 0 397 #define DCN_BASE__INST2_SEG4 0 398 399 #define DCN_BASE__INST3_SEG0 0 400 #define DCN_BASE__INST3_SEG1 0 401 #define DCN_BASE__INST3_SEG2 0 402 #define DCN_BASE__INST3_SEG3 0 403 #define DCN_BASE__INST3_SEG4 0 404 405 #define DCN_BASE__INST4_SEG0 0 406 #define DCN_BASE__INST4_SEG1 0 407 #define DCN_BASE__INST4_SEG2 0 408 #define DCN_BASE__INST4_SEG3 0 409 #define DCN_BASE__INST4_SEG4 0 410 411 #define MP0_BASE__INST0_SEG0 0x00016000 412 #define MP0_BASE__INST0_SEG1 0 413 #define MP0_BASE__INST0_SEG2 0 414 #define MP0_BASE__INST0_SEG3 0 415 #define MP0_BASE__INST0_SEG4 0 416 417 #define MP0_BASE__INST1_SEG0 0 418 #define MP0_BASE__INST1_SEG1 0 419 #define MP0_BASE__INST1_SEG2 0 420 #define MP0_BASE__INST1_SEG3 0 421 #define MP0_BASE__INST1_SEG4 0 422 423 #define MP0_BASE__INST2_SEG0 0 424 #define MP0_BASE__INST2_SEG1 0 425 #define MP0_BASE__INST2_SEG2 0 426 #define MP0_BASE__INST2_SEG3 0 427 #define MP0_BASE__INST2_SEG4 0 428 429 #define MP0_BASE__INST3_SEG0 0 430 #define MP0_BASE__INST3_SEG1 0 431 #define MP0_BASE__INST3_SEG2 0 432 #define MP0_BASE__INST3_SEG3 0 433 #define MP0_BASE__INST3_SEG4 0 434 435 #define MP0_BASE__INST4_SEG0 0 436 #define MP0_BASE__INST4_SEG1 0 437 #define MP0_BASE__INST4_SEG2 0 438 #define MP0_BASE__INST4_SEG3 0 439 #define MP0_BASE__INST4_SEG4 0 440 441 #define MP1_BASE__INST0_SEG0 0x00016200 442 #define MP1_BASE__INST0_SEG1 0 443 #define MP1_BASE__INST0_SEG2 0 444 #define MP1_BASE__INST0_SEG3 0 445 #define MP1_BASE__INST0_SEG4 0 446 447 #define MP1_BASE__INST1_SEG0 0 448 #define MP1_BASE__INST1_SEG1 0 449 #define MP1_BASE__INST1_SEG2 0 450 #define MP1_BASE__INST1_SEG3 0 451 #define MP1_BASE__INST1_SEG4 0 452 453 #define MP1_BASE__INST2_SEG0 0 454 #define MP1_BASE__INST2_SEG1 0 455 #define MP1_BASE__INST2_SEG2 0 456 #define MP1_BASE__INST2_SEG3 0 457 #define MP1_BASE__INST2_SEG4 0 458 459 #define MP1_BASE__INST3_SEG0 0 460 #define MP1_BASE__INST3_SEG1 0 461 #define MP1_BASE__INST3_SEG2 0 462 #define MP1_BASE__INST3_SEG3 0 463 #define MP1_BASE__INST3_SEG4 0 464 465 #define MP1_BASE__INST4_SEG0 0 466 #define MP1_BASE__INST4_SEG1 0 467 #define MP1_BASE__INST4_SEG2 0 468 #define MP1_BASE__INST4_SEG3 0 469 #define MP1_BASE__INST4_SEG4 0 470 471 #define MP2_BASE__INST0_SEG0 0x00016400 472 #define MP2_BASE__INST0_SEG1 0 473 #define MP2_BASE__INST0_SEG2 0 474 #define MP2_BASE__INST0_SEG3 0 475 #define MP2_BASE__INST0_SEG4 0 476 477 #define MP2_BASE__INST1_SEG0 0 478 #define MP2_BASE__INST1_SEG1 0 479 #define MP2_BASE__INST1_SEG2 0 480 #define MP2_BASE__INST1_SEG3 0 481 #define MP2_BASE__INST1_SEG4 0 482 483 #define MP2_BASE__INST2_SEG0 0 484 #define MP2_BASE__INST2_SEG1 0 485 #define MP2_BASE__INST2_SEG2 0 486 #define MP2_BASE__INST2_SEG3 0 487 #define MP2_BASE__INST2_SEG4 0 488 489 #define MP2_BASE__INST3_SEG0 0 490 #define MP2_BASE__INST3_SEG1 0 491 #define MP2_BASE__INST3_SEG2 0 492 #define MP2_BASE__INST3_SEG3 0 493 #define MP2_BASE__INST3_SEG4 0 494 495 #define MP2_BASE__INST4_SEG0 0 496 #define MP2_BASE__INST4_SEG1 0 497 #define MP2_BASE__INST4_SEG2 0 498 #define MP2_BASE__INST4_SEG3 0 499 #define MP2_BASE__INST4_SEG4 0 500 501 #define DF_BASE__INST0_SEG0 0x00007000 502 #define DF_BASE__INST0_SEG1 0 503 #define DF_BASE__INST0_SEG2 0 504 #define DF_BASE__INST0_SEG3 0 505 #define DF_BASE__INST0_SEG4 0 506 507 #define DF_BASE__INST1_SEG0 0 508 #define DF_BASE__INST1_SEG1 0 509 #define DF_BASE__INST1_SEG2 0 510 #define DF_BASE__INST1_SEG3 0 511 #define DF_BASE__INST1_SEG4 0 512 513 #define DF_BASE__INST2_SEG0 0 514 #define DF_BASE__INST2_SEG1 0 515 #define DF_BASE__INST2_SEG2 0 516 #define DF_BASE__INST2_SEG3 0 517 #define DF_BASE__INST2_SEG4 0 518 519 #define DF_BASE__INST3_SEG0 0 520 #define DF_BASE__INST3_SEG1 0 521 #define DF_BASE__INST3_SEG2 0 522 #define DF_BASE__INST3_SEG3 0 523 #define DF_BASE__INST3_SEG4 0 524 525 #define DF_BASE__INST4_SEG0 0 526 #define DF_BASE__INST4_SEG1 0 527 #define DF_BASE__INST4_SEG2 0 528 #define DF_BASE__INST4_SEG3 0 529 #define DF_BASE__INST4_SEG4 0 530 531 #define UVD_BASE__INST0_SEG0 0x00007800 532 #define UVD_BASE__INST0_SEG1 0x00007E00 533 #define UVD_BASE__INST0_SEG2 0 534 #define UVD_BASE__INST0_SEG3 0 535 #define UVD_BASE__INST0_SEG4 0 536 537 #define UVD_BASE__INST1_SEG0 0 538 #define UVD_BASE__INST1_SEG1 0 539 #define UVD_BASE__INST1_SEG2 0 540 #define UVD_BASE__INST1_SEG3 0 541 #define UVD_BASE__INST1_SEG4 0 542 543 #define UVD_BASE__INST2_SEG0 0 544 #define UVD_BASE__INST2_SEG1 0 545 #define UVD_BASE__INST2_SEG2 0 546 #define UVD_BASE__INST2_SEG3 0 547 #define UVD_BASE__INST2_SEG4 0 548 549 #define UVD_BASE__INST3_SEG0 0 550 #define UVD_BASE__INST3_SEG1 0 551 #define UVD_BASE__INST3_SEG2 0 552 #define UVD_BASE__INST3_SEG3 0 553 #define UVD_BASE__INST3_SEG4 0 554 555 #define UVD_BASE__INST4_SEG0 0 556 #define UVD_BASE__INST4_SEG1 0 557 #define UVD_BASE__INST4_SEG2 0 558 #define UVD_BASE__INST4_SEG3 0 559 #define UVD_BASE__INST4_SEG4 0 560 561 #define VCN_BASE__INST0_SEG0 0x00007800 562 #define VCN_BASE__INST0_SEG1 0x00007E00 563 #define VCN_BASE__INST0_SEG2 0 564 #define VCN_BASE__INST0_SEG3 0 565 #define VCN_BASE__INST0_SEG4 0 566 567 #define VCN_BASE__INST1_SEG0 0 568 #define VCN_BASE__INST1_SEG1 0 569 #define VCN_BASE__INST1_SEG2 0 570 #define VCN_BASE__INST1_SEG3 0 571 #define VCN_BASE__INST1_SEG4 0 572 573 #define VCN_BASE__INST2_SEG0 0 574 #define VCN_BASE__INST2_SEG1 0 575 #define VCN_BASE__INST2_SEG2 0 576 #define VCN_BASE__INST2_SEG3 0 577 #define VCN_BASE__INST2_SEG4 0 578 579 #define VCN_BASE__INST3_SEG0 0 580 #define VCN_BASE__INST3_SEG1 0 581 #define VCN_BASE__INST3_SEG2 0 582 #define VCN_BASE__INST3_SEG3 0 583 #define VCN_BASE__INST3_SEG4 0 584 585 #define VCN_BASE__INST4_SEG0 0 586 #define VCN_BASE__INST4_SEG1 0 587 #define VCN_BASE__INST4_SEG2 0 588 #define VCN_BASE__INST4_SEG3 0 589 #define VCN_BASE__INST4_SEG4 0 590 591 #define DBGU_BASE__INST0_SEG0 0x00000180 592 #define DBGU_BASE__INST0_SEG1 0x000001A0 593 #define DBGU_BASE__INST0_SEG2 0 594 #define DBGU_BASE__INST0_SEG3 0 595 #define DBGU_BASE__INST0_SEG4 0 596 597 #define DBGU_BASE__INST1_SEG0 0 598 #define DBGU_BASE__INST1_SEG1 0 599 #define DBGU_BASE__INST1_SEG2 0 600 #define DBGU_BASE__INST1_SEG3 0 601 #define DBGU_BASE__INST1_SEG4 0 602 603 #define DBGU_BASE__INST2_SEG0 0 604 #define DBGU_BASE__INST2_SEG1 0 605 #define DBGU_BASE__INST2_SEG2 0 606 #define DBGU_BASE__INST2_SEG3 0 607 #define DBGU_BASE__INST2_SEG4 0 608 609 #define DBGU_BASE__INST3_SEG0 0 610 #define DBGU_BASE__INST3_SEG1 0 611 #define DBGU_BASE__INST3_SEG2 0 612 #define DBGU_BASE__INST3_SEG3 0 613 #define DBGU_BASE__INST3_SEG4 0 614 615 #define DBGU_BASE__INST4_SEG0 0 616 #define DBGU_BASE__INST4_SEG1 0 617 #define DBGU_BASE__INST4_SEG2 0 618 #define DBGU_BASE__INST4_SEG3 0 619 #define DBGU_BASE__INST4_SEG4 0 620 621 #define DBGU_NBIO_BASE__INST0_SEG0 0x000001C0 622 #define DBGU_NBIO_BASE__INST0_SEG1 0 623 #define DBGU_NBIO_BASE__INST0_SEG2 0 624 #define DBGU_NBIO_BASE__INST0_SEG3 0 625 #define DBGU_NBIO_BASE__INST0_SEG4 0 626 627 #define DBGU_NBIO_BASE__INST1_SEG0 0 628 #define DBGU_NBIO_BASE__INST1_SEG1 0 629 #define DBGU_NBIO_BASE__INST1_SEG2 0 630 #define DBGU_NBIO_BASE__INST1_SEG3 0 631 #define DBGU_NBIO_BASE__INST1_SEG4 0 632 633 #define DBGU_NBIO_BASE__INST2_SEG0 0 634 #define DBGU_NBIO_BASE__INST2_SEG1 0 635 #define DBGU_NBIO_BASE__INST2_SEG2 0 636 #define DBGU_NBIO_BASE__INST2_SEG3 0 637 #define DBGU_NBIO_BASE__INST2_SEG4 0 638 639 #define DBGU_NBIO_BASE__INST3_SEG0 0 640 #define DBGU_NBIO_BASE__INST3_SEG1 0 641 #define DBGU_NBIO_BASE__INST3_SEG2 0 642 #define DBGU_NBIO_BASE__INST3_SEG3 0 643 #define DBGU_NBIO_BASE__INST3_SEG4 0 644 645 #define DBGU_NBIO_BASE__INST4_SEG0 0 646 #define DBGU_NBIO_BASE__INST4_SEG1 0 647 #define DBGU_NBIO_BASE__INST4_SEG2 0 648 #define DBGU_NBIO_BASE__INST4_SEG3 0 649 #define DBGU_NBIO_BASE__INST4_SEG4 0 650 651 #define DBGU_IO_BASE__INST0_SEG0 0x000001E0 652 #define DBGU_IO_BASE__INST0_SEG1 0 653 #define DBGU_IO_BASE__INST0_SEG2 0 654 #define DBGU_IO_BASE__INST0_SEG3 0 655 #define DBGU_IO_BASE__INST0_SEG4 0 656 657 #define DBGU_IO_BASE__INST1_SEG0 0 658 #define DBGU_IO_BASE__INST1_SEG1 0 659 #define DBGU_IO_BASE__INST1_SEG2 0 660 #define DBGU_IO_BASE__INST1_SEG3 0 661 #define DBGU_IO_BASE__INST1_SEG4 0 662 663 #define DBGU_IO_BASE__INST2_SEG0 0 664 #define DBGU_IO_BASE__INST2_SEG1 0 665 #define DBGU_IO_BASE__INST2_SEG2 0 666 #define DBGU_IO_BASE__INST2_SEG3 0 667 #define DBGU_IO_BASE__INST2_SEG4 0 668 669 #define DBGU_IO_BASE__INST3_SEG0 0 670 #define DBGU_IO_BASE__INST3_SEG1 0 671 #define DBGU_IO_BASE__INST3_SEG2 0 672 #define DBGU_IO_BASE__INST3_SEG3 0 673 #define DBGU_IO_BASE__INST3_SEG4 0 674 675 #define DBGU_IO_BASE__INST4_SEG0 0 676 #define DBGU_IO_BASE__INST4_SEG1 0 677 #define DBGU_IO_BASE__INST4_SEG2 0 678 #define DBGU_IO_BASE__INST4_SEG3 0 679 #define DBGU_IO_BASE__INST4_SEG4 0 680 681 #define DFX_DAP_BASE__INST0_SEG0 0x000005A0 682 #define DFX_DAP_BASE__INST0_SEG1 0 683 #define DFX_DAP_BASE__INST0_SEG2 0 684 #define DFX_DAP_BASE__INST0_SEG3 0 685 #define DFX_DAP_BASE__INST0_SEG4 0 686 687 #define DFX_DAP_BASE__INST1_SEG0 0 688 #define DFX_DAP_BASE__INST1_SEG1 0 689 #define DFX_DAP_BASE__INST1_SEG2 0 690 #define DFX_DAP_BASE__INST1_SEG3 0 691 #define DFX_DAP_BASE__INST1_SEG4 0 692 693 #define DFX_DAP_BASE__INST2_SEG0 0 694 #define DFX_DAP_BASE__INST2_SEG1 0 695 #define DFX_DAP_BASE__INST2_SEG2 0 696 #define DFX_DAP_BASE__INST2_SEG3 0 697 #define DFX_DAP_BASE__INST2_SEG4 0 698 699 #define DFX_DAP_BASE__INST3_SEG0 0 700 #define DFX_DAP_BASE__INST3_SEG1 0 701 #define DFX_DAP_BASE__INST3_SEG2 0 702 #define DFX_DAP_BASE__INST3_SEG3 0 703 #define DFX_DAP_BASE__INST3_SEG4 0 704 705 #define DFX_DAP_BASE__INST4_SEG0 0 706 #define DFX_DAP_BASE__INST4_SEG1 0 707 #define DFX_DAP_BASE__INST4_SEG2 0 708 #define DFX_DAP_BASE__INST4_SEG3 0 709 #define DFX_DAP_BASE__INST4_SEG4 0 710 711 #define DFX_BASE__INST0_SEG0 0x00000580 712 #define DFX_BASE__INST0_SEG1 0 713 #define DFX_BASE__INST0_SEG2 0 714 #define DFX_BASE__INST0_SEG3 0 715 #define DFX_BASE__INST0_SEG4 0 716 717 #define DFX_BASE__INST1_SEG0 0 718 #define DFX_BASE__INST1_SEG1 0 719 #define DFX_BASE__INST1_SEG2 0 720 #define DFX_BASE__INST1_SEG3 0 721 #define DFX_BASE__INST1_SEG4 0 722 723 #define DFX_BASE__INST2_SEG0 0 724 #define DFX_BASE__INST2_SEG1 0 725 #define DFX_BASE__INST2_SEG2 0 726 #define DFX_BASE__INST2_SEG3 0 727 #define DFX_BASE__INST2_SEG4 0 728 729 #define DFX_BASE__INST3_SEG0 0 730 #define DFX_BASE__INST3_SEG1 0 731 #define DFX_BASE__INST3_SEG2 0 732 #define DFX_BASE__INST3_SEG3 0 733 #define DFX_BASE__INST3_SEG4 0 734 735 #define DFX_BASE__INST4_SEG0 0 736 #define DFX_BASE__INST4_SEG1 0 737 #define DFX_BASE__INST4_SEG2 0 738 #define DFX_BASE__INST4_SEG3 0 739 #define DFX_BASE__INST4_SEG4 0 740 741 #define ISP_BASE__INST0_SEG0 0x00018000 742 #define ISP_BASE__INST0_SEG1 0 743 #define ISP_BASE__INST0_SEG2 0 744 #define ISP_BASE__INST0_SEG3 0 745 #define ISP_BASE__INST0_SEG4 0 746 747 #define ISP_BASE__INST1_SEG0 0 748 #define ISP_BASE__INST1_SEG1 0 749 #define ISP_BASE__INST1_SEG2 0 750 #define ISP_BASE__INST1_SEG3 0 751 #define ISP_BASE__INST1_SEG4 0 752 753 #define ISP_BASE__INST2_SEG0 0 754 #define ISP_BASE__INST2_SEG1 0 755 #define ISP_BASE__INST2_SEG2 0 756 #define ISP_BASE__INST2_SEG3 0 757 #define ISP_BASE__INST2_SEG4 0 758 759 #define ISP_BASE__INST3_SEG0 0 760 #define ISP_BASE__INST3_SEG1 0 761 #define ISP_BASE__INST3_SEG2 0 762 #define ISP_BASE__INST3_SEG3 0 763 #define ISP_BASE__INST3_SEG4 0 764 765 #define ISP_BASE__INST4_SEG0 0 766 #define ISP_BASE__INST4_SEG1 0 767 #define ISP_BASE__INST4_SEG2 0 768 #define ISP_BASE__INST4_SEG3 0 769 #define ISP_BASE__INST4_SEG4 0 770 771 #define SYSTEMHUB_BASE__INST0_SEG0 0x00000EA0 772 #define SYSTEMHUB_BASE__INST0_SEG1 0 773 #define SYSTEMHUB_BASE__INST0_SEG2 0 774 #define SYSTEMHUB_BASE__INST0_SEG3 0 775 #define SYSTEMHUB_BASE__INST0_SEG4 0 776 777 #define SYSTEMHUB_BASE__INST1_SEG0 0 778 #define SYSTEMHUB_BASE__INST1_SEG1 0 779 #define SYSTEMHUB_BASE__INST1_SEG2 0 780 #define SYSTEMHUB_BASE__INST1_SEG3 0 781 #define SYSTEMHUB_BASE__INST1_SEG4 0 782 783 #define SYSTEMHUB_BASE__INST2_SEG0 0 784 #define SYSTEMHUB_BASE__INST2_SEG1 0 785 #define SYSTEMHUB_BASE__INST2_SEG2 0 786 #define SYSTEMHUB_BASE__INST2_SEG3 0 787 #define SYSTEMHUB_BASE__INST2_SEG4 0 788 789 #define SYSTEMHUB_BASE__INST3_SEG0 0 790 #define SYSTEMHUB_BASE__INST3_SEG1 0 791 #define SYSTEMHUB_BASE__INST3_SEG2 0 792 #define SYSTEMHUB_BASE__INST3_SEG3 0 793 #define SYSTEMHUB_BASE__INST3_SEG4 0 794 795 #define SYSTEMHUB_BASE__INST4_SEG0 0 796 #define SYSTEMHUB_BASE__INST4_SEG1 0 797 #define SYSTEMHUB_BASE__INST4_SEG2 0 798 #define SYSTEMHUB_BASE__INST4_SEG3 0 799 #define SYSTEMHUB_BASE__INST4_SEG4 0 800 801 #define L2IMU_BASE__INST0_SEG0 0x00007DC0 802 #define L2IMU_BASE__INST0_SEG1 0 803 #define L2IMU_BASE__INST0_SEG2 0 804 #define L2IMU_BASE__INST0_SEG3 0 805 #define L2IMU_BASE__INST0_SEG4 0 806 807 #define L2IMU_BASE__INST1_SEG0 0 808 #define L2IMU_BASE__INST1_SEG1 0 809 #define L2IMU_BASE__INST1_SEG2 0 810 #define L2IMU_BASE__INST1_SEG3 0 811 #define L2IMU_BASE__INST1_SEG4 0 812 813 #define L2IMU_BASE__INST2_SEG0 0 814 #define L2IMU_BASE__INST2_SEG1 0 815 #define L2IMU_BASE__INST2_SEG2 0 816 #define L2IMU_BASE__INST2_SEG3 0 817 #define L2IMU_BASE__INST2_SEG4 0 818 819 #define L2IMU_BASE__INST3_SEG0 0 820 #define L2IMU_BASE__INST3_SEG1 0 821 #define L2IMU_BASE__INST3_SEG2 0 822 #define L2IMU_BASE__INST3_SEG3 0 823 #define L2IMU_BASE__INST3_SEG4 0 824 825 #define L2IMU_BASE__INST4_SEG0 0 826 #define L2IMU_BASE__INST4_SEG1 0 827 #define L2IMU_BASE__INST4_SEG2 0 828 #define L2IMU_BASE__INST4_SEG3 0 829 #define L2IMU_BASE__INST4_SEG4 0 830 831 #define IOHC_BASE__INST0_SEG0 0x00010000 832 #define IOHC_BASE__INST0_SEG1 0 833 #define IOHC_BASE__INST0_SEG2 0 834 #define IOHC_BASE__INST0_SEG3 0 835 #define IOHC_BASE__INST0_SEG4 0 836 837 #define IOHC_BASE__INST1_SEG0 0 838 #define IOHC_BASE__INST1_SEG1 0 839 #define IOHC_BASE__INST1_SEG2 0 840 #define IOHC_BASE__INST1_SEG3 0 841 #define IOHC_BASE__INST1_SEG4 0 842 843 #define IOHC_BASE__INST2_SEG0 0 844 #define IOHC_BASE__INST2_SEG1 0 845 #define IOHC_BASE__INST2_SEG2 0 846 #define IOHC_BASE__INST2_SEG3 0 847 #define IOHC_BASE__INST2_SEG4 0 848 849 #define IOHC_BASE__INST3_SEG0 0 850 #define IOHC_BASE__INST3_SEG1 0 851 #define IOHC_BASE__INST3_SEG2 0 852 #define IOHC_BASE__INST3_SEG3 0 853 #define IOHC_BASE__INST3_SEG4 0 854 855 #define IOHC_BASE__INST4_SEG0 0 856 #define IOHC_BASE__INST4_SEG1 0 857 #define IOHC_BASE__INST4_SEG2 0 858 #define IOHC_BASE__INST4_SEG3 0 859 #define IOHC_BASE__INST4_SEG4 0 860 861 #define ATHUB_BASE__INST0_SEG0 0x00000C20 862 #define ATHUB_BASE__INST0_SEG1 0 863 #define ATHUB_BASE__INST0_SEG2 0 864 #define ATHUB_BASE__INST0_SEG3 0 865 #define ATHUB_BASE__INST0_SEG4 0 866 867 #define ATHUB_BASE__INST1_SEG0 0 868 #define ATHUB_BASE__INST1_SEG1 0 869 #define ATHUB_BASE__INST1_SEG2 0 870 #define ATHUB_BASE__INST1_SEG3 0 871 #define ATHUB_BASE__INST1_SEG4 0 872 873 #define ATHUB_BASE__INST2_SEG0 0 874 #define ATHUB_BASE__INST2_SEG1 0 875 #define ATHUB_BASE__INST2_SEG2 0 876 #define ATHUB_BASE__INST2_SEG3 0 877 #define ATHUB_BASE__INST2_SEG4 0 878 879 #define ATHUB_BASE__INST3_SEG0 0 880 #define ATHUB_BASE__INST3_SEG1 0 881 #define ATHUB_BASE__INST3_SEG2 0 882 #define ATHUB_BASE__INST3_SEG3 0 883 #define ATHUB_BASE__INST3_SEG4 0 884 885 #define ATHUB_BASE__INST4_SEG0 0 886 #define ATHUB_BASE__INST4_SEG1 0 887 #define ATHUB_BASE__INST4_SEG2 0 888 #define ATHUB_BASE__INST4_SEG3 0 889 #define ATHUB_BASE__INST4_SEG4 0 890 891 #define VCE_BASE__INST0_SEG0 0x00007E00 892 #define VCE_BASE__INST0_SEG1 0x00048800 893 #define VCE_BASE__INST0_SEG2 0 894 #define VCE_BASE__INST0_SEG3 0 895 #define VCE_BASE__INST0_SEG4 0 896 897 #define VCE_BASE__INST1_SEG0 0 898 #define VCE_BASE__INST1_SEG1 0 899 #define VCE_BASE__INST1_SEG2 0 900 #define VCE_BASE__INST1_SEG3 0 901 #define VCE_BASE__INST1_SEG4 0 902 903 #define VCE_BASE__INST2_SEG0 0 904 #define VCE_BASE__INST2_SEG1 0 905 #define VCE_BASE__INST2_SEG2 0 906 #define VCE_BASE__INST2_SEG3 0 907 #define VCE_BASE__INST2_SEG4 0 908 909 #define VCE_BASE__INST3_SEG0 0 910 #define VCE_BASE__INST3_SEG1 0 911 #define VCE_BASE__INST3_SEG2 0 912 #define VCE_BASE__INST3_SEG3 0 913 #define VCE_BASE__INST3_SEG4 0 914 915 #define VCE_BASE__INST4_SEG0 0 916 #define VCE_BASE__INST4_SEG1 0 917 #define VCE_BASE__INST4_SEG2 0 918 #define VCE_BASE__INST4_SEG3 0 919 #define VCE_BASE__INST4_SEG4 0 920 921 #define GC_BASE__INST0_SEG0 0x00002000 922 #define GC_BASE__INST0_SEG1 0x0000A000 923 #define GC_BASE__INST0_SEG2 0 924 #define GC_BASE__INST0_SEG3 0 925 #define GC_BASE__INST0_SEG4 0 926 927 #define GC_BASE__INST1_SEG0 0 928 #define GC_BASE__INST1_SEG1 0 929 #define GC_BASE__INST1_SEG2 0 930 #define GC_BASE__INST1_SEG3 0 931 #define GC_BASE__INST1_SEG4 0 932 933 #define GC_BASE__INST2_SEG0 0 934 #define GC_BASE__INST2_SEG1 0 935 #define GC_BASE__INST2_SEG2 0 936 #define GC_BASE__INST2_SEG3 0 937 #define GC_BASE__INST2_SEG4 0 938 939 #define GC_BASE__INST3_SEG0 0 940 #define GC_BASE__INST3_SEG1 0 941 #define GC_BASE__INST3_SEG2 0 942 #define GC_BASE__INST3_SEG3 0 943 #define GC_BASE__INST3_SEG4 0 944 945 #define GC_BASE__INST4_SEG0 0 946 #define GC_BASE__INST4_SEG1 0 947 #define GC_BASE__INST4_SEG2 0 948 #define GC_BASE__INST4_SEG3 0 949 #define GC_BASE__INST4_SEG4 0 950 951 #define MMHUB_BASE__INST0_SEG0 0x0001A000 952 #define MMHUB_BASE__INST0_SEG1 0 953 #define MMHUB_BASE__INST0_SEG2 0 954 #define MMHUB_BASE__INST0_SEG3 0 955 #define MMHUB_BASE__INST0_SEG4 0 956 957 #define MMHUB_BASE__INST1_SEG0 0 958 #define MMHUB_BASE__INST1_SEG1 0 959 #define MMHUB_BASE__INST1_SEG2 0 960 #define MMHUB_BASE__INST1_SEG3 0 961 #define MMHUB_BASE__INST1_SEG4 0 962 963 #define MMHUB_BASE__INST2_SEG0 0 964 #define MMHUB_BASE__INST2_SEG1 0 965 #define MMHUB_BASE__INST2_SEG2 0 966 #define MMHUB_BASE__INST2_SEG3 0 967 #define MMHUB_BASE__INST2_SEG4 0 968 969 #define MMHUB_BASE__INST3_SEG0 0 970 #define MMHUB_BASE__INST3_SEG1 0 971 #define MMHUB_BASE__INST3_SEG2 0 972 #define MMHUB_BASE__INST3_SEG3 0 973 #define MMHUB_BASE__INST3_SEG4 0 974 975 #define MMHUB_BASE__INST4_SEG0 0 976 #define MMHUB_BASE__INST4_SEG1 0 977 #define MMHUB_BASE__INST4_SEG2 0 978 #define MMHUB_BASE__INST4_SEG3 0 979 #define MMHUB_BASE__INST4_SEG4 0 980 981 #define RSMU_BASE__INST0_SEG0 0x00012000 982 #define RSMU_BASE__INST0_SEG1 0 983 #define RSMU_BASE__INST0_SEG2 0 984 #define RSMU_BASE__INST0_SEG3 0 985 #define RSMU_BASE__INST0_SEG4 0 986 987 #define RSMU_BASE__INST1_SEG0 0 988 #define RSMU_BASE__INST1_SEG1 0 989 #define RSMU_BASE__INST1_SEG2 0 990 #define RSMU_BASE__INST1_SEG3 0 991 #define RSMU_BASE__INST1_SEG4 0 992 993 #define RSMU_BASE__INST2_SEG0 0 994 #define RSMU_BASE__INST2_SEG1 0 995 #define RSMU_BASE__INST2_SEG2 0 996 #define RSMU_BASE__INST2_SEG3 0 997 #define RSMU_BASE__INST2_SEG4 0 998 999 #define RSMU_BASE__INST3_SEG0 0 1000 #define RSMU_BASE__INST3_SEG1 0 1001 #define RSMU_BASE__INST3_SEG2 0 1002 #define RSMU_BASE__INST3_SEG3 0 1003 #define RSMU_BASE__INST3_SEG4 0 1004 1005 #define RSMU_BASE__INST4_SEG0 0 1006 #define RSMU_BASE__INST4_SEG1 0 1007 #define RSMU_BASE__INST4_SEG2 0 1008 #define RSMU_BASE__INST4_SEG3 0 1009 #define RSMU_BASE__INST4_SEG4 0 1010 1011 #define HDP_BASE__INST0_SEG0 0x00000F20 1012 #define HDP_BASE__INST0_SEG1 0 1013 #define HDP_BASE__INST0_SEG2 0 1014 #define HDP_BASE__INST0_SEG3 0 1015 #define HDP_BASE__INST0_SEG4 0 1016 1017 #define HDP_BASE__INST1_SEG0 0 1018 #define HDP_BASE__INST1_SEG1 0 1019 #define HDP_BASE__INST1_SEG2 0 1020 #define HDP_BASE__INST1_SEG3 0 1021 #define HDP_BASE__INST1_SEG4 0 1022 1023 #define HDP_BASE__INST2_SEG0 0 1024 #define HDP_BASE__INST2_SEG1 0 1025 #define HDP_BASE__INST2_SEG2 0 1026 #define HDP_BASE__INST2_SEG3 0 1027 #define HDP_BASE__INST2_SEG4 0 1028 1029 #define HDP_BASE__INST3_SEG0 0 1030 #define HDP_BASE__INST3_SEG1 0 1031 #define HDP_BASE__INST3_SEG2 0 1032 #define HDP_BASE__INST3_SEG3 0 1033 #define HDP_BASE__INST3_SEG4 0 1034 1035 #define HDP_BASE__INST4_SEG0 0 1036 #define HDP_BASE__INST4_SEG1 0 1037 #define HDP_BASE__INST4_SEG2 0 1038 #define HDP_BASE__INST4_SEG3 0 1039 #define HDP_BASE__INST4_SEG4 0 1040 1041 #define OSSSYS_BASE__INST0_SEG0 0x000010A0 1042 #define OSSSYS_BASE__INST0_SEG1 0 1043 #define OSSSYS_BASE__INST0_SEG2 0 1044 #define OSSSYS_BASE__INST0_SEG3 0 1045 #define OSSSYS_BASE__INST0_SEG4 0 1046 1047 #define OSSSYS_BASE__INST1_SEG0 0 1048 #define OSSSYS_BASE__INST1_SEG1 0 1049 #define OSSSYS_BASE__INST1_SEG2 0 1050 #define OSSSYS_BASE__INST1_SEG3 0 1051 #define OSSSYS_BASE__INST1_SEG4 0 1052 1053 #define OSSSYS_BASE__INST2_SEG0 0 1054 #define OSSSYS_BASE__INST2_SEG1 0 1055 #define OSSSYS_BASE__INST2_SEG2 0 1056 #define OSSSYS_BASE__INST2_SEG3 0 1057 #define OSSSYS_BASE__INST2_SEG4 0 1058 1059 #define OSSSYS_BASE__INST3_SEG0 0 1060 #define OSSSYS_BASE__INST3_SEG1 0 1061 #define OSSSYS_BASE__INST3_SEG2 0 1062 #define OSSSYS_BASE__INST3_SEG3 0 1063 #define OSSSYS_BASE__INST3_SEG4 0 1064 1065 #define OSSSYS_BASE__INST4_SEG0 0 1066 #define OSSSYS_BASE__INST4_SEG1 0 1067 #define OSSSYS_BASE__INST4_SEG2 0 1068 #define OSSSYS_BASE__INST4_SEG3 0 1069 #define OSSSYS_BASE__INST4_SEG4 0 1070 1071 #define SDMA0_BASE__INST0_SEG0 0x00001260 1072 #define SDMA0_BASE__INST0_SEG1 0 1073 #define SDMA0_BASE__INST0_SEG2 0 1074 #define SDMA0_BASE__INST0_SEG3 0 1075 #define SDMA0_BASE__INST0_SEG4 0 1076 1077 #define SDMA0_BASE__INST1_SEG0 0 1078 #define SDMA0_BASE__INST1_SEG1 0 1079 #define SDMA0_BASE__INST1_SEG2 0 1080 #define SDMA0_BASE__INST1_SEG3 0 1081 #define SDMA0_BASE__INST1_SEG4 0 1082 1083 #define SDMA0_BASE__INST2_SEG0 0 1084 #define SDMA0_BASE__INST2_SEG1 0 1085 #define SDMA0_BASE__INST2_SEG2 0 1086 #define SDMA0_BASE__INST2_SEG3 0 1087 #define SDMA0_BASE__INST2_SEG4 0 1088 1089 #define SDMA0_BASE__INST3_SEG0 0 1090 #define SDMA0_BASE__INST3_SEG1 0 1091 #define SDMA0_BASE__INST3_SEG2 0 1092 #define SDMA0_BASE__INST3_SEG3 0 1093 #define SDMA0_BASE__INST3_SEG4 0 1094 1095 #define SDMA0_BASE__INST4_SEG0 0 1096 #define SDMA0_BASE__INST4_SEG1 0 1097 #define SDMA0_BASE__INST4_SEG2 0 1098 #define SDMA0_BASE__INST4_SEG3 0 1099 #define SDMA0_BASE__INST4_SEG4 0 1100 1101 #define SDMA1_BASE__INST0_SEG0 0x00001460 1102 #define SDMA1_BASE__INST0_SEG1 0 1103 #define SDMA1_BASE__INST0_SEG2 0 1104 #define SDMA1_BASE__INST0_SEG3 0 1105 #define SDMA1_BASE__INST0_SEG4 0 1106 1107 #define SDMA1_BASE__INST1_SEG0 0 1108 #define SDMA1_BASE__INST1_SEG1 0 1109 #define SDMA1_BASE__INST1_SEG2 0 1110 #define SDMA1_BASE__INST1_SEG3 0 1111 #define SDMA1_BASE__INST1_SEG4 0 1112 1113 #define SDMA1_BASE__INST2_SEG0 0 1114 #define SDMA1_BASE__INST2_SEG1 0 1115 #define SDMA1_BASE__INST2_SEG2 0 1116 #define SDMA1_BASE__INST2_SEG3 0 1117 #define SDMA1_BASE__INST2_SEG4 0 1118 1119 #define SDMA1_BASE__INST3_SEG0 0 1120 #define SDMA1_BASE__INST3_SEG1 0 1121 #define SDMA1_BASE__INST3_SEG2 0 1122 #define SDMA1_BASE__INST3_SEG3 0 1123 #define SDMA1_BASE__INST3_SEG4 0 1124 1125 #define SDMA1_BASE__INST4_SEG0 0 1126 #define SDMA1_BASE__INST4_SEG1 0 1127 #define SDMA1_BASE__INST4_SEG2 0 1128 #define SDMA1_BASE__INST4_SEG3 0 1129 #define SDMA1_BASE__INST4_SEG4 0 1130 1131 #define XDMA_BASE__INST0_SEG0 0x00003400 1132 #define XDMA_BASE__INST0_SEG1 0 1133 #define XDMA_BASE__INST0_SEG2 0 1134 #define XDMA_BASE__INST0_SEG3 0 1135 #define XDMA_BASE__INST0_SEG4 0 1136 1137 #define XDMA_BASE__INST1_SEG0 0 1138 #define XDMA_BASE__INST1_SEG1 0 1139 #define XDMA_BASE__INST1_SEG2 0 1140 #define XDMA_BASE__INST1_SEG3 0 1141 #define XDMA_BASE__INST1_SEG4 0 1142 1143 #define XDMA_BASE__INST2_SEG0 0 1144 #define XDMA_BASE__INST2_SEG1 0 1145 #define XDMA_BASE__INST2_SEG2 0 1146 #define XDMA_BASE__INST2_SEG3 0 1147 #define XDMA_BASE__INST2_SEG4 0 1148 1149 #define XDMA_BASE__INST3_SEG0 0 1150 #define XDMA_BASE__INST3_SEG1 0 1151 #define XDMA_BASE__INST3_SEG2 0 1152 #define XDMA_BASE__INST3_SEG3 0 1153 #define XDMA_BASE__INST3_SEG4 0 1154 1155 #define XDMA_BASE__INST4_SEG0 0 1156 #define XDMA_BASE__INST4_SEG1 0 1157 #define XDMA_BASE__INST4_SEG2 0 1158 #define XDMA_BASE__INST4_SEG3 0 1159 #define XDMA_BASE__INST4_SEG4 0 1160 1161 #define UMC_BASE__INST0_SEG0 0x00014000 1162 #define UMC_BASE__INST0_SEG1 0 1163 #define UMC_BASE__INST0_SEG2 0 1164 #define UMC_BASE__INST0_SEG3 0 1165 #define UMC_BASE__INST0_SEG4 0 1166 1167 #define UMC_BASE__INST1_SEG0 0 1168 #define UMC_BASE__INST1_SEG1 0 1169 #define UMC_BASE__INST1_SEG2 0 1170 #define UMC_BASE__INST1_SEG3 0 1171 #define UMC_BASE__INST1_SEG4 0 1172 1173 #define UMC_BASE__INST2_SEG0 0 1174 #define UMC_BASE__INST2_SEG1 0 1175 #define UMC_BASE__INST2_SEG2 0 1176 #define UMC_BASE__INST2_SEG3 0 1177 #define UMC_BASE__INST2_SEG4 0 1178 1179 #define UMC_BASE__INST3_SEG0 0 1180 #define UMC_BASE__INST3_SEG1 0 1181 #define UMC_BASE__INST3_SEG2 0 1182 #define UMC_BASE__INST3_SEG3 0 1183 #define UMC_BASE__INST3_SEG4 0 1184 1185 #define UMC_BASE__INST4_SEG0 0 1186 #define UMC_BASE__INST4_SEG1 0 1187 #define UMC_BASE__INST4_SEG2 0 1188 #define UMC_BASE__INST4_SEG3 0 1189 #define UMC_BASE__INST4_SEG4 0 1190 1191 #define THM_BASE__INST0_SEG0 0x00016600 1192 #define THM_BASE__INST0_SEG1 0 1193 #define THM_BASE__INST0_SEG2 0 1194 #define THM_BASE__INST0_SEG3 0 1195 #define THM_BASE__INST0_SEG4 0 1196 1197 #define THM_BASE__INST1_SEG0 0 1198 #define THM_BASE__INST1_SEG1 0 1199 #define THM_BASE__INST1_SEG2 0 1200 #define THM_BASE__INST1_SEG3 0 1201 #define THM_BASE__INST1_SEG4 0 1202 1203 #define THM_BASE__INST2_SEG0 0 1204 #define THM_BASE__INST2_SEG1 0 1205 #define THM_BASE__INST2_SEG2 0 1206 #define THM_BASE__INST2_SEG3 0 1207 #define THM_BASE__INST2_SEG4 0 1208 1209 #define THM_BASE__INST3_SEG0 0 1210 #define THM_BASE__INST3_SEG1 0 1211 #define THM_BASE__INST3_SEG2 0 1212 #define THM_BASE__INST3_SEG3 0 1213 #define THM_BASE__INST3_SEG4 0 1214 1215 #define THM_BASE__INST4_SEG0 0 1216 #define THM_BASE__INST4_SEG1 0 1217 #define THM_BASE__INST4_SEG2 0 1218 #define THM_BASE__INST4_SEG3 0 1219 #define THM_BASE__INST4_SEG4 0 1220 1221 #define SMUIO_BASE__INST0_SEG0 0x00016800 1222 #define SMUIO_BASE__INST0_SEG1 0 1223 #define SMUIO_BASE__INST0_SEG2 0 1224 #define SMUIO_BASE__INST0_SEG3 0 1225 #define SMUIO_BASE__INST0_SEG4 0 1226 1227 #define SMUIO_BASE__INST1_SEG0 0 1228 #define SMUIO_BASE__INST1_SEG1 0 1229 #define SMUIO_BASE__INST1_SEG2 0 1230 #define SMUIO_BASE__INST1_SEG3 0 1231 #define SMUIO_BASE__INST1_SEG4 0 1232 1233 #define SMUIO_BASE__INST2_SEG0 0 1234 #define SMUIO_BASE__INST2_SEG1 0 1235 #define SMUIO_BASE__INST2_SEG2 0 1236 #define SMUIO_BASE__INST2_SEG3 0 1237 #define SMUIO_BASE__INST2_SEG4 0 1238 1239 #define SMUIO_BASE__INST3_SEG0 0 1240 #define SMUIO_BASE__INST3_SEG1 0 1241 #define SMUIO_BASE__INST3_SEG2 0 1242 #define SMUIO_BASE__INST3_SEG3 0 1243 #define SMUIO_BASE__INST3_SEG4 0 1244 1245 #define SMUIO_BASE__INST4_SEG0 0 1246 #define SMUIO_BASE__INST4_SEG1 0 1247 #define SMUIO_BASE__INST4_SEG2 0 1248 #define SMUIO_BASE__INST4_SEG3 0 1249 #define SMUIO_BASE__INST4_SEG4 0 1250 1251 #define PWR_BASE__INST0_SEG0 0x00016A00 1252 #define PWR_BASE__INST0_SEG1 0 1253 #define PWR_BASE__INST0_SEG2 0 1254 #define PWR_BASE__INST0_SEG3 0 1255 #define PWR_BASE__INST0_SEG4 0 1256 1257 #define PWR_BASE__INST1_SEG0 0 1258 #define PWR_BASE__INST1_SEG1 0 1259 #define PWR_BASE__INST1_SEG2 0 1260 #define PWR_BASE__INST1_SEG3 0 1261 #define PWR_BASE__INST1_SEG4 0 1262 1263 #define PWR_BASE__INST2_SEG0 0 1264 #define PWR_BASE__INST2_SEG1 0 1265 #define PWR_BASE__INST2_SEG2 0 1266 #define PWR_BASE__INST2_SEG3 0 1267 #define PWR_BASE__INST2_SEG4 0 1268 1269 #define PWR_BASE__INST3_SEG0 0 1270 #define PWR_BASE__INST3_SEG1 0 1271 #define PWR_BASE__INST3_SEG2 0 1272 #define PWR_BASE__INST3_SEG3 0 1273 #define PWR_BASE__INST3_SEG4 0 1274 1275 #define PWR_BASE__INST4_SEG0 0 1276 #define PWR_BASE__INST4_SEG1 0 1277 #define PWR_BASE__INST4_SEG2 0 1278 #define PWR_BASE__INST4_SEG3 0 1279 #define PWR_BASE__INST4_SEG4 0 1280 1281 #define CLK_BASE__INST0_SEG0 0x00016C00 1282 #define CLK_BASE__INST0_SEG1 0 1283 #define CLK_BASE__INST0_SEG2 0 1284 #define CLK_BASE__INST0_SEG3 0 1285 #define CLK_BASE__INST0_SEG4 0 1286 1287 #define CLK_BASE__INST1_SEG0 0x00016E00 1288 #define CLK_BASE__INST1_SEG1 0 1289 #define CLK_BASE__INST1_SEG2 0 1290 #define CLK_BASE__INST1_SEG3 0 1291 #define CLK_BASE__INST1_SEG4 0 1292 1293 #define CLK_BASE__INST2_SEG0 0x00017000 1294 #define CLK_BASE__INST2_SEG1 0 1295 #define CLK_BASE__INST2_SEG2 0 1296 #define CLK_BASE__INST2_SEG3 0 1297 #define CLK_BASE__INST2_SEG4 0 1298 1299 #define CLK_BASE__INST3_SEG0 0x00017200 1300 #define CLK_BASE__INST3_SEG1 0 1301 #define CLK_BASE__INST3_SEG2 0 1302 #define CLK_BASE__INST3_SEG3 0 1303 #define CLK_BASE__INST3_SEG4 0 1304 1305 #define CLK_BASE__INST4_SEG0 0x00017E00 1306 #define CLK_BASE__INST4_SEG1 0 1307 #define CLK_BASE__INST4_SEG2 0 1308 #define CLK_BASE__INST4_SEG3 0 1309 #define CLK_BASE__INST4_SEG4 0 1310 1311 #define FUSE_BASE__INST0_SEG0 0x00017400 1312 #define FUSE_BASE__INST0_SEG1 0 1313 #define FUSE_BASE__INST0_SEG2 0 1314 #define FUSE_BASE__INST0_SEG3 0 1315 #define FUSE_BASE__INST0_SEG4 0 1316 1317 #define FUSE_BASE__INST1_SEG0 0 1318 #define FUSE_BASE__INST1_SEG1 0 1319 #define FUSE_BASE__INST1_SEG2 0 1320 #define FUSE_BASE__INST1_SEG3 0 1321 #define FUSE_BASE__INST1_SEG4 0 1322 1323 #define FUSE_BASE__INST2_SEG0 0 1324 #define FUSE_BASE__INST2_SEG1 0 1325 #define FUSE_BASE__INST2_SEG2 0 1326 #define FUSE_BASE__INST2_SEG3 0 1327 #define FUSE_BASE__INST2_SEG4 0 1328 1329 #define FUSE_BASE__INST3_SEG0 0 1330 #define FUSE_BASE__INST3_SEG1 0 1331 #define FUSE_BASE__INST3_SEG2 0 1332 #define FUSE_BASE__INST3_SEG3 0 1333 #define FUSE_BASE__INST3_SEG4 0 1334 1335 #define FUSE_BASE__INST4_SEG0 0 1336 #define FUSE_BASE__INST4_SEG1 0 1337 #define FUSE_BASE__INST4_SEG2 0 1338 #define FUSE_BASE__INST4_SEG3 0 1339 #define FUSE_BASE__INST4_SEG4 0 1340 1341 1342 #endif 1343 1344