1 /*
2 * Copyright 2015 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 */
23 #include "pp_debug.h"
24 #include <linux/module.h>
25 #include <linux/slab.h>
26
27 #include "process_pptables_v1_0.h"
28 #include "ppatomctrl.h"
29 #include "atombios.h"
30 #include "hwmgr.h"
31 #include "cgs_common.h"
32 #include "pptable_v1_0.h"
33
34 /**
35 * Private Function used during initialization.
36 * @param hwmgr Pointer to the hardware manager.
37 * @param setIt A flag indication if the capability should be set (TRUE) or reset (FALSE).
38 * @param cap Which capability to set/reset.
39 */
set_hw_cap(struct pp_hwmgr * hwmgr,bool setIt,enum phm_platform_caps cap)40 static void set_hw_cap(struct pp_hwmgr *hwmgr, bool setIt, enum phm_platform_caps cap)
41 {
42 if (setIt)
43 phm_cap_set(hwmgr->platform_descriptor.platformCaps, cap);
44 else
45 phm_cap_unset(hwmgr->platform_descriptor.platformCaps, cap);
46 }
47
48
49 /**
50 * Private Function used during initialization.
51 * @param hwmgr Pointer to the hardware manager.
52 * @param powerplay_caps the bit array (from BIOS) of capability bits.
53 * @exception the current implementation always returns 1.
54 */
set_platform_caps(struct pp_hwmgr * hwmgr,uint32_t powerplay_caps)55 static int set_platform_caps(struct pp_hwmgr *hwmgr, uint32_t powerplay_caps)
56 {
57 PP_ASSERT_WITH_CODE((~powerplay_caps & ____RETIRE16____),
58 "ATOM_PP_PLATFORM_CAP_ASPM_L1 is not supported!", continue);
59 PP_ASSERT_WITH_CODE((~powerplay_caps & ____RETIRE64____),
60 "ATOM_PP_PLATFORM_CAP_GEMINIPRIMARY is not supported!", continue);
61 PP_ASSERT_WITH_CODE((~powerplay_caps & ____RETIRE512____),
62 "ATOM_PP_PLATFORM_CAP_SIDEPORTCONTROL is not supported!", continue);
63 PP_ASSERT_WITH_CODE((~powerplay_caps & ____RETIRE1024____),
64 "ATOM_PP_PLATFORM_CAP_TURNOFFPLL_ASPML1 is not supported!", continue);
65 PP_ASSERT_WITH_CODE((~powerplay_caps & ____RETIRE2048____),
66 "ATOM_PP_PLATFORM_CAP_HTLINKCONTROL is not supported!", continue);
67
68 set_hw_cap(
69 hwmgr,
70 0 != (powerplay_caps & ATOM_TONGA_PP_PLATFORM_CAP_POWERPLAY),
71 PHM_PlatformCaps_PowerPlaySupport
72 );
73
74 set_hw_cap(
75 hwmgr,
76 0 != (powerplay_caps & ATOM_TONGA_PP_PLATFORM_CAP_SBIOSPOWERSOURCE),
77 PHM_PlatformCaps_BiosPowerSourceControl
78 );
79
80 set_hw_cap(
81 hwmgr,
82 0 != (powerplay_caps & ATOM_TONGA_PP_PLATFORM_CAP_HARDWAREDC),
83 PHM_PlatformCaps_AutomaticDCTransition
84 );
85
86 set_hw_cap(
87 hwmgr,
88 0 != (powerplay_caps & ATOM_TONGA_PP_PLATFORM_CAP_MVDD_CONTROL),
89 PHM_PlatformCaps_EnableMVDDControl
90 );
91
92 set_hw_cap(
93 hwmgr,
94 0 != (powerplay_caps & ATOM_TONGA_PP_PLATFORM_CAP_VDDCI_CONTROL),
95 PHM_PlatformCaps_ControlVDDCI
96 );
97
98 set_hw_cap(
99 hwmgr,
100 0 != (powerplay_caps & ATOM_TONGA_PP_PLATFORM_CAP_VDDGFX_CONTROL),
101 PHM_PlatformCaps_ControlVDDGFX
102 );
103
104 set_hw_cap(
105 hwmgr,
106 0 != (powerplay_caps & ATOM_TONGA_PP_PLATFORM_CAP_BACO),
107 PHM_PlatformCaps_BACO
108 );
109
110 set_hw_cap(
111 hwmgr,
112 0 != (powerplay_caps & ATOM_TONGA_PP_PLATFORM_CAP_DISABLE_VOLTAGE_ISLAND),
113 PHM_PlatformCaps_DisableVoltageIsland
114 );
115
116 set_hw_cap(
117 hwmgr,
118 0 != (powerplay_caps & ATOM_TONGA_PP_PLATFORM_COMBINE_PCC_WITH_THERMAL_SIGNAL),
119 PHM_PlatformCaps_CombinePCCWithThermalSignal
120 );
121
122 set_hw_cap(
123 hwmgr,
124 0 != (powerplay_caps & ATOM_TONGA_PLATFORM_LOAD_POST_PRODUCTION_FIRMWARE),
125 PHM_PlatformCaps_LoadPostProductionFirmware
126 );
127
128 return 0;
129 }
130
131 /**
132 * Private Function to get the PowerPlay Table Address.
133 */
get_powerplay_table(struct pp_hwmgr * hwmgr)134 static const void *get_powerplay_table(struct pp_hwmgr *hwmgr)
135 {
136 int index = GetIndexIntoMasterTable(DATA, PowerPlayInfo);
137
138 u16 size;
139 u8 frev, crev;
140 void *table_address = (void *)hwmgr->soft_pp_table;
141
142 if (!table_address) {
143 table_address = (ATOM_Tonga_POWERPLAYTABLE *)
144 cgs_atom_get_data_table(hwmgr->device,
145 index, &size, &frev, &crev);
146 hwmgr->soft_pp_table = table_address; /*Cache the result in RAM.*/
147 hwmgr->soft_pp_table_size = size;
148 }
149
150 return table_address;
151 }
152
get_vddc_lookup_table(struct pp_hwmgr * hwmgr,phm_ppt_v1_voltage_lookup_table ** lookup_table,const ATOM_Tonga_Voltage_Lookup_Table * vddc_lookup_pp_tables,uint32_t max_levels)153 static int get_vddc_lookup_table(
154 struct pp_hwmgr *hwmgr,
155 phm_ppt_v1_voltage_lookup_table **lookup_table,
156 const ATOM_Tonga_Voltage_Lookup_Table *vddc_lookup_pp_tables,
157 uint32_t max_levels
158 )
159 {
160 uint32_t table_size, i;
161 phm_ppt_v1_voltage_lookup_table *table;
162 phm_ppt_v1_voltage_lookup_record *record;
163 ATOM_Tonga_Voltage_Lookup_Record *atom_record;
164
165 PP_ASSERT_WITH_CODE((0 != vddc_lookup_pp_tables->ucNumEntries),
166 "Invalid CAC Leakage PowerPlay Table!", return 1);
167
168 table_size = sizeof(uint32_t) +
169 sizeof(phm_ppt_v1_voltage_lookup_record) * max_levels;
170
171 table = kzalloc(table_size, GFP_KERNEL);
172
173 if (NULL == table)
174 return -ENOMEM;
175
176 memset(table, 0x00, table_size);
177
178 table->count = vddc_lookup_pp_tables->ucNumEntries;
179
180 for (i = 0; i < vddc_lookup_pp_tables->ucNumEntries; i++) {
181 record = GET_FLEXIBLE_ARRAY_MEMBER_ADDR(
182 phm_ppt_v1_voltage_lookup_record,
183 entries, table, i);
184 atom_record = GET_FLEXIBLE_ARRAY_MEMBER_ADDR(
185 ATOM_Tonga_Voltage_Lookup_Record,
186 entries, vddc_lookup_pp_tables, i);
187 record->us_calculated = 0;
188 record->us_vdd = atom_record->usVdd;
189 record->us_cac_low = atom_record->usCACLow;
190 record->us_cac_mid = atom_record->usCACMid;
191 record->us_cac_high = atom_record->usCACHigh;
192 }
193
194 *lookup_table = table;
195
196 return 0;
197 }
198
199 /**
200 * Private Function used during initialization.
201 * Initialize Platform Power Management Parameter table
202 * @param hwmgr Pointer to the hardware manager.
203 * @param atom_ppm_table Pointer to PPM table in VBIOS
204 */
get_platform_power_management_table(struct pp_hwmgr * hwmgr,ATOM_Tonga_PPM_Table * atom_ppm_table)205 static int get_platform_power_management_table(
206 struct pp_hwmgr *hwmgr,
207 ATOM_Tonga_PPM_Table *atom_ppm_table)
208 {
209 struct phm_ppm_table *ptr = kzalloc(sizeof(ATOM_Tonga_PPM_Table), GFP_KERNEL);
210 struct phm_ppt_v1_information *pp_table_information =
211 (struct phm_ppt_v1_information *)(hwmgr->pptable);
212
213 if (NULL == ptr)
214 return -ENOMEM;
215
216 ptr->ppm_design
217 = atom_ppm_table->ucPpmDesign;
218 ptr->cpu_core_number
219 = atom_ppm_table->usCpuCoreNumber;
220 ptr->platform_tdp
221 = atom_ppm_table->ulPlatformTDP;
222 ptr->small_ac_platform_tdp
223 = atom_ppm_table->ulSmallACPlatformTDP;
224 ptr->platform_tdc
225 = atom_ppm_table->ulPlatformTDC;
226 ptr->small_ac_platform_tdc
227 = atom_ppm_table->ulSmallACPlatformTDC;
228 ptr->apu_tdp
229 = atom_ppm_table->ulApuTDP;
230 ptr->dgpu_tdp
231 = atom_ppm_table->ulDGpuTDP;
232 ptr->dgpu_ulv_power
233 = atom_ppm_table->ulDGpuUlvPower;
234 ptr->tj_max
235 = atom_ppm_table->ulTjmax;
236
237 pp_table_information->ppm_parameter_table = ptr;
238
239 return 0;
240 }
241
242 /**
243 * Private Function used during initialization.
244 * Initialize TDP limits for DPM2
245 * @param hwmgr Pointer to the hardware manager.
246 * @param powerplay_table Pointer to the PowerPlay Table.
247 */
init_dpm_2_parameters(struct pp_hwmgr * hwmgr,const ATOM_Tonga_POWERPLAYTABLE * powerplay_table)248 static int init_dpm_2_parameters(
249 struct pp_hwmgr *hwmgr,
250 const ATOM_Tonga_POWERPLAYTABLE *powerplay_table
251 )
252 {
253 int result = 0;
254 struct phm_ppt_v1_information *pp_table_information = (struct phm_ppt_v1_information *)(hwmgr->pptable);
255 ATOM_Tonga_PPM_Table *atom_ppm_table;
256 uint32_t disable_ppm = 0;
257 uint32_t disable_power_control = 0;
258
259 pp_table_information->us_ulv_voltage_offset =
260 le16_to_cpu(powerplay_table->usUlvVoltageOffset);
261
262 pp_table_information->ppm_parameter_table = NULL;
263 pp_table_information->vddc_lookup_table = NULL;
264 pp_table_information->vddgfx_lookup_table = NULL;
265 /* TDP limits */
266 hwmgr->platform_descriptor.TDPODLimit =
267 le16_to_cpu(powerplay_table->usPowerControlLimit);
268 hwmgr->platform_descriptor.TDPAdjustment = 0;
269 hwmgr->platform_descriptor.VidAdjustment = 0;
270 hwmgr->platform_descriptor.VidAdjustmentPolarity = 0;
271 hwmgr->platform_descriptor.VidMinLimit = 0;
272 hwmgr->platform_descriptor.VidMaxLimit = 1500000;
273 hwmgr->platform_descriptor.VidStep = 6250;
274
275 disable_power_control = 0;
276 if (0 == disable_power_control) {
277 /* enable TDP overdrive (PowerControl) feature as well if supported */
278 if (hwmgr->platform_descriptor.TDPODLimit != 0)
279 phm_cap_set(hwmgr->platform_descriptor.platformCaps,
280 PHM_PlatformCaps_PowerControl);
281 }
282
283 if (0 != powerplay_table->usVddcLookupTableOffset) {
284 const ATOM_Tonga_Voltage_Lookup_Table *pVddcCACTable =
285 (ATOM_Tonga_Voltage_Lookup_Table *)(((unsigned long)powerplay_table) +
286 le16_to_cpu(powerplay_table->usVddcLookupTableOffset));
287
288 result = get_vddc_lookup_table(hwmgr,
289 &pp_table_information->vddc_lookup_table, pVddcCACTable, 16);
290 }
291
292 if (0 != powerplay_table->usVddgfxLookupTableOffset) {
293 const ATOM_Tonga_Voltage_Lookup_Table *pVddgfxCACTable =
294 (ATOM_Tonga_Voltage_Lookup_Table *)(((unsigned long)powerplay_table) +
295 le16_to_cpu(powerplay_table->usVddgfxLookupTableOffset));
296
297 result = get_vddc_lookup_table(hwmgr,
298 &pp_table_information->vddgfx_lookup_table, pVddgfxCACTable, 16);
299 }
300
301 disable_ppm = 0;
302 if (0 == disable_ppm) {
303 atom_ppm_table = (ATOM_Tonga_PPM_Table *)
304 (((unsigned long)powerplay_table) + le16_to_cpu(powerplay_table->usPPMTableOffset));
305
306 if (0 != powerplay_table->usPPMTableOffset) {
307 if (get_platform_power_management_table(hwmgr, atom_ppm_table) == 0) {
308 phm_cap_set(hwmgr->platform_descriptor.platformCaps,
309 PHM_PlatformCaps_EnablePlatformPowerManagement);
310 }
311 }
312 }
313
314 return result;
315 }
316
get_valid_clk(struct pp_hwmgr * hwmgr,struct phm_clock_array ** clk_table,phm_ppt_v1_clock_voltage_dependency_table const * clk_volt_pp_table)317 static int get_valid_clk(
318 struct pp_hwmgr *hwmgr,
319 struct phm_clock_array **clk_table,
320 phm_ppt_v1_clock_voltage_dependency_table const *clk_volt_pp_table
321 )
322 {
323 uint32_t table_size, i;
324 struct phm_clock_array *table;
325 phm_ppt_v1_clock_voltage_dependency_record *dep_record;
326
327 PP_ASSERT_WITH_CODE((0 != clk_volt_pp_table->count),
328 "Invalid PowerPlay Table!", return -1);
329
330 table_size = sizeof(uint32_t) +
331 sizeof(uint32_t) * clk_volt_pp_table->count;
332
333 table = kzalloc(table_size, GFP_KERNEL);
334
335 if (NULL == table)
336 return -ENOMEM;
337
338 memset(table, 0x00, table_size);
339
340 table->count = (uint32_t)clk_volt_pp_table->count;
341
342 for (i = 0; i < table->count; i++) {
343 dep_record = GET_FLEXIBLE_ARRAY_MEMBER_ADDR(
344 phm_ppt_v1_clock_voltage_dependency_record,
345 entries, clk_volt_pp_table, i);
346 table->values[i] = (uint32_t)dep_record->clk;
347 }
348 *clk_table = table;
349
350 return 0;
351 }
352
get_hard_limits(struct pp_hwmgr * hwmgr,struct phm_clock_and_voltage_limits * limits,ATOM_Tonga_Hard_Limit_Table const * limitable)353 static int get_hard_limits(
354 struct pp_hwmgr *hwmgr,
355 struct phm_clock_and_voltage_limits *limits,
356 ATOM_Tonga_Hard_Limit_Table const *limitable
357 )
358 {
359 PP_ASSERT_WITH_CODE((0 != limitable->ucNumEntries), "Invalid PowerPlay Table!", return -1);
360
361 /* currently we always take entries[0] parameters */
362 limits->sclk = (uint32_t)limitable->entries[0].ulSCLKLimit;
363 limits->mclk = (uint32_t)limitable->entries[0].ulMCLKLimit;
364 limits->vddc = (uint16_t)limitable->entries[0].usVddcLimit;
365 limits->vddci = (uint16_t)limitable->entries[0].usVddciLimit;
366 limits->vddgfx = (uint16_t)limitable->entries[0].usVddgfxLimit;
367
368 return 0;
369 }
370
get_mclk_voltage_dependency_table(struct pp_hwmgr * hwmgr,phm_ppt_v1_clock_voltage_dependency_table ** pp_tonga_mclk_dep_table,ATOM_Tonga_MCLK_Dependency_Table const * mclk_dep_table)371 static int get_mclk_voltage_dependency_table(
372 struct pp_hwmgr *hwmgr,
373 phm_ppt_v1_clock_voltage_dependency_table **pp_tonga_mclk_dep_table,
374 ATOM_Tonga_MCLK_Dependency_Table const *mclk_dep_table
375 )
376 {
377 uint32_t table_size, i;
378 phm_ppt_v1_clock_voltage_dependency_table *mclk_table;
379 phm_ppt_v1_clock_voltage_dependency_record *mclk_table_record;
380 ATOM_Tonga_MCLK_Dependency_Record *mclk_dep_record;
381
382 PP_ASSERT_WITH_CODE((0 != mclk_dep_table->ucNumEntries),
383 "Invalid PowerPlay Table!", return -1);
384
385 table_size = sizeof(uint32_t) + sizeof(phm_ppt_v1_clock_voltage_dependency_record)
386 * mclk_dep_table->ucNumEntries;
387
388 mclk_table = kzalloc(table_size, GFP_KERNEL);
389
390 if (NULL == mclk_table)
391 return -ENOMEM;
392
393 memset(mclk_table, 0x00, table_size);
394
395 mclk_table->count = (uint32_t)mclk_dep_table->ucNumEntries;
396
397 for (i = 0; i < mclk_dep_table->ucNumEntries; i++) {
398 mclk_table_record = GET_FLEXIBLE_ARRAY_MEMBER_ADDR(
399 phm_ppt_v1_clock_voltage_dependency_record,
400 entries, mclk_table, i);
401 mclk_dep_record = GET_FLEXIBLE_ARRAY_MEMBER_ADDR(
402 ATOM_Tonga_MCLK_Dependency_Record,
403 entries, mclk_dep_table, i);
404 mclk_table_record->vddInd = mclk_dep_record->ucVddcInd;
405 mclk_table_record->vdd_offset = mclk_dep_record->usVddgfxOffset;
406 mclk_table_record->vddci = mclk_dep_record->usVddci;
407 mclk_table_record->mvdd = mclk_dep_record->usMvdd;
408 mclk_table_record->clk = mclk_dep_record->ulMclk;
409 }
410
411 *pp_tonga_mclk_dep_table = mclk_table;
412
413 return 0;
414 }
415
get_sclk_voltage_dependency_table(struct pp_hwmgr * hwmgr,phm_ppt_v1_clock_voltage_dependency_table ** pp_tonga_sclk_dep_table,PPTable_Generic_SubTable_Header const * sclk_dep_table)416 static int get_sclk_voltage_dependency_table(
417 struct pp_hwmgr *hwmgr,
418 phm_ppt_v1_clock_voltage_dependency_table **pp_tonga_sclk_dep_table,
419 PPTable_Generic_SubTable_Header const *sclk_dep_table
420 )
421 {
422 uint32_t table_size, i;
423 phm_ppt_v1_clock_voltage_dependency_table *sclk_table;
424 phm_ppt_v1_clock_voltage_dependency_record *sclk_table_record;
425
426 if (sclk_dep_table->ucRevId < 1) {
427 const ATOM_Tonga_SCLK_Dependency_Table *tonga_table =
428 (ATOM_Tonga_SCLK_Dependency_Table *)sclk_dep_table;
429 ATOM_Tonga_SCLK_Dependency_Record *sclk_dep_record;
430
431 PP_ASSERT_WITH_CODE((0 != tonga_table->ucNumEntries),
432 "Invalid PowerPlay Table!", return -1);
433
434 table_size = sizeof(uint32_t) + sizeof(phm_ppt_v1_clock_voltage_dependency_record)
435 * tonga_table->ucNumEntries;
436
437 sclk_table = kzalloc(table_size, GFP_KERNEL);
438
439 if (NULL == sclk_table)
440 return -ENOMEM;
441
442 memset(sclk_table, 0x00, table_size);
443
444 sclk_table->count = (uint32_t)tonga_table->ucNumEntries;
445
446 for (i = 0; i < tonga_table->ucNumEntries; i++) {
447 sclk_dep_record = GET_FLEXIBLE_ARRAY_MEMBER_ADDR(
448 ATOM_Tonga_SCLK_Dependency_Record,
449 entries, tonga_table, i);
450 sclk_table_record = GET_FLEXIBLE_ARRAY_MEMBER_ADDR(
451 phm_ppt_v1_clock_voltage_dependency_record,
452 entries, sclk_table, i);
453 sclk_table_record->vddInd = sclk_dep_record->ucVddInd;
454 sclk_table_record->vdd_offset = sclk_dep_record->usVddcOffset;
455 sclk_table_record->clk = sclk_dep_record->ulSclk;
456 sclk_table_record->cks_enable =
457 (((sclk_dep_record->ucCKSVOffsetandDisable & 0x80) >> 7) == 0) ? 1 : 0;
458 sclk_table_record->cks_voffset = (sclk_dep_record->ucCKSVOffsetandDisable & 0x7F);
459 }
460 } else {
461 const ATOM_Polaris_SCLK_Dependency_Table *polaris_table =
462 (ATOM_Polaris_SCLK_Dependency_Table *)sclk_dep_table;
463 ATOM_Polaris_SCLK_Dependency_Record *sclk_dep_record;
464
465 PP_ASSERT_WITH_CODE((0 != polaris_table->ucNumEntries),
466 "Invalid PowerPlay Table!", return -1);
467
468 table_size = sizeof(uint32_t) + sizeof(phm_ppt_v1_clock_voltage_dependency_record)
469 * polaris_table->ucNumEntries;
470
471 sclk_table = kzalloc(table_size, GFP_KERNEL);
472
473 if (NULL == sclk_table)
474 return -ENOMEM;
475
476 memset(sclk_table, 0x00, table_size);
477
478 sclk_table->count = (uint32_t)polaris_table->ucNumEntries;
479
480 for (i = 0; i < polaris_table->ucNumEntries; i++) {
481 sclk_dep_record = GET_FLEXIBLE_ARRAY_MEMBER_ADDR(
482 ATOM_Polaris_SCLK_Dependency_Record,
483 entries, polaris_table, i);
484 sclk_table_record = GET_FLEXIBLE_ARRAY_MEMBER_ADDR(
485 phm_ppt_v1_clock_voltage_dependency_record,
486 entries, sclk_table, i);
487 sclk_table_record->vddInd = sclk_dep_record->ucVddInd;
488 sclk_table_record->vdd_offset = sclk_dep_record->usVddcOffset;
489 sclk_table_record->clk = sclk_dep_record->ulSclk;
490 sclk_table_record->cks_enable =
491 (((sclk_dep_record->ucCKSVOffsetandDisable & 0x80) >> 7) == 0) ? 1 : 0;
492 sclk_table_record->cks_voffset = (sclk_dep_record->ucCKSVOffsetandDisable & 0x7F);
493 sclk_table_record->sclk_offset = sclk_dep_record->ulSclkOffset;
494 }
495 }
496 *pp_tonga_sclk_dep_table = sclk_table;
497
498 return 0;
499 }
500
get_pcie_table(struct pp_hwmgr * hwmgr,phm_ppt_v1_pcie_table ** pp_tonga_pcie_table,PPTable_Generic_SubTable_Header const * ptable)501 static int get_pcie_table(
502 struct pp_hwmgr *hwmgr,
503 phm_ppt_v1_pcie_table **pp_tonga_pcie_table,
504 PPTable_Generic_SubTable_Header const *ptable
505 )
506 {
507 uint32_t table_size, i, pcie_count;
508 phm_ppt_v1_pcie_table *pcie_table;
509 struct phm_ppt_v1_information *pp_table_information =
510 (struct phm_ppt_v1_information *)(hwmgr->pptable);
511 phm_ppt_v1_pcie_record *pcie_record;
512
513 if (ptable->ucRevId < 1) {
514 const ATOM_Tonga_PCIE_Table *atom_pcie_table = (ATOM_Tonga_PCIE_Table *)ptable;
515 ATOM_Tonga_PCIE_Record *atom_pcie_record;
516
517 PP_ASSERT_WITH_CODE((atom_pcie_table->ucNumEntries != 0),
518 "Invalid PowerPlay Table!", return -1);
519
520 table_size = sizeof(uint32_t) +
521 sizeof(phm_ppt_v1_pcie_record) * atom_pcie_table->ucNumEntries;
522
523 pcie_table = kzalloc(table_size, GFP_KERNEL);
524
525 if (pcie_table == NULL)
526 return -ENOMEM;
527
528 memset(pcie_table, 0x00, table_size);
529
530 /*
531 * Make sure the number of pcie entries are less than or equal to sclk dpm levels.
532 * Since first PCIE entry is for ULV, #pcie has to be <= SclkLevel + 1.
533 */
534 pcie_count = (pp_table_information->vdd_dep_on_sclk->count) + 1;
535 if ((uint32_t)atom_pcie_table->ucNumEntries <= pcie_count)
536 pcie_count = (uint32_t)atom_pcie_table->ucNumEntries;
537 else
538 pr_err("Number of Pcie Entries exceed the number of SCLK Dpm Levels! \
539 Disregarding the excess entries... \n");
540
541 pcie_table->count = pcie_count;
542 for (i = 0; i < pcie_count; i++) {
543 pcie_record = GET_FLEXIBLE_ARRAY_MEMBER_ADDR(
544 phm_ppt_v1_pcie_record,
545 entries, pcie_table, i);
546 atom_pcie_record = GET_FLEXIBLE_ARRAY_MEMBER_ADDR(
547 ATOM_Tonga_PCIE_Record,
548 entries, atom_pcie_table, i);
549 pcie_record->gen_speed = atom_pcie_record->ucPCIEGenSpeed;
550 pcie_record->lane_width = atom_pcie_record->usPCIELaneWidth;
551 }
552
553 *pp_tonga_pcie_table = pcie_table;
554 } else {
555 /* Polaris10/Polaris11 and newer. */
556 const ATOM_Polaris10_PCIE_Table *atom_pcie_table = (ATOM_Polaris10_PCIE_Table *)ptable;
557 ATOM_Polaris10_PCIE_Record *atom_pcie_record;
558
559 PP_ASSERT_WITH_CODE((atom_pcie_table->ucNumEntries != 0),
560 "Invalid PowerPlay Table!", return -1);
561
562 table_size = sizeof(uint32_t) +
563 sizeof(phm_ppt_v1_pcie_record) * atom_pcie_table->ucNumEntries;
564
565 pcie_table = kzalloc(table_size, GFP_KERNEL);
566
567 if (pcie_table == NULL)
568 return -ENOMEM;
569
570 memset(pcie_table, 0x00, table_size);
571
572 /*
573 * Make sure the number of pcie entries are less than or equal to sclk dpm levels.
574 * Since first PCIE entry is for ULV, #pcie has to be <= SclkLevel + 1.
575 */
576 pcie_count = (pp_table_information->vdd_dep_on_sclk->count) + 1;
577 if ((uint32_t)atom_pcie_table->ucNumEntries <= pcie_count)
578 pcie_count = (uint32_t)atom_pcie_table->ucNumEntries;
579 else
580 pr_err("Number of Pcie Entries exceed the number of SCLK Dpm Levels! \
581 Disregarding the excess entries... \n");
582
583 pcie_table->count = pcie_count;
584
585 for (i = 0; i < pcie_count; i++) {
586 pcie_record = GET_FLEXIBLE_ARRAY_MEMBER_ADDR(
587 phm_ppt_v1_pcie_record,
588 entries, pcie_table, i);
589 atom_pcie_record = GET_FLEXIBLE_ARRAY_MEMBER_ADDR(
590 ATOM_Polaris10_PCIE_Record,
591 entries, atom_pcie_table, i);
592 pcie_record->gen_speed = atom_pcie_record->ucPCIEGenSpeed;
593 pcie_record->lane_width = atom_pcie_record->usPCIELaneWidth;
594 pcie_record->pcie_sclk = atom_pcie_record->ulPCIE_Sclk;
595 }
596
597 *pp_tonga_pcie_table = pcie_table;
598 }
599
600 return 0;
601 }
602
get_cac_tdp_table(struct pp_hwmgr * hwmgr,struct phm_cac_tdp_table ** cac_tdp_table,const PPTable_Generic_SubTable_Header * table)603 static int get_cac_tdp_table(
604 struct pp_hwmgr *hwmgr,
605 struct phm_cac_tdp_table **cac_tdp_table,
606 const PPTable_Generic_SubTable_Header * table
607 )
608 {
609 uint32_t table_size;
610 struct phm_cac_tdp_table *tdp_table;
611
612 table_size = sizeof(uint32_t) + sizeof(struct phm_cac_tdp_table);
613 tdp_table = kzalloc(table_size, GFP_KERNEL);
614
615 if (NULL == tdp_table)
616 return -ENOMEM;
617
618 memset(tdp_table, 0x00, table_size);
619
620 hwmgr->dyn_state.cac_dtp_table = kzalloc(table_size, GFP_KERNEL);
621
622 if (NULL == hwmgr->dyn_state.cac_dtp_table) {
623 kfree(tdp_table);
624 return -ENOMEM;
625 }
626
627 memset(hwmgr->dyn_state.cac_dtp_table, 0x00, table_size);
628
629 if (table->ucRevId < 3) {
630 const ATOM_Tonga_PowerTune_Table *tonga_table =
631 (ATOM_Tonga_PowerTune_Table *)table;
632 tdp_table->usTDP = tonga_table->usTDP;
633 tdp_table->usConfigurableTDP =
634 tonga_table->usConfigurableTDP;
635 tdp_table->usTDC = tonga_table->usTDC;
636 tdp_table->usBatteryPowerLimit =
637 tonga_table->usBatteryPowerLimit;
638 tdp_table->usSmallPowerLimit =
639 tonga_table->usSmallPowerLimit;
640 tdp_table->usLowCACLeakage =
641 tonga_table->usLowCACLeakage;
642 tdp_table->usHighCACLeakage =
643 tonga_table->usHighCACLeakage;
644 tdp_table->usMaximumPowerDeliveryLimit =
645 tonga_table->usMaximumPowerDeliveryLimit;
646 tdp_table->usDefaultTargetOperatingTemp =
647 tonga_table->usTjMax;
648 tdp_table->usTargetOperatingTemp =
649 tonga_table->usTjMax; /*Set the initial temp to the same as default */
650 tdp_table->usPowerTuneDataSetID =
651 tonga_table->usPowerTuneDataSetID;
652 tdp_table->usSoftwareShutdownTemp =
653 tonga_table->usSoftwareShutdownTemp;
654 tdp_table->usClockStretchAmount =
655 tonga_table->usClockStretchAmount;
656 } else { /* Fiji and newer */
657 const ATOM_Fiji_PowerTune_Table *fijitable =
658 (ATOM_Fiji_PowerTune_Table *)table;
659 tdp_table->usTDP = fijitable->usTDP;
660 tdp_table->usConfigurableTDP = fijitable->usConfigurableTDP;
661 tdp_table->usTDC = fijitable->usTDC;
662 tdp_table->usBatteryPowerLimit = fijitable->usBatteryPowerLimit;
663 tdp_table->usSmallPowerLimit = fijitable->usSmallPowerLimit;
664 tdp_table->usLowCACLeakage = fijitable->usLowCACLeakage;
665 tdp_table->usHighCACLeakage = fijitable->usHighCACLeakage;
666 tdp_table->usMaximumPowerDeliveryLimit =
667 fijitable->usMaximumPowerDeliveryLimit;
668 tdp_table->usDefaultTargetOperatingTemp =
669 fijitable->usTjMax;
670 tdp_table->usTargetOperatingTemp =
671 fijitable->usTjMax; /*Set the initial temp to the same as default */
672 tdp_table->usPowerTuneDataSetID =
673 fijitable->usPowerTuneDataSetID;
674 tdp_table->usSoftwareShutdownTemp =
675 fijitable->usSoftwareShutdownTemp;
676 tdp_table->usClockStretchAmount =
677 fijitable->usClockStretchAmount;
678 tdp_table->usTemperatureLimitHotspot =
679 fijitable->usTemperatureLimitHotspot;
680 tdp_table->usTemperatureLimitLiquid1 =
681 fijitable->usTemperatureLimitLiquid1;
682 tdp_table->usTemperatureLimitLiquid2 =
683 fijitable->usTemperatureLimitLiquid2;
684 tdp_table->usTemperatureLimitVrVddc =
685 fijitable->usTemperatureLimitVrVddc;
686 tdp_table->usTemperatureLimitVrMvdd =
687 fijitable->usTemperatureLimitVrMvdd;
688 tdp_table->usTemperatureLimitPlx =
689 fijitable->usTemperatureLimitPlx;
690 tdp_table->ucLiquid1_I2C_address =
691 fijitable->ucLiquid1_I2C_address;
692 tdp_table->ucLiquid2_I2C_address =
693 fijitable->ucLiquid2_I2C_address;
694 tdp_table->ucLiquid_I2C_Line =
695 fijitable->ucLiquid_I2C_Line;
696 tdp_table->ucVr_I2C_address = fijitable->ucVr_I2C_address;
697 tdp_table->ucVr_I2C_Line = fijitable->ucVr_I2C_Line;
698 tdp_table->ucPlx_I2C_address = fijitable->ucPlx_I2C_address;
699 tdp_table->ucPlx_I2C_Line = fijitable->ucPlx_I2C_Line;
700 }
701
702 *cac_tdp_table = tdp_table;
703
704 return 0;
705 }
706
get_mm_clock_voltage_table(struct pp_hwmgr * hwmgr,phm_ppt_v1_mm_clock_voltage_dependency_table ** tonga_mm_table,const ATOM_Tonga_MM_Dependency_Table * mm_dependency_table)707 static int get_mm_clock_voltage_table(
708 struct pp_hwmgr *hwmgr,
709 phm_ppt_v1_mm_clock_voltage_dependency_table **tonga_mm_table,
710 const ATOM_Tonga_MM_Dependency_Table * mm_dependency_table
711 )
712 {
713 uint32_t table_size, i;
714 const ATOM_Tonga_MM_Dependency_Record *mm_dependency_record;
715 phm_ppt_v1_mm_clock_voltage_dependency_table *mm_table;
716 phm_ppt_v1_mm_clock_voltage_dependency_record *mm_table_record;
717
718 PP_ASSERT_WITH_CODE((0 != mm_dependency_table->ucNumEntries),
719 "Invalid PowerPlay Table!", return -1);
720 table_size = sizeof(uint32_t) +
721 sizeof(phm_ppt_v1_mm_clock_voltage_dependency_record)
722 * mm_dependency_table->ucNumEntries;
723 mm_table = kzalloc(table_size, GFP_KERNEL);
724
725 if (NULL == mm_table)
726 return -ENOMEM;
727
728 memset(mm_table, 0x00, table_size);
729
730 mm_table->count = mm_dependency_table->ucNumEntries;
731
732 for (i = 0; i < mm_dependency_table->ucNumEntries; i++) {
733 mm_dependency_record = GET_FLEXIBLE_ARRAY_MEMBER_ADDR(
734 ATOM_Tonga_MM_Dependency_Record,
735 entries, mm_dependency_table, i);
736 mm_table_record = GET_FLEXIBLE_ARRAY_MEMBER_ADDR(
737 phm_ppt_v1_mm_clock_voltage_dependency_record,
738 entries, mm_table, i);
739 mm_table_record->vddcInd = mm_dependency_record->ucVddcInd;
740 mm_table_record->vddgfx_offset = mm_dependency_record->usVddgfxOffset;
741 mm_table_record->aclk = mm_dependency_record->ulAClk;
742 mm_table_record->samclock = mm_dependency_record->ulSAMUClk;
743 mm_table_record->eclk = mm_dependency_record->ulEClk;
744 mm_table_record->vclk = mm_dependency_record->ulVClk;
745 mm_table_record->dclk = mm_dependency_record->ulDClk;
746 }
747
748 *tonga_mm_table = mm_table;
749
750 return 0;
751 }
752
753 /**
754 * Private Function used during initialization.
755 * Initialize clock voltage dependency
756 * @param hwmgr Pointer to the hardware manager.
757 * @param powerplay_table Pointer to the PowerPlay Table.
758 */
init_clock_voltage_dependency(struct pp_hwmgr * hwmgr,const ATOM_Tonga_POWERPLAYTABLE * powerplay_table)759 static int init_clock_voltage_dependency(
760 struct pp_hwmgr *hwmgr,
761 const ATOM_Tonga_POWERPLAYTABLE *powerplay_table
762 )
763 {
764 int result = 0;
765 struct phm_ppt_v1_information *pp_table_information =
766 (struct phm_ppt_v1_information *)(hwmgr->pptable);
767
768 const ATOM_Tonga_MM_Dependency_Table *mm_dependency_table =
769 (const ATOM_Tonga_MM_Dependency_Table *)(((unsigned long) powerplay_table) +
770 le16_to_cpu(powerplay_table->usMMDependencyTableOffset));
771 const PPTable_Generic_SubTable_Header *pPowerTuneTable =
772 (const PPTable_Generic_SubTable_Header *)(((unsigned long) powerplay_table) +
773 le16_to_cpu(powerplay_table->usPowerTuneTableOffset));
774 const ATOM_Tonga_MCLK_Dependency_Table *mclk_dep_table =
775 (const ATOM_Tonga_MCLK_Dependency_Table *)(((unsigned long) powerplay_table) +
776 le16_to_cpu(powerplay_table->usMclkDependencyTableOffset));
777 const PPTable_Generic_SubTable_Header *sclk_dep_table =
778 (const PPTable_Generic_SubTable_Header *)(((unsigned long) powerplay_table) +
779 le16_to_cpu(powerplay_table->usSclkDependencyTableOffset));
780 const ATOM_Tonga_Hard_Limit_Table *pHardLimits =
781 (const ATOM_Tonga_Hard_Limit_Table *)(((unsigned long) powerplay_table) +
782 le16_to_cpu(powerplay_table->usHardLimitTableOffset));
783 const PPTable_Generic_SubTable_Header *pcie_table =
784 (const PPTable_Generic_SubTable_Header *)(((unsigned long) powerplay_table) +
785 le16_to_cpu(powerplay_table->usPCIETableOffset));
786
787 pp_table_information->vdd_dep_on_sclk = NULL;
788 pp_table_information->vdd_dep_on_mclk = NULL;
789 pp_table_information->mm_dep_table = NULL;
790 pp_table_information->pcie_table = NULL;
791
792 if (powerplay_table->usMMDependencyTableOffset != 0)
793 result = get_mm_clock_voltage_table(hwmgr,
794 &pp_table_information->mm_dep_table, mm_dependency_table);
795
796 if (result == 0 && powerplay_table->usPowerTuneTableOffset != 0)
797 result = get_cac_tdp_table(hwmgr,
798 &pp_table_information->cac_dtp_table, pPowerTuneTable);
799
800 if (result == 0 && powerplay_table->usSclkDependencyTableOffset != 0)
801 result = get_sclk_voltage_dependency_table(hwmgr,
802 &pp_table_information->vdd_dep_on_sclk, sclk_dep_table);
803
804 if (result == 0 && powerplay_table->usMclkDependencyTableOffset != 0)
805 result = get_mclk_voltage_dependency_table(hwmgr,
806 &pp_table_information->vdd_dep_on_mclk, mclk_dep_table);
807
808 if (result == 0 && powerplay_table->usPCIETableOffset != 0)
809 result = get_pcie_table(hwmgr,
810 &pp_table_information->pcie_table, pcie_table);
811
812 if (result == 0 && powerplay_table->usHardLimitTableOffset != 0)
813 result = get_hard_limits(hwmgr,
814 &pp_table_information->max_clock_voltage_on_dc, pHardLimits);
815
816 hwmgr->dyn_state.max_clock_voltage_on_dc.sclk =
817 pp_table_information->max_clock_voltage_on_dc.sclk;
818 hwmgr->dyn_state.max_clock_voltage_on_dc.mclk =
819 pp_table_information->max_clock_voltage_on_dc.mclk;
820 hwmgr->dyn_state.max_clock_voltage_on_dc.vddc =
821 pp_table_information->max_clock_voltage_on_dc.vddc;
822 hwmgr->dyn_state.max_clock_voltage_on_dc.vddci =
823 pp_table_information->max_clock_voltage_on_dc.vddci;
824
825 if (result == 0 && (NULL != pp_table_information->vdd_dep_on_mclk)
826 && (0 != pp_table_information->vdd_dep_on_mclk->count))
827 result = get_valid_clk(hwmgr, &pp_table_information->valid_mclk_values,
828 pp_table_information->vdd_dep_on_mclk);
829
830 if (result == 0 && (NULL != pp_table_information->vdd_dep_on_sclk)
831 && (0 != pp_table_information->vdd_dep_on_sclk->count))
832 result = get_valid_clk(hwmgr, &pp_table_information->valid_sclk_values,
833 pp_table_information->vdd_dep_on_sclk);
834
835 return result;
836 }
837
838 /** Retrieves the (signed) Overdrive limits from VBIOS.
839 * The max engine clock, memory clock and max temperature come from the firmware info table.
840 *
841 * The information is placed into the platform descriptor.
842 *
843 * @param hwmgr source of the VBIOS table and owner of the platform descriptor to be updated.
844 * @param powerplay_table the address of the PowerPlay table.
845 *
846 * @return 1 as long as the firmware info table was present and of a supported version.
847 */
init_over_drive_limits(struct pp_hwmgr * hwmgr,const ATOM_Tonga_POWERPLAYTABLE * powerplay_table)848 static int init_over_drive_limits(
849 struct pp_hwmgr *hwmgr,
850 const ATOM_Tonga_POWERPLAYTABLE *powerplay_table)
851 {
852 hwmgr->platform_descriptor.overdriveLimit.engineClock =
853 le32_to_cpu(powerplay_table->ulMaxODEngineClock);
854 hwmgr->platform_descriptor.overdriveLimit.memoryClock =
855 le32_to_cpu(powerplay_table->ulMaxODMemoryClock);
856
857 hwmgr->platform_descriptor.minOverdriveVDDC = 0;
858 hwmgr->platform_descriptor.maxOverdriveVDDC = 0;
859 hwmgr->platform_descriptor.overdriveVDDCStep = 0;
860
861 if (hwmgr->platform_descriptor.overdriveLimit.engineClock > 0 \
862 && hwmgr->platform_descriptor.overdriveLimit.memoryClock > 0) {
863 phm_cap_set(hwmgr->platform_descriptor.platformCaps,
864 PHM_PlatformCaps_ACOverdriveSupport);
865 }
866
867 return 0;
868 }
869
870 /**
871 * Private Function used during initialization.
872 * Inspect the PowerPlay table for obvious signs of corruption.
873 * @param hwmgr Pointer to the hardware manager.
874 * @param powerplay_table Pointer to the PowerPlay Table.
875 * @exception This implementation always returns 1.
876 */
init_thermal_controller(struct pp_hwmgr * hwmgr,const ATOM_Tonga_POWERPLAYTABLE * powerplay_table)877 static int init_thermal_controller(
878 struct pp_hwmgr *hwmgr,
879 const ATOM_Tonga_POWERPLAYTABLE *powerplay_table
880 )
881 {
882 const PPTable_Generic_SubTable_Header *fan_table;
883 ATOM_Tonga_Thermal_Controller *thermal_controller;
884
885 thermal_controller = (ATOM_Tonga_Thermal_Controller *)
886 (((unsigned long)powerplay_table) +
887 le16_to_cpu(powerplay_table->usThermalControllerOffset));
888 PP_ASSERT_WITH_CODE((0 != powerplay_table->usThermalControllerOffset),
889 "Thermal controller table not set!", return -1);
890
891 hwmgr->thermal_controller.ucType = thermal_controller->ucType;
892 hwmgr->thermal_controller.ucI2cLine = thermal_controller->ucI2cLine;
893 hwmgr->thermal_controller.ucI2cAddress = thermal_controller->ucI2cAddress;
894
895 hwmgr->thermal_controller.fanInfo.bNoFan =
896 (0 != (thermal_controller->ucFanParameters & ATOM_TONGA_PP_FANPARAMETERS_NOFAN));
897
898 hwmgr->thermal_controller.fanInfo.ucTachometerPulsesPerRevolution =
899 thermal_controller->ucFanParameters &
900 ATOM_TONGA_PP_FANPARAMETERS_TACHOMETER_PULSES_PER_REVOLUTION_MASK;
901
902 hwmgr->thermal_controller.fanInfo.ulMinRPM
903 = thermal_controller->ucFanMinRPM * 100UL;
904 hwmgr->thermal_controller.fanInfo.ulMaxRPM
905 = thermal_controller->ucFanMaxRPM * 100UL;
906
907 set_hw_cap(
908 hwmgr,
909 ATOM_TONGA_PP_THERMALCONTROLLER_NONE != hwmgr->thermal_controller.ucType,
910 PHM_PlatformCaps_ThermalController
911 );
912
913 if (0 == powerplay_table->usFanTableOffset)
914 return 0;
915
916 fan_table = (const PPTable_Generic_SubTable_Header *)
917 (((unsigned long)powerplay_table) +
918 le16_to_cpu(powerplay_table->usFanTableOffset));
919
920 PP_ASSERT_WITH_CODE((0 != powerplay_table->usFanTableOffset),
921 "Fan table not set!", return -1);
922 PP_ASSERT_WITH_CODE((0 < fan_table->ucRevId),
923 "Unsupported fan table format!", return -1);
924
925 hwmgr->thermal_controller.advanceFanControlParameters.ulCycleDelay
926 = 100000;
927 phm_cap_set(hwmgr->platform_descriptor.platformCaps,
928 PHM_PlatformCaps_MicrocodeFanControl);
929
930 if (fan_table->ucRevId < 8) {
931 const ATOM_Tonga_Fan_Table *tonga_fan_table =
932 (ATOM_Tonga_Fan_Table *)fan_table;
933 hwmgr->thermal_controller.advanceFanControlParameters.ucTHyst
934 = tonga_fan_table->ucTHyst;
935 hwmgr->thermal_controller.advanceFanControlParameters.usTMin
936 = tonga_fan_table->usTMin;
937 hwmgr->thermal_controller.advanceFanControlParameters.usTMed
938 = tonga_fan_table->usTMed;
939 hwmgr->thermal_controller.advanceFanControlParameters.usTHigh
940 = tonga_fan_table->usTHigh;
941 hwmgr->thermal_controller.advanceFanControlParameters.usPWMMin
942 = tonga_fan_table->usPWMMin;
943 hwmgr->thermal_controller.advanceFanControlParameters.usPWMMed
944 = tonga_fan_table->usPWMMed;
945 hwmgr->thermal_controller.advanceFanControlParameters.usPWMHigh
946 = tonga_fan_table->usPWMHigh;
947 hwmgr->thermal_controller.advanceFanControlParameters.usTMax
948 = 10900; /* hard coded */
949 hwmgr->thermal_controller.advanceFanControlParameters.usTMax
950 = tonga_fan_table->usTMax;
951 hwmgr->thermal_controller.advanceFanControlParameters.ucFanControlMode
952 = tonga_fan_table->ucFanControlMode;
953 hwmgr->thermal_controller.advanceFanControlParameters.usDefaultMaxFanPWM
954 = tonga_fan_table->usFanPWMMax;
955 hwmgr->thermal_controller.advanceFanControlParameters.usDefaultFanOutputSensitivity
956 = 4836;
957 hwmgr->thermal_controller.advanceFanControlParameters.usFanOutputSensitivity
958 = tonga_fan_table->usFanOutputSensitivity;
959 hwmgr->thermal_controller.advanceFanControlParameters.usDefaultMaxFanRPM
960 = tonga_fan_table->usFanRPMMax;
961 hwmgr->thermal_controller.advanceFanControlParameters.ulMinFanSCLKAcousticLimit
962 = (tonga_fan_table->ulMinFanSCLKAcousticLimit / 100); /* PPTable stores it in 10Khz unit for 2 decimal places. SMC wants MHz. */
963 hwmgr->thermal_controller.advanceFanControlParameters.ucTargetTemperature
964 = tonga_fan_table->ucTargetTemperature;
965 hwmgr->thermal_controller.advanceFanControlParameters.ucMinimumPWMLimit
966 = tonga_fan_table->ucMinimumPWMLimit;
967 } else {
968 const ATOM_Fiji_Fan_Table *fiji_fan_table =
969 (ATOM_Fiji_Fan_Table *)fan_table;
970 hwmgr->thermal_controller.advanceFanControlParameters.ucTHyst
971 = fiji_fan_table->ucTHyst;
972 hwmgr->thermal_controller.advanceFanControlParameters.usTMin
973 = fiji_fan_table->usTMin;
974 hwmgr->thermal_controller.advanceFanControlParameters.usTMed
975 = fiji_fan_table->usTMed;
976 hwmgr->thermal_controller.advanceFanControlParameters.usTHigh
977 = fiji_fan_table->usTHigh;
978 hwmgr->thermal_controller.advanceFanControlParameters.usPWMMin
979 = fiji_fan_table->usPWMMin;
980 hwmgr->thermal_controller.advanceFanControlParameters.usPWMMed
981 = fiji_fan_table->usPWMMed;
982 hwmgr->thermal_controller.advanceFanControlParameters.usPWMHigh
983 = fiji_fan_table->usPWMHigh;
984 hwmgr->thermal_controller.advanceFanControlParameters.usTMax
985 = fiji_fan_table->usTMax;
986 hwmgr->thermal_controller.advanceFanControlParameters.ucFanControlMode
987 = fiji_fan_table->ucFanControlMode;
988 hwmgr->thermal_controller.advanceFanControlParameters.usDefaultMaxFanPWM
989 = fiji_fan_table->usFanPWMMax;
990 hwmgr->thermal_controller.advanceFanControlParameters.usDefaultFanOutputSensitivity
991 = 4836;
992 hwmgr->thermal_controller.advanceFanControlParameters.usFanOutputSensitivity
993 = fiji_fan_table->usFanOutputSensitivity;
994 hwmgr->thermal_controller.advanceFanControlParameters.usDefaultMaxFanRPM
995 = fiji_fan_table->usFanRPMMax;
996 hwmgr->thermal_controller.advanceFanControlParameters.ulMinFanSCLKAcousticLimit
997 = (fiji_fan_table->ulMinFanSCLKAcousticLimit / 100); /* PPTable stores it in 10Khz unit for 2 decimal places. SMC wants MHz. */
998 hwmgr->thermal_controller.advanceFanControlParameters.ucTargetTemperature
999 = fiji_fan_table->ucTargetTemperature;
1000 hwmgr->thermal_controller.advanceFanControlParameters.ucMinimumPWMLimit
1001 = fiji_fan_table->ucMinimumPWMLimit;
1002
1003 hwmgr->thermal_controller.advanceFanControlParameters.usFanGainEdge
1004 = fiji_fan_table->usFanGainEdge;
1005 hwmgr->thermal_controller.advanceFanControlParameters.usFanGainHotspot
1006 = fiji_fan_table->usFanGainHotspot;
1007 hwmgr->thermal_controller.advanceFanControlParameters.usFanGainLiquid
1008 = fiji_fan_table->usFanGainLiquid;
1009 hwmgr->thermal_controller.advanceFanControlParameters.usFanGainVrVddc
1010 = fiji_fan_table->usFanGainVrVddc;
1011 hwmgr->thermal_controller.advanceFanControlParameters.usFanGainVrMvdd
1012 = fiji_fan_table->usFanGainVrMvdd;
1013 hwmgr->thermal_controller.advanceFanControlParameters.usFanGainPlx
1014 = fiji_fan_table->usFanGainPlx;
1015 hwmgr->thermal_controller.advanceFanControlParameters.usFanGainHbm
1016 = fiji_fan_table->usFanGainHbm;
1017 }
1018
1019 return 0;
1020 }
1021
1022 /**
1023 * Private Function used during initialization.
1024 * Inspect the PowerPlay table for obvious signs of corruption.
1025 * @param hwmgr Pointer to the hardware manager.
1026 * @param powerplay_table Pointer to the PowerPlay Table.
1027 * @exception 2 if the powerplay table is incorrect.
1028 */
check_powerplay_tables(struct pp_hwmgr * hwmgr,const ATOM_Tonga_POWERPLAYTABLE * powerplay_table)1029 static int check_powerplay_tables(
1030 struct pp_hwmgr *hwmgr,
1031 const ATOM_Tonga_POWERPLAYTABLE *powerplay_table
1032 )
1033 {
1034 const ATOM_Tonga_State_Array *state_arrays;
1035
1036 state_arrays = (ATOM_Tonga_State_Array *)(((unsigned long)powerplay_table) +
1037 le16_to_cpu(powerplay_table->usStateArrayOffset));
1038
1039 PP_ASSERT_WITH_CODE((ATOM_Tonga_TABLE_REVISION_TONGA <=
1040 powerplay_table->sHeader.ucTableFormatRevision),
1041 "Unsupported PPTable format!", return -1);
1042 PP_ASSERT_WITH_CODE((0 != powerplay_table->usStateArrayOffset),
1043 "State table is not set!", return -1);
1044 PP_ASSERT_WITH_CODE((0 < powerplay_table->sHeader.usStructureSize),
1045 "Invalid PowerPlay Table!", return -1);
1046 PP_ASSERT_WITH_CODE((0 < state_arrays->ucNumEntries),
1047 "Invalid PowerPlay Table!", return -1);
1048
1049 return 0;
1050 }
1051
pp_tables_v1_0_initialize(struct pp_hwmgr * hwmgr)1052 static int pp_tables_v1_0_initialize(struct pp_hwmgr *hwmgr)
1053 {
1054 int result = 0;
1055 const ATOM_Tonga_POWERPLAYTABLE *powerplay_table;
1056
1057 hwmgr->pptable = kzalloc(sizeof(struct phm_ppt_v1_information), GFP_KERNEL);
1058
1059 PP_ASSERT_WITH_CODE((NULL != hwmgr->pptable),
1060 "Failed to allocate hwmgr->pptable!", return -ENOMEM);
1061
1062 memset(hwmgr->pptable, 0x00, sizeof(struct phm_ppt_v1_information));
1063
1064 powerplay_table = get_powerplay_table(hwmgr);
1065
1066 PP_ASSERT_WITH_CODE((NULL != powerplay_table),
1067 "Missing PowerPlay Table!", return -1);
1068
1069 result = check_powerplay_tables(hwmgr, powerplay_table);
1070
1071 PP_ASSERT_WITH_CODE((result == 0),
1072 "check_powerplay_tables failed", return result);
1073
1074 result = set_platform_caps(hwmgr,
1075 le32_to_cpu(powerplay_table->ulPlatformCaps));
1076
1077 PP_ASSERT_WITH_CODE((result == 0),
1078 "set_platform_caps failed", return result);
1079
1080 result = init_thermal_controller(hwmgr, powerplay_table);
1081
1082 PP_ASSERT_WITH_CODE((result == 0),
1083 "init_thermal_controller failed", return result);
1084
1085 result = init_over_drive_limits(hwmgr, powerplay_table);
1086
1087 PP_ASSERT_WITH_CODE((result == 0),
1088 "init_over_drive_limits failed", return result);
1089
1090 result = init_clock_voltage_dependency(hwmgr, powerplay_table);
1091
1092 PP_ASSERT_WITH_CODE((result == 0),
1093 "init_clock_voltage_dependency failed", return result);
1094
1095 result = init_dpm_2_parameters(hwmgr, powerplay_table);
1096
1097 PP_ASSERT_WITH_CODE((result == 0),
1098 "init_dpm_2_parameters failed", return result);
1099
1100 return result;
1101 }
1102
pp_tables_v1_0_uninitialize(struct pp_hwmgr * hwmgr)1103 static int pp_tables_v1_0_uninitialize(struct pp_hwmgr *hwmgr)
1104 {
1105 struct phm_ppt_v1_information *pp_table_information =
1106 (struct phm_ppt_v1_information *)(hwmgr->pptable);
1107
1108 kfree(pp_table_information->vdd_dep_on_sclk);
1109 pp_table_information->vdd_dep_on_sclk = NULL;
1110
1111 kfree(pp_table_information->vdd_dep_on_mclk);
1112 pp_table_information->vdd_dep_on_mclk = NULL;
1113
1114 kfree(pp_table_information->valid_mclk_values);
1115 pp_table_information->valid_mclk_values = NULL;
1116
1117 kfree(pp_table_information->valid_sclk_values);
1118 pp_table_information->valid_sclk_values = NULL;
1119
1120 kfree(pp_table_information->vddc_lookup_table);
1121 pp_table_information->vddc_lookup_table = NULL;
1122
1123 kfree(pp_table_information->vddgfx_lookup_table);
1124 pp_table_information->vddgfx_lookup_table = NULL;
1125
1126 kfree(pp_table_information->mm_dep_table);
1127 pp_table_information->mm_dep_table = NULL;
1128
1129 kfree(pp_table_information->cac_dtp_table);
1130 pp_table_information->cac_dtp_table = NULL;
1131
1132 kfree(hwmgr->dyn_state.cac_dtp_table);
1133 hwmgr->dyn_state.cac_dtp_table = NULL;
1134
1135 kfree(pp_table_information->ppm_parameter_table);
1136 pp_table_information->ppm_parameter_table = NULL;
1137
1138 kfree(pp_table_information->pcie_table);
1139 pp_table_information->pcie_table = NULL;
1140
1141 kfree(hwmgr->pptable);
1142 hwmgr->pptable = NULL;
1143
1144 return 0;
1145 }
1146
1147 const struct pp_table_func pptable_v1_0_funcs = {
1148 .pptable_init = pp_tables_v1_0_initialize,
1149 .pptable_fini = pp_tables_v1_0_uninitialize,
1150 };
1151
get_number_of_powerplay_table_entries_v1_0(struct pp_hwmgr * hwmgr)1152 int get_number_of_powerplay_table_entries_v1_0(struct pp_hwmgr *hwmgr)
1153 {
1154 ATOM_Tonga_State_Array const *state_arrays;
1155 const ATOM_Tonga_POWERPLAYTABLE *pp_table = get_powerplay_table(hwmgr);
1156
1157 PP_ASSERT_WITH_CODE((NULL != pp_table),
1158 "Missing PowerPlay Table!", return -1);
1159 PP_ASSERT_WITH_CODE((pp_table->sHeader.ucTableFormatRevision >=
1160 ATOM_Tonga_TABLE_REVISION_TONGA),
1161 "Incorrect PowerPlay table revision!", return -1);
1162
1163 state_arrays = (ATOM_Tonga_State_Array *)(((unsigned long)pp_table) +
1164 le16_to_cpu(pp_table->usStateArrayOffset));
1165
1166 return (uint32_t)(state_arrays->ucNumEntries);
1167 }
1168
1169 /**
1170 * Private function to convert flags stored in the BIOS to software flags in PowerPlay.
1171 */
make_classification_flags(struct pp_hwmgr * hwmgr,uint16_t classification,uint16_t classification2)1172 static uint32_t make_classification_flags(struct pp_hwmgr *hwmgr,
1173 uint16_t classification, uint16_t classification2)
1174 {
1175 uint32_t result = 0;
1176
1177 if (classification & ATOM_PPLIB_CLASSIFICATION_BOOT)
1178 result |= PP_StateClassificationFlag_Boot;
1179
1180 if (classification & ATOM_PPLIB_CLASSIFICATION_THERMAL)
1181 result |= PP_StateClassificationFlag_Thermal;
1182
1183 if (classification & ATOM_PPLIB_CLASSIFICATION_LIMITEDPOWERSOURCE)
1184 result |= PP_StateClassificationFlag_LimitedPowerSource;
1185
1186 if (classification & ATOM_PPLIB_CLASSIFICATION_REST)
1187 result |= PP_StateClassificationFlag_Rest;
1188
1189 if (classification & ATOM_PPLIB_CLASSIFICATION_FORCED)
1190 result |= PP_StateClassificationFlag_Forced;
1191
1192 if (classification & ATOM_PPLIB_CLASSIFICATION_ACPI)
1193 result |= PP_StateClassificationFlag_ACPI;
1194
1195 if (classification2 & ATOM_PPLIB_CLASSIFICATION2_LIMITEDPOWERSOURCE_2)
1196 result |= PP_StateClassificationFlag_LimitedPowerSource_2;
1197
1198 return result;
1199 }
1200
ppt_get_num_of_vce_state_table_entries_v1_0(struct pp_hwmgr * hwmgr)1201 static int ppt_get_num_of_vce_state_table_entries_v1_0(struct pp_hwmgr *hwmgr)
1202 {
1203 const ATOM_Tonga_POWERPLAYTABLE *pp_table = get_powerplay_table(hwmgr);
1204 const ATOM_Tonga_VCE_State_Table *vce_state_table;
1205
1206
1207 if (pp_table == NULL)
1208 return 0;
1209
1210 vce_state_table = (void *)pp_table +
1211 le16_to_cpu(pp_table->usVCEStateTableOffset);
1212
1213 return vce_state_table->ucNumEntries;
1214 }
1215
ppt_get_vce_state_table_entry_v1_0(struct pp_hwmgr * hwmgr,uint32_t i,struct amd_vce_state * vce_state,void ** clock_info,uint32_t * flag)1216 static int ppt_get_vce_state_table_entry_v1_0(struct pp_hwmgr *hwmgr, uint32_t i,
1217 struct amd_vce_state *vce_state, void **clock_info, uint32_t *flag)
1218 {
1219 const ATOM_Tonga_VCE_State_Record *vce_state_record;
1220 ATOM_Tonga_SCLK_Dependency_Record *sclk_dep_record;
1221 ATOM_Tonga_MCLK_Dependency_Record *mclk_dep_record;
1222 ATOM_Tonga_MM_Dependency_Record *mm_dep_record;
1223 const ATOM_Tonga_POWERPLAYTABLE *pptable = get_powerplay_table(hwmgr);
1224 const ATOM_Tonga_VCE_State_Table *vce_state_table = (ATOM_Tonga_VCE_State_Table *)(((unsigned long)pptable)
1225 + le16_to_cpu(pptable->usVCEStateTableOffset));
1226 const ATOM_Tonga_SCLK_Dependency_Table *sclk_dep_table = (ATOM_Tonga_SCLK_Dependency_Table *)(((unsigned long)pptable)
1227 + le16_to_cpu(pptable->usSclkDependencyTableOffset));
1228 const ATOM_Tonga_MCLK_Dependency_Table *mclk_dep_table = (ATOM_Tonga_MCLK_Dependency_Table *)(((unsigned long)pptable)
1229 + le16_to_cpu(pptable->usMclkDependencyTableOffset));
1230 const ATOM_Tonga_MM_Dependency_Table *mm_dep_table = (ATOM_Tonga_MM_Dependency_Table *)(((unsigned long)pptable)
1231 + le16_to_cpu(pptable->usMMDependencyTableOffset));
1232
1233 PP_ASSERT_WITH_CODE((i < vce_state_table->ucNumEntries),
1234 "Requested state entry ID is out of range!",
1235 return -EINVAL);
1236
1237 vce_state_record = GET_FLEXIBLE_ARRAY_MEMBER_ADDR(
1238 ATOM_Tonga_VCE_State_Record,
1239 entries, vce_state_table, i);
1240 sclk_dep_record = GET_FLEXIBLE_ARRAY_MEMBER_ADDR(
1241 ATOM_Tonga_SCLK_Dependency_Record,
1242 entries, sclk_dep_table,
1243 vce_state_record->ucSCLKIndex);
1244 mm_dep_record = GET_FLEXIBLE_ARRAY_MEMBER_ADDR(
1245 ATOM_Tonga_MM_Dependency_Record,
1246 entries, mm_dep_table,
1247 vce_state_record->ucVCEClockIndex);
1248 *flag = vce_state_record->ucFlag;
1249
1250 vce_state->evclk = mm_dep_record->ulEClk;
1251 vce_state->ecclk = mm_dep_record->ulEClk;
1252 vce_state->sclk = sclk_dep_record->ulSclk;
1253
1254 if (vce_state_record->ucMCLKIndex >= mclk_dep_table->ucNumEntries)
1255 mclk_dep_record = GET_FLEXIBLE_ARRAY_MEMBER_ADDR(
1256 ATOM_Tonga_MCLK_Dependency_Record,
1257 entries, mclk_dep_table,
1258 mclk_dep_table->ucNumEntries - 1);
1259 else
1260 mclk_dep_record = GET_FLEXIBLE_ARRAY_MEMBER_ADDR(
1261 ATOM_Tonga_MCLK_Dependency_Record,
1262 entries, mclk_dep_table,
1263 vce_state_record->ucMCLKIndex);
1264
1265 vce_state->mclk = mclk_dep_record->ulMclk;
1266 return 0;
1267 }
1268
1269 /**
1270 * Create a Power State out of an entry in the PowerPlay table.
1271 * This function is called by the hardware back-end.
1272 * @param hwmgr Pointer to the hardware manager.
1273 * @param entry_index The index of the entry to be extracted from the table.
1274 * @param power_state The address of the PowerState instance being created.
1275 * @return -1 if the entry cannot be retrieved.
1276 */
get_powerplay_table_entry_v1_0(struct pp_hwmgr * hwmgr,uint32_t entry_index,struct pp_power_state * power_state,int (* call_back_func)(struct pp_hwmgr *,void *,struct pp_power_state *,void *,uint32_t))1277 int get_powerplay_table_entry_v1_0(struct pp_hwmgr *hwmgr,
1278 uint32_t entry_index, struct pp_power_state *power_state,
1279 int (*call_back_func)(struct pp_hwmgr *, void *,
1280 struct pp_power_state *, void *, uint32_t))
1281 {
1282 int result = 0;
1283 const ATOM_Tonga_State_Array *state_arrays;
1284 const ATOM_Tonga_State *state_entry;
1285 const ATOM_Tonga_POWERPLAYTABLE *pp_table = get_powerplay_table(hwmgr);
1286 int i, j;
1287 uint32_t flags = 0;
1288
1289 PP_ASSERT_WITH_CODE((NULL != pp_table), "Missing PowerPlay Table!", return -1;);
1290 power_state->classification.bios_index = entry_index;
1291
1292 if (pp_table->sHeader.ucTableFormatRevision >=
1293 ATOM_Tonga_TABLE_REVISION_TONGA) {
1294 state_arrays = (ATOM_Tonga_State_Array *)(((unsigned long)pp_table) +
1295 le16_to_cpu(pp_table->usStateArrayOffset));
1296
1297 PP_ASSERT_WITH_CODE((0 < pp_table->usStateArrayOffset),
1298 "Invalid PowerPlay Table State Array Offset.", return -1);
1299 PP_ASSERT_WITH_CODE((0 < state_arrays->ucNumEntries),
1300 "Invalid PowerPlay Table State Array.", return -1);
1301 PP_ASSERT_WITH_CODE((entry_index <= state_arrays->ucNumEntries),
1302 "Invalid PowerPlay Table State Array Entry.", return -1);
1303
1304 state_entry = GET_FLEXIBLE_ARRAY_MEMBER_ADDR(
1305 ATOM_Tonga_State, entries,
1306 state_arrays, entry_index);
1307
1308 result = call_back_func(hwmgr, (void *)state_entry, power_state,
1309 (void *)pp_table,
1310 make_classification_flags(hwmgr,
1311 le16_to_cpu(state_entry->usClassification),
1312 le16_to_cpu(state_entry->usClassification2)));
1313 }
1314
1315 if (!result && (power_state->classification.flags &
1316 PP_StateClassificationFlag_Boot))
1317 result = hwmgr->hwmgr_func->patch_boot_state(hwmgr, &(power_state->hardware));
1318
1319 hwmgr->num_vce_state_tables = i = ppt_get_num_of_vce_state_table_entries_v1_0(hwmgr);
1320
1321 if ((i != 0) && (i <= AMD_MAX_VCE_LEVELS)) {
1322 for (j = 0; j < i; j++)
1323 ppt_get_vce_state_table_entry_v1_0(hwmgr, j, &(hwmgr->vce_states[j]), NULL, &flags);
1324 }
1325
1326 return result;
1327 }
1328
1329