1 /*
2 * Copyright (C) 2014 Traphandler
3 * Copyright (C) 2014 Free Electrons
4 * Copyright (C) 2014 Atmel
5 *
6 * Author: Jean-Jacques Hiblot <jjhiblot@traphandler.com>
7 * Author: Boris BREZILLON <boris.brezillon@free-electrons.com>
8 *
9 * This program is free software; you can redistribute it and/or modify it
10 * under the terms of the GNU General Public License version 2 as published by
11 * the Free Software Foundation.
12 *
13 * This program is distributed in the hope that it will be useful, but WITHOUT
14 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
15 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
16 * more details.
17 *
18 * You should have received a copy of the GNU General Public License along with
19 * this program. If not, see <http://www.gnu.org/licenses/>.
20 */
21
22 #ifndef DRM_ATMEL_HLCDC_H
23 #define DRM_ATMEL_HLCDC_H
24
25 #include <linux/clk.h>
26 #include <linux/dmapool.h>
27 #include <linux/irqdomain.h>
28 #include <linux/mfd/atmel-hlcdc.h>
29 #include <linux/pwm.h>
30
31 #include <drm/drm_atomic.h>
32 #include <drm/drm_atomic_helper.h>
33 #include <drm/drm_crtc.h>
34 #include <drm/drm_crtc_helper.h>
35 #include <drm/drm_fb_cma_helper.h>
36 #include <drm/drm_gem_cma_helper.h>
37 #include <drm/drm_panel.h>
38 #include <drm/drm_plane_helper.h>
39 #include <drm/drmP.h>
40
41 #define ATMEL_HLCDC_LAYER_CHER 0x0
42 #define ATMEL_HLCDC_LAYER_CHDR 0x4
43 #define ATMEL_HLCDC_LAYER_CHSR 0x8
44 #define ATMEL_HLCDC_LAYER_EN BIT(0)
45 #define ATMEL_HLCDC_LAYER_UPDATE BIT(1)
46 #define ATMEL_HLCDC_LAYER_A2Q BIT(2)
47 #define ATMEL_HLCDC_LAYER_RST BIT(8)
48
49 #define ATMEL_HLCDC_LAYER_IER 0xc
50 #define ATMEL_HLCDC_LAYER_IDR 0x10
51 #define ATMEL_HLCDC_LAYER_IMR 0x14
52 #define ATMEL_HLCDC_LAYER_ISR 0x18
53 #define ATMEL_HLCDC_LAYER_DFETCH BIT(0)
54 #define ATMEL_HLCDC_LAYER_LFETCH BIT(1)
55 #define ATMEL_HLCDC_LAYER_DMA_IRQ(p) BIT(2 + (8 * (p)))
56 #define ATMEL_HLCDC_LAYER_DSCR_IRQ(p) BIT(3 + (8 * (p)))
57 #define ATMEL_HLCDC_LAYER_ADD_IRQ(p) BIT(4 + (8 * (p)))
58 #define ATMEL_HLCDC_LAYER_DONE_IRQ(p) BIT(5 + (8 * (p)))
59 #define ATMEL_HLCDC_LAYER_OVR_IRQ(p) BIT(6 + (8 * (p)))
60
61 #define ATMEL_HLCDC_LAYER_PLANE_HEAD(p) (((p) * 0x10) + 0x1c)
62 #define ATMEL_HLCDC_LAYER_PLANE_ADDR(p) (((p) * 0x10) + 0x20)
63 #define ATMEL_HLCDC_LAYER_PLANE_CTRL(p) (((p) * 0x10) + 0x24)
64 #define ATMEL_HLCDC_LAYER_PLANE_NEXT(p) (((p) * 0x10) + 0x28)
65
66 #define ATMEL_HLCDC_LAYER_DMA_CFG 0
67 #define ATMEL_HLCDC_LAYER_DMA_SIF BIT(0)
68 #define ATMEL_HLCDC_LAYER_DMA_BLEN_MASK GENMASK(5, 4)
69 #define ATMEL_HLCDC_LAYER_DMA_BLEN_SINGLE (0 << 4)
70 #define ATMEL_HLCDC_LAYER_DMA_BLEN_INCR4 (1 << 4)
71 #define ATMEL_HLCDC_LAYER_DMA_BLEN_INCR8 (2 << 4)
72 #define ATMEL_HLCDC_LAYER_DMA_BLEN_INCR16 (3 << 4)
73 #define ATMEL_HLCDC_LAYER_DMA_DLBO BIT(8)
74 #define ATMEL_HLCDC_LAYER_DMA_ROTDIS BIT(12)
75 #define ATMEL_HLCDC_LAYER_DMA_LOCKDIS BIT(13)
76
77 #define ATMEL_HLCDC_LAYER_FORMAT_CFG 1
78 #define ATMEL_HLCDC_LAYER_RGB (0 << 0)
79 #define ATMEL_HLCDC_LAYER_CLUT (1 << 0)
80 #define ATMEL_HLCDC_LAYER_YUV (2 << 0)
81 #define ATMEL_HLCDC_RGB_MODE(m) \
82 (ATMEL_HLCDC_LAYER_RGB | (((m) & 0xf) << 4))
83 #define ATMEL_HLCDC_CLUT_MODE(m) \
84 (ATMEL_HLCDC_LAYER_CLUT | (((m) & 0x3) << 8))
85 #define ATMEL_HLCDC_YUV_MODE(m) \
86 (ATMEL_HLCDC_LAYER_YUV | (((m) & 0xf) << 12))
87 #define ATMEL_HLCDC_YUV422ROT BIT(16)
88 #define ATMEL_HLCDC_YUV422SWP BIT(17)
89 #define ATMEL_HLCDC_DSCALEOPT BIT(20)
90
91 #define ATMEL_HLCDC_C1_MODE ATMEL_HLCDC_CLUT_MODE(0)
92 #define ATMEL_HLCDC_C2_MODE ATMEL_HLCDC_CLUT_MODE(1)
93 #define ATMEL_HLCDC_C4_MODE ATMEL_HLCDC_CLUT_MODE(2)
94 #define ATMEL_HLCDC_C8_MODE ATMEL_HLCDC_CLUT_MODE(3)
95
96 #define ATMEL_HLCDC_XRGB4444_MODE ATMEL_HLCDC_RGB_MODE(0)
97 #define ATMEL_HLCDC_ARGB4444_MODE ATMEL_HLCDC_RGB_MODE(1)
98 #define ATMEL_HLCDC_RGBA4444_MODE ATMEL_HLCDC_RGB_MODE(2)
99 #define ATMEL_HLCDC_RGB565_MODE ATMEL_HLCDC_RGB_MODE(3)
100 #define ATMEL_HLCDC_ARGB1555_MODE ATMEL_HLCDC_RGB_MODE(4)
101 #define ATMEL_HLCDC_XRGB8888_MODE ATMEL_HLCDC_RGB_MODE(9)
102 #define ATMEL_HLCDC_RGB888_MODE ATMEL_HLCDC_RGB_MODE(10)
103 #define ATMEL_HLCDC_ARGB8888_MODE ATMEL_HLCDC_RGB_MODE(12)
104 #define ATMEL_HLCDC_RGBA8888_MODE ATMEL_HLCDC_RGB_MODE(13)
105
106 #define ATMEL_HLCDC_AYUV_MODE ATMEL_HLCDC_YUV_MODE(0)
107 #define ATMEL_HLCDC_YUYV_MODE ATMEL_HLCDC_YUV_MODE(1)
108 #define ATMEL_HLCDC_UYVY_MODE ATMEL_HLCDC_YUV_MODE(2)
109 #define ATMEL_HLCDC_YVYU_MODE ATMEL_HLCDC_YUV_MODE(3)
110 #define ATMEL_HLCDC_VYUY_MODE ATMEL_HLCDC_YUV_MODE(4)
111 #define ATMEL_HLCDC_NV61_MODE ATMEL_HLCDC_YUV_MODE(5)
112 #define ATMEL_HLCDC_YUV422_MODE ATMEL_HLCDC_YUV_MODE(6)
113 #define ATMEL_HLCDC_NV21_MODE ATMEL_HLCDC_YUV_MODE(7)
114 #define ATMEL_HLCDC_YUV420_MODE ATMEL_HLCDC_YUV_MODE(8)
115
116 #define ATMEL_HLCDC_LAYER_POS(x, y) ((x) | ((y) << 16))
117 #define ATMEL_HLCDC_LAYER_SIZE(w, h) (((w) - 1) | (((h) - 1) << 16))
118
119 #define ATMEL_HLCDC_LAYER_CRKEY BIT(0)
120 #define ATMEL_HLCDC_LAYER_INV BIT(1)
121 #define ATMEL_HLCDC_LAYER_ITER2BL BIT(2)
122 #define ATMEL_HLCDC_LAYER_ITER BIT(3)
123 #define ATMEL_HLCDC_LAYER_REVALPHA BIT(4)
124 #define ATMEL_HLCDC_LAYER_GAEN BIT(5)
125 #define ATMEL_HLCDC_LAYER_LAEN BIT(6)
126 #define ATMEL_HLCDC_LAYER_OVR BIT(7)
127 #define ATMEL_HLCDC_LAYER_DMA BIT(8)
128 #define ATMEL_HLCDC_LAYER_REP BIT(9)
129 #define ATMEL_HLCDC_LAYER_DSTKEY BIT(10)
130 #define ATMEL_HLCDC_LAYER_DISCEN BIT(11)
131 #define ATMEL_HLCDC_LAYER_GA_SHIFT 16
132 #define ATMEL_HLCDC_LAYER_GA_MASK \
133 GENMASK(23, ATMEL_HLCDC_LAYER_GA_SHIFT)
134 #define ATMEL_HLCDC_LAYER_GA(x) \
135 ((x) << ATMEL_HLCDC_LAYER_GA_SHIFT)
136
137 #define ATMEL_HLCDC_LAYER_DISC_POS(x, y) ((x) | ((y) << 16))
138 #define ATMEL_HLCDC_LAYER_DISC_SIZE(w, h) (((w) - 1) | (((h) - 1) << 16))
139
140 #define ATMEL_HLCDC_LAYER_SCALER_FACTORS(x, y) ((x) | ((y) << 16))
141 #define ATMEL_HLCDC_LAYER_SCALER_ENABLE BIT(31)
142
143 #define ATMEL_HLCDC_LAYER_MAX_PLANES 3
144
145 #define ATMEL_HLCDC_DMA_CHANNEL_DSCR_RESERVED BIT(0)
146 #define ATMEL_HLCDC_DMA_CHANNEL_DSCR_LOADED BIT(1)
147 #define ATMEL_HLCDC_DMA_CHANNEL_DSCR_DONE BIT(2)
148 #define ATMEL_HLCDC_DMA_CHANNEL_DSCR_OVERRUN BIT(3)
149
150 #define ATMEL_HLCDC_CLUT_SIZE 256
151
152 #define ATMEL_HLCDC_MAX_LAYERS 6
153
154 /**
155 * Atmel HLCDC Layer registers layout structure
156 *
157 * Each HLCDC layer has its own register organization and a given register
158 * can be placed differently on 2 different layers depending on its
159 * capabilities.
160 * This structure stores common registers layout for a given layer and is
161 * used by HLCDC layer code to choose the appropriate register to write to
162 * or to read from.
163 *
164 * For all fields, a value of zero means "unsupported".
165 *
166 * See Atmel's datasheet for a detailled description of these registers.
167 *
168 * @xstride: xstride registers
169 * @pstride: pstride registers
170 * @pos: position register
171 * @size: displayed size register
172 * @memsize: memory size register
173 * @default_color: default color register
174 * @chroma_key: chroma key register
175 * @chroma_key_mask: chroma key mask register
176 * @general_config: general layer config register
177 * @sacler_config: scaler factors register
178 * @phicoeffs: X/Y PHI coefficient registers
179 * @disc_pos: discard area position register
180 * @disc_size: discard area size register
181 * @csc: color space conversion register
182 */
183 struct atmel_hlcdc_layer_cfg_layout {
184 int xstride[ATMEL_HLCDC_LAYER_MAX_PLANES];
185 int pstride[ATMEL_HLCDC_LAYER_MAX_PLANES];
186 int pos;
187 int size;
188 int memsize;
189 int default_color;
190 int chroma_key;
191 int chroma_key_mask;
192 int general_config;
193 int scaler_config;
194 struct {
195 int x;
196 int y;
197 } phicoeffs;
198 int disc_pos;
199 int disc_size;
200 int csc;
201 };
202
203 /**
204 * Atmel HLCDC DMA descriptor structure
205 *
206 * This structure is used by the HLCDC DMA engine to schedule a DMA transfer.
207 *
208 * The structure fields must remain in this specific order, because they're
209 * used by the HLCDC DMA engine, which expect them in this order.
210 * HLCDC DMA descriptors must be aligned on 64 bits.
211 *
212 * @addr: buffer DMA address
213 * @ctrl: DMA transfer options
214 * @next: next DMA descriptor to fetch
215 * @self: descriptor DMA address
216 */
217 struct atmel_hlcdc_dma_channel_dscr {
218 dma_addr_t addr;
219 u32 ctrl;
220 dma_addr_t next;
221 dma_addr_t self;
222 } __aligned(sizeof(u64));
223
224 /**
225 * Atmel HLCDC layer types
226 */
227 enum atmel_hlcdc_layer_type {
228 ATMEL_HLCDC_NO_LAYER,
229 ATMEL_HLCDC_BASE_LAYER,
230 ATMEL_HLCDC_OVERLAY_LAYER,
231 ATMEL_HLCDC_CURSOR_LAYER,
232 ATMEL_HLCDC_PP_LAYER,
233 };
234
235 /**
236 * Atmel HLCDC Supported formats structure
237 *
238 * This structure list all the formats supported by a given layer.
239 *
240 * @nformats: number of supported formats
241 * @formats: supported formats
242 */
243 struct atmel_hlcdc_formats {
244 int nformats;
245 u32 *formats;
246 };
247
248 /**
249 * Atmel HLCDC Layer description structure
250 *
251 * This structure describes the capabilities provided by a given layer.
252 *
253 * @name: layer name
254 * @type: layer type
255 * @id: layer id
256 * @regs_offset: offset of the layer registers from the HLCDC registers base
257 * @cfgs_offset: CFGX registers offset from the layer registers base
258 * @formats: supported formats
259 * @layout: config registers layout
260 * @max_width: maximum width supported by this layer (0 means unlimited)
261 * @max_height: maximum height supported by this layer (0 means unlimited)
262 */
263 struct atmel_hlcdc_layer_desc {
264 const char *name;
265 enum atmel_hlcdc_layer_type type;
266 int id;
267 int regs_offset;
268 int cfgs_offset;
269 int clut_offset;
270 struct atmel_hlcdc_formats *formats;
271 struct atmel_hlcdc_layer_cfg_layout layout;
272 int max_width;
273 int max_height;
274 };
275
276 /**
277 * Atmel HLCDC Layer.
278 *
279 * A layer can be a DRM plane of a post processing layer used to render
280 * HLCDC composition into memory.
281 *
282 * @desc: layer description
283 * @regmap: pointer to the HLCDC regmap
284 */
285 struct atmel_hlcdc_layer {
286 const struct atmel_hlcdc_layer_desc *desc;
287 struct regmap *regmap;
288 };
289
290 /**
291 * Atmel HLCDC Plane.
292 *
293 * @base: base DRM plane structure
294 * @layer: HLCDC layer structure
295 * @properties: pointer to the property definitions structure
296 */
297 struct atmel_hlcdc_plane {
298 struct drm_plane base;
299 struct atmel_hlcdc_layer layer;
300 struct atmel_hlcdc_plane_properties *properties;
301 };
302
303 static inline struct atmel_hlcdc_plane *
drm_plane_to_atmel_hlcdc_plane(struct drm_plane * p)304 drm_plane_to_atmel_hlcdc_plane(struct drm_plane *p)
305 {
306 return container_of(p, struct atmel_hlcdc_plane, base);
307 }
308
309 static inline struct atmel_hlcdc_plane *
atmel_hlcdc_layer_to_plane(struct atmel_hlcdc_layer * layer)310 atmel_hlcdc_layer_to_plane(struct atmel_hlcdc_layer *layer)
311 {
312 return container_of(layer, struct atmel_hlcdc_plane, layer);
313 }
314
315 /**
316 * Atmel HLCDC Display Controller description structure.
317 *
318 * This structure describes the HLCDC IP capabilities and depends on the
319 * HLCDC IP version (or Atmel SoC family).
320 *
321 * @min_width: minimum width supported by the Display Controller
322 * @min_height: minimum height supported by the Display Controller
323 * @max_width: maximum width supported by the Display Controller
324 * @max_height: maximum height supported by the Display Controller
325 * @max_spw: maximum vertical/horizontal pulse width
326 * @max_vpw: maximum vertical back/front porch width
327 * @max_hpw: maximum horizontal back/front porch width
328 * @conflicting_output_formats: true if RGBXXX output formats conflict with
329 * each other.
330 * @layers: a layer description table describing available layers
331 * @nlayers: layer description table size
332 */
333 struct atmel_hlcdc_dc_desc {
334 int min_width;
335 int min_height;
336 int max_width;
337 int max_height;
338 int max_spw;
339 int max_vpw;
340 int max_hpw;
341 bool conflicting_output_formats;
342 const struct atmel_hlcdc_layer_desc *layers;
343 int nlayers;
344 };
345
346 /**
347 * Atmel HLCDC Plane properties.
348 *
349 * This structure stores plane property definitions.
350 *
351 * @alpha: alpha blending (or transparency) property
352 * @rotation: rotation property
353 */
354 struct atmel_hlcdc_plane_properties {
355 struct drm_property *alpha;
356 };
357
358 /**
359 * Atmel HLCDC Display Controller.
360 *
361 * @desc: HLCDC Display Controller description
362 * @dscrpool: DMA coherent pool used to allocate DMA descriptors
363 * @hlcdc: pointer to the atmel_hlcdc structure provided by the MFD device
364 * @fbdev: framebuffer device attached to the Display Controller
365 * @crtc: CRTC provided by the display controller
366 * @planes: instantiated planes
367 * @layers: active HLCDC layers
368 * @wq: display controller workqueue
369 * @suspend: used to store the HLCDC state when entering suspend
370 * @commit: used for async commit handling
371 */
372 struct atmel_hlcdc_dc {
373 const struct atmel_hlcdc_dc_desc *desc;
374 struct dma_pool *dscrpool;
375 struct atmel_hlcdc *hlcdc;
376 struct drm_fbdev_cma *fbdev;
377 struct drm_crtc *crtc;
378 struct atmel_hlcdc_layer *layers[ATMEL_HLCDC_MAX_LAYERS];
379 struct workqueue_struct *wq;
380 struct {
381 u32 imr;
382 struct drm_atomic_state *state;
383 } suspend;
384 struct {
385 wait_queue_head_t wait;
386 bool pending;
387 } commit;
388 };
389
390 extern struct atmel_hlcdc_formats atmel_hlcdc_plane_rgb_formats;
391 extern struct atmel_hlcdc_formats atmel_hlcdc_plane_rgb_and_yuv_formats;
392
atmel_hlcdc_layer_write_reg(struct atmel_hlcdc_layer * layer,unsigned int reg,u32 val)393 static inline void atmel_hlcdc_layer_write_reg(struct atmel_hlcdc_layer *layer,
394 unsigned int reg, u32 val)
395 {
396 regmap_write(layer->regmap, layer->desc->regs_offset + reg, val);
397 }
398
atmel_hlcdc_layer_read_reg(struct atmel_hlcdc_layer * layer,unsigned int reg)399 static inline u32 atmel_hlcdc_layer_read_reg(struct atmel_hlcdc_layer *layer,
400 unsigned int reg)
401 {
402 u32 val;
403
404 regmap_read(layer->regmap, layer->desc->regs_offset + reg, &val);
405
406 return val;
407 }
408
atmel_hlcdc_layer_write_cfg(struct atmel_hlcdc_layer * layer,unsigned int cfgid,u32 val)409 static inline void atmel_hlcdc_layer_write_cfg(struct atmel_hlcdc_layer *layer,
410 unsigned int cfgid, u32 val)
411 {
412 atmel_hlcdc_layer_write_reg(layer,
413 layer->desc->cfgs_offset +
414 (cfgid * sizeof(u32)), val);
415 }
416
atmel_hlcdc_layer_read_cfg(struct atmel_hlcdc_layer * layer,unsigned int cfgid)417 static inline u32 atmel_hlcdc_layer_read_cfg(struct atmel_hlcdc_layer *layer,
418 unsigned int cfgid)
419 {
420 return atmel_hlcdc_layer_read_reg(layer,
421 layer->desc->cfgs_offset +
422 (cfgid * sizeof(u32)));
423 }
424
atmel_hlcdc_layer_write_clut(struct atmel_hlcdc_layer * layer,unsigned int c,u32 val)425 static inline void atmel_hlcdc_layer_write_clut(struct atmel_hlcdc_layer *layer,
426 unsigned int c, u32 val)
427 {
428 regmap_write(layer->regmap,
429 layer->desc->clut_offset + c * sizeof(u32),
430 val);
431 }
432
atmel_hlcdc_layer_init(struct atmel_hlcdc_layer * layer,const struct atmel_hlcdc_layer_desc * desc,struct regmap * regmap)433 static inline void atmel_hlcdc_layer_init(struct atmel_hlcdc_layer *layer,
434 const struct atmel_hlcdc_layer_desc *desc,
435 struct regmap *regmap)
436 {
437 layer->desc = desc;
438 layer->regmap = regmap;
439 }
440
441 enum drm_mode_status
442 atmel_hlcdc_dc_mode_valid(struct atmel_hlcdc_dc *dc,
443 const struct drm_display_mode *mode);
444
445 int atmel_hlcdc_create_planes(struct drm_device *dev);
446 void atmel_hlcdc_plane_irq(struct atmel_hlcdc_plane *plane);
447
448 int atmel_hlcdc_plane_prepare_disc_area(struct drm_crtc_state *c_state);
449 int atmel_hlcdc_plane_prepare_ahb_routing(struct drm_crtc_state *c_state);
450
451 void atmel_hlcdc_crtc_irq(struct drm_crtc *c);
452
453 int atmel_hlcdc_crtc_create(struct drm_device *dev);
454
455 int atmel_hlcdc_create_outputs(struct drm_device *dev);
456
457 #endif /* DRM_ATMEL_HLCDC_H */
458