1 /*
2 * Copyright © 2014 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
21 * DEALINGS IN THE SOFTWARE.
22 */
23
24 #include <linux/kernel.h>
25 #include <linux/component.h>
26 #include <drm/i915_component.h>
27 #include <drm/intel_lpe_audio.h>
28 #include "intel_drv.h"
29
30 #include <drm/drmP.h>
31 #include <drm/drm_edid.h>
32 #include "i915_drv.h"
33
34 /**
35 * DOC: High Definition Audio over HDMI and Display Port
36 *
37 * The graphics and audio drivers together support High Definition Audio over
38 * HDMI and Display Port. The audio programming sequences are divided into audio
39 * codec and controller enable and disable sequences. The graphics driver
40 * handles the audio codec sequences, while the audio driver handles the audio
41 * controller sequences.
42 *
43 * The disable sequences must be performed before disabling the transcoder or
44 * port. The enable sequences may only be performed after enabling the
45 * transcoder and port, and after completed link training. Therefore the audio
46 * enable/disable sequences are part of the modeset sequence.
47 *
48 * The codec and controller sequences could be done either parallel or serial,
49 * but generally the ELDV/PD change in the codec sequence indicates to the audio
50 * driver that the controller sequence should start. Indeed, most of the
51 * co-operation between the graphics and audio drivers is handled via audio
52 * related registers. (The notable exception is the power management, not
53 * covered here.)
54 *
55 * The struct &i915_audio_component is used to interact between the graphics
56 * and audio drivers. The struct &i915_audio_component_ops @ops in it is
57 * defined in graphics driver and called in audio driver. The
58 * struct &i915_audio_component_audio_ops @audio_ops is called from i915 driver.
59 */
60
61 /* DP N/M table */
62 #define LC_540M 540000
63 #define LC_270M 270000
64 #define LC_162M 162000
65
66 struct dp_aud_n_m {
67 int sample_rate;
68 int clock;
69 u16 m;
70 u16 n;
71 };
72
73 /* Values according to DP 1.4 Table 2-104 */
74 static const struct dp_aud_n_m dp_aud_n_m[] = {
75 { 32000, LC_162M, 1024, 10125 },
76 { 44100, LC_162M, 784, 5625 },
77 { 48000, LC_162M, 512, 3375 },
78 { 64000, LC_162M, 2048, 10125 },
79 { 88200, LC_162M, 1568, 5625 },
80 { 96000, LC_162M, 1024, 3375 },
81 { 128000, LC_162M, 4096, 10125 },
82 { 176400, LC_162M, 3136, 5625 },
83 { 192000, LC_162M, 2048, 3375 },
84 { 32000, LC_270M, 1024, 16875 },
85 { 44100, LC_270M, 784, 9375 },
86 { 48000, LC_270M, 512, 5625 },
87 { 64000, LC_270M, 2048, 16875 },
88 { 88200, LC_270M, 1568, 9375 },
89 { 96000, LC_270M, 1024, 5625 },
90 { 128000, LC_270M, 4096, 16875 },
91 { 176400, LC_270M, 3136, 9375 },
92 { 192000, LC_270M, 2048, 5625 },
93 { 32000, LC_540M, 1024, 33750 },
94 { 44100, LC_540M, 784, 18750 },
95 { 48000, LC_540M, 512, 11250 },
96 { 64000, LC_540M, 2048, 33750 },
97 { 88200, LC_540M, 1568, 18750 },
98 { 96000, LC_540M, 1024, 11250 },
99 { 128000, LC_540M, 4096, 33750 },
100 { 176400, LC_540M, 3136, 18750 },
101 { 192000, LC_540M, 2048, 11250 },
102 };
103
104 static const struct dp_aud_n_m *
audio_config_dp_get_n_m(struct intel_crtc * intel_crtc,int rate)105 audio_config_dp_get_n_m(struct intel_crtc *intel_crtc, int rate)
106 {
107 int i;
108
109 for (i = 0; i < ARRAY_SIZE(dp_aud_n_m); i++) {
110 if (rate == dp_aud_n_m[i].sample_rate &&
111 intel_crtc->config->port_clock == dp_aud_n_m[i].clock)
112 return &dp_aud_n_m[i];
113 }
114
115 return NULL;
116 }
117
118 static const struct {
119 int clock;
120 u32 config;
121 } hdmi_audio_clock[] = {
122 { 25175, AUD_CONFIG_PIXEL_CLOCK_HDMI_25175 },
123 { 25200, AUD_CONFIG_PIXEL_CLOCK_HDMI_25200 }, /* default per bspec */
124 { 27000, AUD_CONFIG_PIXEL_CLOCK_HDMI_27000 },
125 { 27027, AUD_CONFIG_PIXEL_CLOCK_HDMI_27027 },
126 { 54000, AUD_CONFIG_PIXEL_CLOCK_HDMI_54000 },
127 { 54054, AUD_CONFIG_PIXEL_CLOCK_HDMI_54054 },
128 { 74176, AUD_CONFIG_PIXEL_CLOCK_HDMI_74176 },
129 { 74250, AUD_CONFIG_PIXEL_CLOCK_HDMI_74250 },
130 { 148352, AUD_CONFIG_PIXEL_CLOCK_HDMI_148352 },
131 { 148500, AUD_CONFIG_PIXEL_CLOCK_HDMI_148500 },
132 };
133
134 /* HDMI N/CTS table */
135 #define TMDS_297M 297000
136 #define TMDS_296M 296703
137 #define TMDS_594M 594000
138 #define TMDS_593M 593407
139
140 static const struct {
141 int sample_rate;
142 int clock;
143 int n;
144 int cts;
145 } hdmi_aud_ncts[] = {
146 { 44100, TMDS_296M, 4459, 234375 },
147 { 44100, TMDS_297M, 4704, 247500 },
148 { 48000, TMDS_296M, 5824, 281250 },
149 { 48000, TMDS_297M, 5120, 247500 },
150 { 32000, TMDS_296M, 5824, 421875 },
151 { 32000, TMDS_297M, 3072, 222750 },
152 { 88200, TMDS_296M, 8918, 234375 },
153 { 88200, TMDS_297M, 9408, 247500 },
154 { 96000, TMDS_296M, 11648, 281250 },
155 { 96000, TMDS_297M, 10240, 247500 },
156 { 176400, TMDS_296M, 17836, 234375 },
157 { 176400, TMDS_297M, 18816, 247500 },
158 { 192000, TMDS_296M, 23296, 281250 },
159 { 192000, TMDS_297M, 20480, 247500 },
160 { 44100, TMDS_593M, 8918, 937500 },
161 { 44100, TMDS_594M, 9408, 990000 },
162 { 48000, TMDS_593M, 5824, 562500 },
163 { 48000, TMDS_594M, 6144, 594000 },
164 { 32000, TMDS_593M, 5824, 843750 },
165 { 32000, TMDS_594M, 3072, 445500 },
166 { 88200, TMDS_593M, 17836, 937500 },
167 { 88200, TMDS_594M, 18816, 990000 },
168 { 96000, TMDS_593M, 11648, 562500 },
169 { 96000, TMDS_594M, 12288, 594000 },
170 { 176400, TMDS_593M, 35672, 937500 },
171 { 176400, TMDS_594M, 37632, 990000 },
172 { 192000, TMDS_593M, 23296, 562500 },
173 { 192000, TMDS_594M, 24576, 594000 },
174 };
175
176 /* get AUD_CONFIG_PIXEL_CLOCK_HDMI_* value for mode */
audio_config_hdmi_pixel_clock(const struct drm_display_mode * adjusted_mode)177 static u32 audio_config_hdmi_pixel_clock(const struct drm_display_mode *adjusted_mode)
178 {
179 int i;
180
181 for (i = 0; i < ARRAY_SIZE(hdmi_audio_clock); i++) {
182 if (adjusted_mode->crtc_clock == hdmi_audio_clock[i].clock)
183 break;
184 }
185
186 if (i == ARRAY_SIZE(hdmi_audio_clock)) {
187 DRM_DEBUG_KMS("HDMI audio pixel clock setting for %d not found, falling back to defaults\n",
188 adjusted_mode->crtc_clock);
189 i = 1;
190 }
191
192 DRM_DEBUG_KMS("Configuring HDMI audio for pixel clock %d (0x%08x)\n",
193 hdmi_audio_clock[i].clock,
194 hdmi_audio_clock[i].config);
195
196 return hdmi_audio_clock[i].config;
197 }
198
audio_config_hdmi_get_n(const struct drm_display_mode * adjusted_mode,int rate)199 static int audio_config_hdmi_get_n(const struct drm_display_mode *adjusted_mode,
200 int rate)
201 {
202 int i;
203
204 for (i = 0; i < ARRAY_SIZE(hdmi_aud_ncts); i++) {
205 if (rate == hdmi_aud_ncts[i].sample_rate &&
206 adjusted_mode->crtc_clock == hdmi_aud_ncts[i].clock) {
207 return hdmi_aud_ncts[i].n;
208 }
209 }
210 return 0;
211 }
212
intel_eld_uptodate(struct drm_connector * connector,i915_reg_t reg_eldv,uint32_t bits_eldv,i915_reg_t reg_elda,uint32_t bits_elda,i915_reg_t reg_edid)213 static bool intel_eld_uptodate(struct drm_connector *connector,
214 i915_reg_t reg_eldv, uint32_t bits_eldv,
215 i915_reg_t reg_elda, uint32_t bits_elda,
216 i915_reg_t reg_edid)
217 {
218 struct drm_i915_private *dev_priv = to_i915(connector->dev);
219 uint8_t *eld = connector->eld;
220 uint32_t tmp;
221 int i;
222
223 tmp = I915_READ(reg_eldv);
224 tmp &= bits_eldv;
225
226 if (!tmp)
227 return false;
228
229 tmp = I915_READ(reg_elda);
230 tmp &= ~bits_elda;
231 I915_WRITE(reg_elda, tmp);
232
233 for (i = 0; i < drm_eld_size(eld) / 4; i++)
234 if (I915_READ(reg_edid) != *((uint32_t *)eld + i))
235 return false;
236
237 return true;
238 }
239
g4x_audio_codec_disable(struct intel_encoder * encoder)240 static void g4x_audio_codec_disable(struct intel_encoder *encoder)
241 {
242 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
243 uint32_t eldv, tmp;
244
245 DRM_DEBUG_KMS("Disable audio codec\n");
246
247 tmp = I915_READ(G4X_AUD_VID_DID);
248 if (tmp == INTEL_AUDIO_DEVBLC || tmp == INTEL_AUDIO_DEVCL)
249 eldv = G4X_ELDV_DEVCL_DEVBLC;
250 else
251 eldv = G4X_ELDV_DEVCTG;
252
253 /* Invalidate ELD */
254 tmp = I915_READ(G4X_AUD_CNTL_ST);
255 tmp &= ~eldv;
256 I915_WRITE(G4X_AUD_CNTL_ST, tmp);
257 }
258
g4x_audio_codec_enable(struct drm_connector * connector,struct intel_encoder * encoder,const struct drm_display_mode * adjusted_mode)259 static void g4x_audio_codec_enable(struct drm_connector *connector,
260 struct intel_encoder *encoder,
261 const struct drm_display_mode *adjusted_mode)
262 {
263 struct drm_i915_private *dev_priv = to_i915(connector->dev);
264 uint8_t *eld = connector->eld;
265 uint32_t eldv;
266 uint32_t tmp;
267 int len, i;
268
269 DRM_DEBUG_KMS("Enable audio codec, %u bytes ELD\n", eld[2]);
270
271 tmp = I915_READ(G4X_AUD_VID_DID);
272 if (tmp == INTEL_AUDIO_DEVBLC || tmp == INTEL_AUDIO_DEVCL)
273 eldv = G4X_ELDV_DEVCL_DEVBLC;
274 else
275 eldv = G4X_ELDV_DEVCTG;
276
277 if (intel_eld_uptodate(connector,
278 G4X_AUD_CNTL_ST, eldv,
279 G4X_AUD_CNTL_ST, G4X_ELD_ADDR_MASK,
280 G4X_HDMIW_HDMIEDID))
281 return;
282
283 tmp = I915_READ(G4X_AUD_CNTL_ST);
284 tmp &= ~(eldv | G4X_ELD_ADDR_MASK);
285 len = (tmp >> 9) & 0x1f; /* ELD buffer size */
286 I915_WRITE(G4X_AUD_CNTL_ST, tmp);
287
288 len = min(drm_eld_size(eld) / 4, len);
289 DRM_DEBUG_DRIVER("ELD size %d\n", len);
290 for (i = 0; i < len; i++)
291 I915_WRITE(G4X_HDMIW_HDMIEDID, *((uint32_t *)eld + i));
292
293 tmp = I915_READ(G4X_AUD_CNTL_ST);
294 tmp |= eldv;
295 I915_WRITE(G4X_AUD_CNTL_ST, tmp);
296 }
297
298 static void
hsw_dp_audio_config_update(struct intel_crtc * intel_crtc,enum port port,const struct drm_display_mode * adjusted_mode)299 hsw_dp_audio_config_update(struct intel_crtc *intel_crtc, enum port port,
300 const struct drm_display_mode *adjusted_mode)
301 {
302 struct drm_i915_private *dev_priv = to_i915(intel_crtc->base.dev);
303 struct i915_audio_component *acomp = dev_priv->audio_component;
304 int rate = acomp ? acomp->aud_sample_rate[port] : 0;
305 const struct dp_aud_n_m *nm = audio_config_dp_get_n_m(intel_crtc, rate);
306 enum pipe pipe = intel_crtc->pipe;
307 u32 tmp;
308
309 if (nm)
310 DRM_DEBUG_KMS("using Maud %u, Naud %u\n", nm->m, nm->n);
311 else
312 DRM_DEBUG_KMS("using automatic Maud, Naud\n");
313
314 tmp = I915_READ(HSW_AUD_CFG(pipe));
315 tmp &= ~AUD_CONFIG_N_VALUE_INDEX;
316 tmp &= ~AUD_CONFIG_PIXEL_CLOCK_HDMI_MASK;
317 tmp &= ~AUD_CONFIG_N_PROG_ENABLE;
318 tmp |= AUD_CONFIG_N_VALUE_INDEX;
319
320 if (nm) {
321 tmp &= ~AUD_CONFIG_N_MASK;
322 tmp |= AUD_CONFIG_N(nm->n);
323 tmp |= AUD_CONFIG_N_PROG_ENABLE;
324 }
325
326 I915_WRITE(HSW_AUD_CFG(pipe), tmp);
327
328 tmp = I915_READ(HSW_AUD_M_CTS_ENABLE(pipe));
329 tmp &= ~AUD_CONFIG_M_MASK;
330 tmp &= ~AUD_M_CTS_M_VALUE_INDEX;
331 tmp &= ~AUD_M_CTS_M_PROG_ENABLE;
332
333 if (nm) {
334 tmp |= nm->m;
335 tmp |= AUD_M_CTS_M_VALUE_INDEX;
336 tmp |= AUD_M_CTS_M_PROG_ENABLE;
337 }
338
339 I915_WRITE(HSW_AUD_M_CTS_ENABLE(pipe), tmp);
340 }
341
342 static void
hsw_hdmi_audio_config_update(struct intel_crtc * intel_crtc,enum port port,const struct drm_display_mode * adjusted_mode)343 hsw_hdmi_audio_config_update(struct intel_crtc *intel_crtc, enum port port,
344 const struct drm_display_mode *adjusted_mode)
345 {
346 struct drm_i915_private *dev_priv = to_i915(intel_crtc->base.dev);
347 struct i915_audio_component *acomp = dev_priv->audio_component;
348 int rate = acomp ? acomp->aud_sample_rate[port] : 0;
349 enum pipe pipe = intel_crtc->pipe;
350 int n;
351 u32 tmp;
352
353 tmp = I915_READ(HSW_AUD_CFG(pipe));
354 tmp &= ~AUD_CONFIG_N_VALUE_INDEX;
355 tmp &= ~AUD_CONFIG_PIXEL_CLOCK_HDMI_MASK;
356 tmp &= ~AUD_CONFIG_N_PROG_ENABLE;
357 tmp |= audio_config_hdmi_pixel_clock(adjusted_mode);
358
359 n = audio_config_hdmi_get_n(adjusted_mode, rate);
360 if (n != 0) {
361 DRM_DEBUG_KMS("using N %d\n", n);
362
363 tmp &= ~AUD_CONFIG_N_MASK;
364 tmp |= AUD_CONFIG_N(n);
365 tmp |= AUD_CONFIG_N_PROG_ENABLE;
366 } else {
367 DRM_DEBUG_KMS("using automatic N\n");
368 }
369
370 I915_WRITE(HSW_AUD_CFG(pipe), tmp);
371
372 /*
373 * Let's disable "Enable CTS or M Prog bit"
374 * and let HW calculate the value
375 */
376 tmp = I915_READ(HSW_AUD_M_CTS_ENABLE(pipe));
377 tmp &= ~AUD_M_CTS_M_PROG_ENABLE;
378 tmp &= ~AUD_M_CTS_M_VALUE_INDEX;
379 I915_WRITE(HSW_AUD_M_CTS_ENABLE(pipe), tmp);
380 }
381
382 static void
hsw_audio_config_update(struct intel_crtc * intel_crtc,enum port port,const struct drm_display_mode * adjusted_mode)383 hsw_audio_config_update(struct intel_crtc *intel_crtc, enum port port,
384 const struct drm_display_mode *adjusted_mode)
385 {
386 if (intel_crtc_has_dp_encoder(intel_crtc->config))
387 hsw_dp_audio_config_update(intel_crtc, port, adjusted_mode);
388 else
389 hsw_hdmi_audio_config_update(intel_crtc, port, adjusted_mode);
390 }
391
hsw_audio_codec_disable(struct intel_encoder * encoder)392 static void hsw_audio_codec_disable(struct intel_encoder *encoder)
393 {
394 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
395 struct intel_crtc *intel_crtc = to_intel_crtc(encoder->base.crtc);
396 enum pipe pipe = intel_crtc->pipe;
397 uint32_t tmp;
398
399 DRM_DEBUG_KMS("Disable audio codec on pipe %c\n", pipe_name(pipe));
400
401 mutex_lock(&dev_priv->av_mutex);
402
403 /* Disable timestamps */
404 tmp = I915_READ(HSW_AUD_CFG(pipe));
405 tmp &= ~AUD_CONFIG_N_VALUE_INDEX;
406 tmp |= AUD_CONFIG_N_PROG_ENABLE;
407 tmp &= ~AUD_CONFIG_UPPER_N_MASK;
408 tmp &= ~AUD_CONFIG_LOWER_N_MASK;
409 if (intel_crtc_has_dp_encoder(intel_crtc->config))
410 tmp |= AUD_CONFIG_N_VALUE_INDEX;
411 I915_WRITE(HSW_AUD_CFG(pipe), tmp);
412
413 /* Invalidate ELD */
414 tmp = I915_READ(HSW_AUD_PIN_ELD_CP_VLD);
415 tmp &= ~AUDIO_ELD_VALID(pipe);
416 tmp &= ~AUDIO_OUTPUT_ENABLE(pipe);
417 I915_WRITE(HSW_AUD_PIN_ELD_CP_VLD, tmp);
418
419 mutex_unlock(&dev_priv->av_mutex);
420 }
421
hsw_audio_codec_enable(struct drm_connector * connector,struct intel_encoder * intel_encoder,const struct drm_display_mode * adjusted_mode)422 static void hsw_audio_codec_enable(struct drm_connector *connector,
423 struct intel_encoder *intel_encoder,
424 const struct drm_display_mode *adjusted_mode)
425 {
426 struct drm_i915_private *dev_priv = to_i915(connector->dev);
427 struct intel_crtc *intel_crtc = to_intel_crtc(intel_encoder->base.crtc);
428 enum pipe pipe = intel_crtc->pipe;
429 enum port port = intel_encoder->port;
430 const uint8_t *eld = connector->eld;
431 uint32_t tmp;
432 int len, i;
433
434 DRM_DEBUG_KMS("Enable audio codec on pipe %c, %u bytes ELD\n",
435 pipe_name(pipe), drm_eld_size(eld));
436
437 mutex_lock(&dev_priv->av_mutex);
438
439 /* Enable audio presence detect, invalidate ELD */
440 tmp = I915_READ(HSW_AUD_PIN_ELD_CP_VLD);
441 tmp |= AUDIO_OUTPUT_ENABLE(pipe);
442 tmp &= ~AUDIO_ELD_VALID(pipe);
443 I915_WRITE(HSW_AUD_PIN_ELD_CP_VLD, tmp);
444
445 /*
446 * FIXME: We're supposed to wait for vblank here, but we have vblanks
447 * disabled during the mode set. The proper fix would be to push the
448 * rest of the setup into a vblank work item, queued here, but the
449 * infrastructure is not there yet.
450 */
451
452 /* Reset ELD write address */
453 tmp = I915_READ(HSW_AUD_DIP_ELD_CTRL(pipe));
454 tmp &= ~IBX_ELD_ADDRESS_MASK;
455 I915_WRITE(HSW_AUD_DIP_ELD_CTRL(pipe), tmp);
456
457 /* Up to 84 bytes of hw ELD buffer */
458 len = min(drm_eld_size(eld), 84);
459 for (i = 0; i < len / 4; i++)
460 I915_WRITE(HSW_AUD_EDID_DATA(pipe), *((uint32_t *)eld + i));
461
462 /* ELD valid */
463 tmp = I915_READ(HSW_AUD_PIN_ELD_CP_VLD);
464 tmp |= AUDIO_ELD_VALID(pipe);
465 I915_WRITE(HSW_AUD_PIN_ELD_CP_VLD, tmp);
466
467 /* Enable timestamps */
468 hsw_audio_config_update(intel_crtc, port, adjusted_mode);
469
470 mutex_unlock(&dev_priv->av_mutex);
471 }
472
ilk_audio_codec_disable(struct intel_encoder * intel_encoder)473 static void ilk_audio_codec_disable(struct intel_encoder *intel_encoder)
474 {
475 struct drm_i915_private *dev_priv = to_i915(intel_encoder->base.dev);
476 struct intel_crtc *intel_crtc = to_intel_crtc(intel_encoder->base.crtc);
477 enum pipe pipe = intel_crtc->pipe;
478 enum port port = intel_encoder->port;
479 uint32_t tmp, eldv;
480 i915_reg_t aud_config, aud_cntrl_st2;
481
482 DRM_DEBUG_KMS("Disable audio codec on port %c, pipe %c\n",
483 port_name(port), pipe_name(pipe));
484
485 if (WARN_ON(port == PORT_A))
486 return;
487
488 if (HAS_PCH_IBX(dev_priv)) {
489 aud_config = IBX_AUD_CFG(pipe);
490 aud_cntrl_st2 = IBX_AUD_CNTL_ST2;
491 } else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
492 aud_config = VLV_AUD_CFG(pipe);
493 aud_cntrl_st2 = VLV_AUD_CNTL_ST2;
494 } else {
495 aud_config = CPT_AUD_CFG(pipe);
496 aud_cntrl_st2 = CPT_AUD_CNTRL_ST2;
497 }
498
499 /* Disable timestamps */
500 tmp = I915_READ(aud_config);
501 tmp &= ~AUD_CONFIG_N_VALUE_INDEX;
502 tmp |= AUD_CONFIG_N_PROG_ENABLE;
503 tmp &= ~AUD_CONFIG_UPPER_N_MASK;
504 tmp &= ~AUD_CONFIG_LOWER_N_MASK;
505 if (intel_crtc_has_dp_encoder(intel_crtc->config))
506 tmp |= AUD_CONFIG_N_VALUE_INDEX;
507 I915_WRITE(aud_config, tmp);
508
509 eldv = IBX_ELD_VALID(port);
510
511 /* Invalidate ELD */
512 tmp = I915_READ(aud_cntrl_st2);
513 tmp &= ~eldv;
514 I915_WRITE(aud_cntrl_st2, tmp);
515 }
516
ilk_audio_codec_enable(struct drm_connector * connector,struct intel_encoder * intel_encoder,const struct drm_display_mode * adjusted_mode)517 static void ilk_audio_codec_enable(struct drm_connector *connector,
518 struct intel_encoder *intel_encoder,
519 const struct drm_display_mode *adjusted_mode)
520 {
521 struct drm_i915_private *dev_priv = to_i915(connector->dev);
522 struct intel_crtc *intel_crtc = to_intel_crtc(intel_encoder->base.crtc);
523 enum pipe pipe = intel_crtc->pipe;
524 enum port port = intel_encoder->port;
525 uint8_t *eld = connector->eld;
526 uint32_t tmp, eldv;
527 int len, i;
528 i915_reg_t hdmiw_hdmiedid, aud_config, aud_cntl_st, aud_cntrl_st2;
529
530 DRM_DEBUG_KMS("Enable audio codec on port %c, pipe %c, %u bytes ELD\n",
531 port_name(port), pipe_name(pipe), drm_eld_size(eld));
532
533 if (WARN_ON(port == PORT_A))
534 return;
535
536 /*
537 * FIXME: We're supposed to wait for vblank here, but we have vblanks
538 * disabled during the mode set. The proper fix would be to push the
539 * rest of the setup into a vblank work item, queued here, but the
540 * infrastructure is not there yet.
541 */
542
543 if (HAS_PCH_IBX(dev_priv)) {
544 hdmiw_hdmiedid = IBX_HDMIW_HDMIEDID(pipe);
545 aud_config = IBX_AUD_CFG(pipe);
546 aud_cntl_st = IBX_AUD_CNTL_ST(pipe);
547 aud_cntrl_st2 = IBX_AUD_CNTL_ST2;
548 } else if (IS_VALLEYVIEW(dev_priv) ||
549 IS_CHERRYVIEW(dev_priv)) {
550 hdmiw_hdmiedid = VLV_HDMIW_HDMIEDID(pipe);
551 aud_config = VLV_AUD_CFG(pipe);
552 aud_cntl_st = VLV_AUD_CNTL_ST(pipe);
553 aud_cntrl_st2 = VLV_AUD_CNTL_ST2;
554 } else {
555 hdmiw_hdmiedid = CPT_HDMIW_HDMIEDID(pipe);
556 aud_config = CPT_AUD_CFG(pipe);
557 aud_cntl_st = CPT_AUD_CNTL_ST(pipe);
558 aud_cntrl_st2 = CPT_AUD_CNTRL_ST2;
559 }
560
561 eldv = IBX_ELD_VALID(port);
562
563 /* Invalidate ELD */
564 tmp = I915_READ(aud_cntrl_st2);
565 tmp &= ~eldv;
566 I915_WRITE(aud_cntrl_st2, tmp);
567
568 /* Reset ELD write address */
569 tmp = I915_READ(aud_cntl_st);
570 tmp &= ~IBX_ELD_ADDRESS_MASK;
571 I915_WRITE(aud_cntl_st, tmp);
572
573 /* Up to 84 bytes of hw ELD buffer */
574 len = min(drm_eld_size(eld), 84);
575 for (i = 0; i < len / 4; i++)
576 I915_WRITE(hdmiw_hdmiedid, *((uint32_t *)eld + i));
577
578 /* ELD valid */
579 tmp = I915_READ(aud_cntrl_st2);
580 tmp |= eldv;
581 I915_WRITE(aud_cntrl_st2, tmp);
582
583 /* Enable timestamps */
584 tmp = I915_READ(aud_config);
585 tmp &= ~AUD_CONFIG_N_VALUE_INDEX;
586 tmp &= ~AUD_CONFIG_N_PROG_ENABLE;
587 tmp &= ~AUD_CONFIG_PIXEL_CLOCK_HDMI_MASK;
588 if (intel_crtc_has_dp_encoder(intel_crtc->config))
589 tmp |= AUD_CONFIG_N_VALUE_INDEX;
590 else
591 tmp |= audio_config_hdmi_pixel_clock(adjusted_mode);
592 I915_WRITE(aud_config, tmp);
593 }
594
595 /**
596 * intel_audio_codec_enable - Enable the audio codec for HD audio
597 * @intel_encoder: encoder on which to enable audio
598 * @crtc_state: pointer to the current crtc state.
599 * @conn_state: pointer to the current connector state.
600 *
601 * The enable sequences may only be performed after enabling the transcoder and
602 * port, and after completed link training.
603 */
intel_audio_codec_enable(struct intel_encoder * intel_encoder,const struct intel_crtc_state * crtc_state,const struct drm_connector_state * conn_state)604 void intel_audio_codec_enable(struct intel_encoder *intel_encoder,
605 const struct intel_crtc_state *crtc_state,
606 const struct drm_connector_state *conn_state)
607 {
608 struct drm_encoder *encoder = &intel_encoder->base;
609 const struct drm_display_mode *adjusted_mode = &crtc_state->base.adjusted_mode;
610 struct drm_connector *connector;
611 struct drm_i915_private *dev_priv = to_i915(encoder->dev);
612 struct i915_audio_component *acomp = dev_priv->audio_component;
613 enum port port = intel_encoder->port;
614 enum pipe pipe = to_intel_crtc(crtc_state->base.crtc)->pipe;
615
616 connector = conn_state->connector;
617 if (!connector || !connector->eld[0])
618 return;
619
620 DRM_DEBUG_DRIVER("ELD on [CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
621 connector->base.id,
622 connector->name,
623 connector->encoder->base.id,
624 connector->encoder->name);
625
626 connector->eld[6] = drm_av_sync_delay(connector, adjusted_mode) / 2;
627
628 if (dev_priv->display.audio_codec_enable)
629 dev_priv->display.audio_codec_enable(connector, intel_encoder,
630 adjusted_mode);
631
632 mutex_lock(&dev_priv->av_mutex);
633 intel_encoder->audio_connector = connector;
634
635 /* referred in audio callbacks */
636 dev_priv->av_enc_map[pipe] = intel_encoder;
637 mutex_unlock(&dev_priv->av_mutex);
638
639 if (acomp && acomp->audio_ops && acomp->audio_ops->pin_eld_notify) {
640 /* audio drivers expect pipe = -1 to indicate Non-MST cases */
641 if (intel_encoder->type != INTEL_OUTPUT_DP_MST)
642 pipe = -1;
643 acomp->audio_ops->pin_eld_notify(acomp->audio_ops->audio_ptr,
644 (int) port, (int) pipe);
645 }
646
647 intel_lpe_audio_notify(dev_priv, pipe, port, connector->eld,
648 crtc_state->port_clock,
649 intel_encoder->type == INTEL_OUTPUT_DP);
650 }
651
652 /**
653 * intel_audio_codec_disable - Disable the audio codec for HD audio
654 * @intel_encoder: encoder on which to disable audio
655 *
656 * The disable sequences must be performed before disabling the transcoder or
657 * port.
658 */
intel_audio_codec_disable(struct intel_encoder * intel_encoder)659 void intel_audio_codec_disable(struct intel_encoder *intel_encoder)
660 {
661 struct drm_encoder *encoder = &intel_encoder->base;
662 struct drm_i915_private *dev_priv = to_i915(encoder->dev);
663 struct i915_audio_component *acomp = dev_priv->audio_component;
664 enum port port = intel_encoder->port;
665 struct intel_crtc *crtc = to_intel_crtc(encoder->crtc);
666 enum pipe pipe = crtc->pipe;
667
668 if (dev_priv->display.audio_codec_disable)
669 dev_priv->display.audio_codec_disable(intel_encoder);
670
671 mutex_lock(&dev_priv->av_mutex);
672 intel_encoder->audio_connector = NULL;
673 dev_priv->av_enc_map[pipe] = NULL;
674 mutex_unlock(&dev_priv->av_mutex);
675
676 if (acomp && acomp->audio_ops && acomp->audio_ops->pin_eld_notify) {
677 /* audio drivers expect pipe = -1 to indicate Non-MST cases */
678 if (intel_encoder->type != INTEL_OUTPUT_DP_MST)
679 pipe = -1;
680 acomp->audio_ops->pin_eld_notify(acomp->audio_ops->audio_ptr,
681 (int) port, (int) pipe);
682 }
683
684 intel_lpe_audio_notify(dev_priv, pipe, port, NULL, 0, false);
685 }
686
687 /**
688 * intel_init_audio_hooks - Set up chip specific audio hooks
689 * @dev_priv: device private
690 */
intel_init_audio_hooks(struct drm_i915_private * dev_priv)691 void intel_init_audio_hooks(struct drm_i915_private *dev_priv)
692 {
693 if (IS_G4X(dev_priv)) {
694 dev_priv->display.audio_codec_enable = g4x_audio_codec_enable;
695 dev_priv->display.audio_codec_disable = g4x_audio_codec_disable;
696 } else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
697 dev_priv->display.audio_codec_enable = ilk_audio_codec_enable;
698 dev_priv->display.audio_codec_disable = ilk_audio_codec_disable;
699 } else if (IS_HASWELL(dev_priv) || INTEL_INFO(dev_priv)->gen >= 8) {
700 dev_priv->display.audio_codec_enable = hsw_audio_codec_enable;
701 dev_priv->display.audio_codec_disable = hsw_audio_codec_disable;
702 } else if (HAS_PCH_SPLIT(dev_priv)) {
703 dev_priv->display.audio_codec_enable = ilk_audio_codec_enable;
704 dev_priv->display.audio_codec_disable = ilk_audio_codec_disable;
705 }
706 }
707
i915_audio_component_get_power(struct device * kdev)708 static void i915_audio_component_get_power(struct device *kdev)
709 {
710 intel_display_power_get(kdev_to_i915(kdev), POWER_DOMAIN_AUDIO);
711 }
712
i915_audio_component_put_power(struct device * kdev)713 static void i915_audio_component_put_power(struct device *kdev)
714 {
715 intel_display_power_put(kdev_to_i915(kdev), POWER_DOMAIN_AUDIO);
716 }
717
i915_audio_component_codec_wake_override(struct device * kdev,bool enable)718 static void i915_audio_component_codec_wake_override(struct device *kdev,
719 bool enable)
720 {
721 struct drm_i915_private *dev_priv = kdev_to_i915(kdev);
722 u32 tmp;
723
724 if (!IS_GEN9(dev_priv))
725 return;
726
727 i915_audio_component_get_power(kdev);
728
729 /*
730 * Enable/disable generating the codec wake signal, overriding the
731 * internal logic to generate the codec wake to controller.
732 */
733 tmp = I915_READ(HSW_AUD_CHICKENBIT);
734 tmp &= ~SKL_AUD_CODEC_WAKE_SIGNAL;
735 I915_WRITE(HSW_AUD_CHICKENBIT, tmp);
736 usleep_range(1000, 1500);
737
738 if (enable) {
739 tmp = I915_READ(HSW_AUD_CHICKENBIT);
740 tmp |= SKL_AUD_CODEC_WAKE_SIGNAL;
741 I915_WRITE(HSW_AUD_CHICKENBIT, tmp);
742 usleep_range(1000, 1500);
743 }
744
745 i915_audio_component_put_power(kdev);
746 }
747
748 /* Get CDCLK in kHz */
i915_audio_component_get_cdclk_freq(struct device * kdev)749 static int i915_audio_component_get_cdclk_freq(struct device *kdev)
750 {
751 struct drm_i915_private *dev_priv = kdev_to_i915(kdev);
752
753 if (WARN_ON_ONCE(!HAS_DDI(dev_priv)))
754 return -ENODEV;
755
756 return dev_priv->cdclk.hw.cdclk;
757 }
758
759 /*
760 * get the intel_encoder according to the parameter port and pipe
761 * intel_encoder is saved by the index of pipe
762 * MST & (pipe >= 0): return the av_enc_map[pipe],
763 * when port is matched
764 * MST & (pipe < 0): this is invalid
765 * Non-MST & (pipe >= 0): only pipe = 0 (the first device entry)
766 * will get the right intel_encoder with port matched
767 * Non-MST & (pipe < 0): get the right intel_encoder with port matched
768 */
get_saved_enc(struct drm_i915_private * dev_priv,int port,int pipe)769 static struct intel_encoder *get_saved_enc(struct drm_i915_private *dev_priv,
770 int port, int pipe)
771 {
772 struct intel_encoder *encoder;
773
774 if (WARN_ON(pipe >= I915_MAX_PIPES))
775 return NULL;
776
777 /* MST */
778 if (pipe >= 0) {
779 encoder = dev_priv->av_enc_map[pipe];
780 /*
781 * when bootup, audio driver may not know it is
782 * MST or not. So it will poll all the port & pipe
783 * combinations
784 */
785 if (encoder != NULL && encoder->port == port &&
786 encoder->type == INTEL_OUTPUT_DP_MST)
787 return encoder;
788 }
789
790 /* Non-MST */
791 if (pipe > 0)
792 return NULL;
793
794 for_each_pipe(dev_priv, pipe) {
795 encoder = dev_priv->av_enc_map[pipe];
796 if (encoder == NULL)
797 continue;
798
799 if (encoder->type == INTEL_OUTPUT_DP_MST)
800 continue;
801
802 if (port == encoder->port)
803 return encoder;
804 }
805
806 return NULL;
807 }
808
i915_audio_component_sync_audio_rate(struct device * kdev,int port,int pipe,int rate)809 static int i915_audio_component_sync_audio_rate(struct device *kdev, int port,
810 int pipe, int rate)
811 {
812 struct drm_i915_private *dev_priv = kdev_to_i915(kdev);
813 struct intel_encoder *intel_encoder;
814 struct intel_crtc *crtc;
815 struct drm_display_mode *adjusted_mode;
816 struct i915_audio_component *acomp = dev_priv->audio_component;
817 int err = 0;
818
819 if (!HAS_DDI(dev_priv))
820 return 0;
821
822 i915_audio_component_get_power(kdev);
823 mutex_lock(&dev_priv->av_mutex);
824
825 /* 1. get the pipe */
826 intel_encoder = get_saved_enc(dev_priv, port, pipe);
827 if (!intel_encoder || !intel_encoder->base.crtc) {
828 DRM_DEBUG_KMS("Not valid for port %c\n", port_name(port));
829 err = -ENODEV;
830 goto unlock;
831 }
832
833 /* pipe passed from the audio driver will be -1 for Non-MST case */
834 crtc = to_intel_crtc(intel_encoder->base.crtc);
835 pipe = crtc->pipe;
836
837 adjusted_mode = &crtc->config->base.adjusted_mode;
838
839 /* port must be valid now, otherwise the pipe will be invalid */
840 acomp->aud_sample_rate[port] = rate;
841
842 hsw_audio_config_update(crtc, port, adjusted_mode);
843
844 unlock:
845 mutex_unlock(&dev_priv->av_mutex);
846 i915_audio_component_put_power(kdev);
847 return err;
848 }
849
i915_audio_component_get_eld(struct device * kdev,int port,int pipe,bool * enabled,unsigned char * buf,int max_bytes)850 static int i915_audio_component_get_eld(struct device *kdev, int port,
851 int pipe, bool *enabled,
852 unsigned char *buf, int max_bytes)
853 {
854 struct drm_i915_private *dev_priv = kdev_to_i915(kdev);
855 struct intel_encoder *intel_encoder;
856 const u8 *eld;
857 int ret = -EINVAL;
858
859 mutex_lock(&dev_priv->av_mutex);
860
861 intel_encoder = get_saved_enc(dev_priv, port, pipe);
862 if (!intel_encoder) {
863 DRM_DEBUG_KMS("Not valid for port %c\n", port_name(port));
864 mutex_unlock(&dev_priv->av_mutex);
865 return ret;
866 }
867
868 ret = 0;
869 *enabled = intel_encoder->audio_connector != NULL;
870 if (*enabled) {
871 eld = intel_encoder->audio_connector->eld;
872 ret = drm_eld_size(eld);
873 memcpy(buf, eld, min(max_bytes, ret));
874 }
875
876 mutex_unlock(&dev_priv->av_mutex);
877 return ret;
878 }
879
880 static const struct i915_audio_component_ops i915_audio_component_ops = {
881 .owner = THIS_MODULE,
882 .get_power = i915_audio_component_get_power,
883 .put_power = i915_audio_component_put_power,
884 .codec_wake_override = i915_audio_component_codec_wake_override,
885 .get_cdclk_freq = i915_audio_component_get_cdclk_freq,
886 .sync_audio_rate = i915_audio_component_sync_audio_rate,
887 .get_eld = i915_audio_component_get_eld,
888 };
889
i915_audio_component_bind(struct device * i915_kdev,struct device * hda_kdev,void * data)890 static int i915_audio_component_bind(struct device *i915_kdev,
891 struct device *hda_kdev, void *data)
892 {
893 struct i915_audio_component *acomp = data;
894 struct drm_i915_private *dev_priv = kdev_to_i915(i915_kdev);
895 int i;
896
897 if (WARN_ON(acomp->ops || acomp->dev))
898 return -EEXIST;
899
900 drm_modeset_lock_all(&dev_priv->drm);
901 acomp->ops = &i915_audio_component_ops;
902 acomp->dev = i915_kdev;
903 BUILD_BUG_ON(MAX_PORTS != I915_MAX_PORTS);
904 for (i = 0; i < ARRAY_SIZE(acomp->aud_sample_rate); i++)
905 acomp->aud_sample_rate[i] = 0;
906 dev_priv->audio_component = acomp;
907 drm_modeset_unlock_all(&dev_priv->drm);
908
909 return 0;
910 }
911
i915_audio_component_unbind(struct device * i915_kdev,struct device * hda_kdev,void * data)912 static void i915_audio_component_unbind(struct device *i915_kdev,
913 struct device *hda_kdev, void *data)
914 {
915 struct i915_audio_component *acomp = data;
916 struct drm_i915_private *dev_priv = kdev_to_i915(i915_kdev);
917
918 drm_modeset_lock_all(&dev_priv->drm);
919 acomp->ops = NULL;
920 acomp->dev = NULL;
921 dev_priv->audio_component = NULL;
922 drm_modeset_unlock_all(&dev_priv->drm);
923 }
924
925 static const struct component_ops i915_audio_component_bind_ops = {
926 .bind = i915_audio_component_bind,
927 .unbind = i915_audio_component_unbind,
928 };
929
930 /**
931 * i915_audio_component_init - initialize and register the audio component
932 * @dev_priv: i915 device instance
933 *
934 * This will register with the component framework a child component which
935 * will bind dynamically to the snd_hda_intel driver's corresponding master
936 * component when the latter is registered. During binding the child
937 * initializes an instance of struct i915_audio_component which it receives
938 * from the master. The master can then start to use the interface defined by
939 * this struct. Each side can break the binding at any point by deregistering
940 * its own component after which each side's component unbind callback is
941 * called.
942 *
943 * We ignore any error during registration and continue with reduced
944 * functionality (i.e. without HDMI audio).
945 */
i915_audio_component_init(struct drm_i915_private * dev_priv)946 void i915_audio_component_init(struct drm_i915_private *dev_priv)
947 {
948 int ret;
949
950 if (INTEL_INFO(dev_priv)->num_pipes == 0)
951 return;
952
953 ret = component_add(dev_priv->drm.dev, &i915_audio_component_bind_ops);
954 if (ret < 0) {
955 DRM_ERROR("failed to add audio component (%d)\n", ret);
956 /* continue with reduced functionality */
957 return;
958 }
959
960 dev_priv->audio_component_registered = true;
961 }
962
963 /**
964 * i915_audio_component_cleanup - deregister the audio component
965 * @dev_priv: i915 device instance
966 *
967 * Deregisters the audio component, breaking any existing binding to the
968 * corresponding snd_hda_intel driver's master component.
969 */
i915_audio_component_cleanup(struct drm_i915_private * dev_priv)970 void i915_audio_component_cleanup(struct drm_i915_private *dev_priv)
971 {
972 if (!dev_priv->audio_component_registered)
973 return;
974
975 component_del(dev_priv->drm.dev, &i915_audio_component_bind_ops);
976 dev_priv->audio_component_registered = false;
977 }
978
979 /**
980 * intel_audio_init() - Initialize the audio driver either using
981 * component framework or using lpe audio bridge
982 * @dev_priv: the i915 drm device private data
983 *
984 */
intel_audio_init(struct drm_i915_private * dev_priv)985 void intel_audio_init(struct drm_i915_private *dev_priv)
986 {
987 if (intel_lpe_audio_init(dev_priv) < 0)
988 i915_audio_component_init(dev_priv);
989 }
990
991 /**
992 * intel_audio_deinit() - deinitialize the audio driver
993 * @dev_priv: the i915 drm device private data
994 *
995 */
intel_audio_deinit(struct drm_i915_private * dev_priv)996 void intel_audio_deinit(struct drm_i915_private *dev_priv)
997 {
998 if ((dev_priv)->lpe_audio.platdev != NULL)
999 intel_lpe_audio_teardown(dev_priv);
1000 else
1001 i915_audio_component_cleanup(dev_priv);
1002 }
1003