1 /* 2 * Copyright © 2014 Intel Corporation 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice (including the next 12 * paragraph) shall be included in all copies or substantial portions of the 13 * Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS 21 * IN THE SOFTWARE. 22 */ 23 #ifndef _INTEL_GUC_FWIF_H 24 #define _INTEL_GUC_FWIF_H 25 26 #define GUC_CORE_FAMILY_GEN9 12 27 #define GUC_CORE_FAMILY_UNKNOWN 0x7fffffff 28 29 #define GUC_CLIENT_PRIORITY_KMD_HIGH 0 30 #define GUC_CLIENT_PRIORITY_HIGH 1 31 #define GUC_CLIENT_PRIORITY_KMD_NORMAL 2 32 #define GUC_CLIENT_PRIORITY_NORMAL 3 33 #define GUC_CLIENT_PRIORITY_NUM 4 34 35 #define GUC_MAX_STAGE_DESCRIPTORS 1024 36 #define GUC_INVALID_STAGE_ID GUC_MAX_STAGE_DESCRIPTORS 37 38 #define GUC_RENDER_ENGINE 0 39 #define GUC_VIDEO_ENGINE 1 40 #define GUC_BLITTER_ENGINE 2 41 #define GUC_VIDEOENHANCE_ENGINE 3 42 #define GUC_VIDEO_ENGINE2 4 43 #define GUC_MAX_ENGINES_NUM (GUC_VIDEO_ENGINE2 + 1) 44 45 /* Work queue item header definitions */ 46 #define WQ_STATUS_ACTIVE 1 47 #define WQ_STATUS_SUSPENDED 2 48 #define WQ_STATUS_CMD_ERROR 3 49 #define WQ_STATUS_ENGINE_ID_NOT_USED 4 50 #define WQ_STATUS_SUSPENDED_FROM_RESET 5 51 #define WQ_TYPE_SHIFT 0 52 #define WQ_TYPE_BATCH_BUF (0x1 << WQ_TYPE_SHIFT) 53 #define WQ_TYPE_PSEUDO (0x2 << WQ_TYPE_SHIFT) 54 #define WQ_TYPE_INORDER (0x3 << WQ_TYPE_SHIFT) 55 #define WQ_TARGET_SHIFT 10 56 #define WQ_LEN_SHIFT 16 57 #define WQ_NO_WCFLUSH_WAIT (1 << 27) 58 #define WQ_PRESENT_WORKLOAD (1 << 28) 59 #define WQ_WORKLOAD_SHIFT 29 60 #define WQ_WORKLOAD_GENERAL (0 << WQ_WORKLOAD_SHIFT) 61 #define WQ_WORKLOAD_GPGPU (1 << WQ_WORKLOAD_SHIFT) 62 #define WQ_WORKLOAD_TOUCH (2 << WQ_WORKLOAD_SHIFT) 63 64 #define WQ_RING_TAIL_SHIFT 20 65 #define WQ_RING_TAIL_MAX 0x7FF /* 2^11 QWords */ 66 #define WQ_RING_TAIL_MASK (WQ_RING_TAIL_MAX << WQ_RING_TAIL_SHIFT) 67 68 #define GUC_DOORBELL_ENABLED 1 69 #define GUC_DOORBELL_DISABLED 0 70 71 #define GUC_STAGE_DESC_ATTR_ACTIVE BIT(0) 72 #define GUC_STAGE_DESC_ATTR_PENDING_DB BIT(1) 73 #define GUC_STAGE_DESC_ATTR_KERNEL BIT(2) 74 #define GUC_STAGE_DESC_ATTR_PREEMPT BIT(3) 75 #define GUC_STAGE_DESC_ATTR_RESET BIT(4) 76 #define GUC_STAGE_DESC_ATTR_WQLOCKED BIT(5) 77 #define GUC_STAGE_DESC_ATTR_PCH BIT(6) 78 #define GUC_STAGE_DESC_ATTR_TERMINATED BIT(7) 79 80 /* The guc control data is 10 DWORDs */ 81 #define GUC_CTL_CTXINFO 0 82 #define GUC_CTL_CTXNUM_IN16_SHIFT 0 83 #define GUC_CTL_BASE_ADDR_SHIFT 12 84 85 #define GUC_CTL_ARAT_HIGH 1 86 #define GUC_CTL_ARAT_LOW 2 87 88 #define GUC_CTL_DEVICE_INFO 3 89 #define GUC_CTL_GTTYPE_SHIFT 0 90 #define GUC_CTL_COREFAMILY_SHIFT 7 91 92 #define GUC_CTL_LOG_PARAMS 4 93 #define GUC_LOG_VALID (1 << 0) 94 #define GUC_LOG_NOTIFY_ON_HALF_FULL (1 << 1) 95 #define GUC_LOG_ALLOC_IN_MEGABYTE (1 << 3) 96 #define GUC_LOG_CRASH_PAGES 1 97 #define GUC_LOG_CRASH_SHIFT 4 98 #define GUC_LOG_DPC_PAGES 7 99 #define GUC_LOG_DPC_SHIFT 6 100 #define GUC_LOG_ISR_PAGES 7 101 #define GUC_LOG_ISR_SHIFT 9 102 #define GUC_LOG_BUF_ADDR_SHIFT 12 103 104 #define GUC_CTL_PAGE_FAULT_CONTROL 5 105 106 #define GUC_CTL_WA 6 107 #define GUC_CTL_WA_UK_BY_DRIVER (1 << 3) 108 109 #define GUC_CTL_FEATURE 7 110 #define GUC_CTL_VCS2_ENABLED (1 << 0) 111 #define GUC_CTL_KERNEL_SUBMISSIONS (1 << 1) 112 #define GUC_CTL_FEATURE2 (1 << 2) 113 #define GUC_CTL_POWER_GATING (1 << 3) 114 #define GUC_CTL_DISABLE_SCHEDULER (1 << 4) 115 #define GUC_CTL_PREEMPTION_LOG (1 << 5) 116 #define GUC_CTL_ENABLE_SLPC (1 << 7) 117 #define GUC_CTL_RESET_ON_PREMPT_FAILURE (1 << 8) 118 119 #define GUC_CTL_DEBUG 8 120 #define GUC_LOG_VERBOSITY_SHIFT 0 121 #define GUC_LOG_VERBOSITY_LOW (0 << GUC_LOG_VERBOSITY_SHIFT) 122 #define GUC_LOG_VERBOSITY_MED (1 << GUC_LOG_VERBOSITY_SHIFT) 123 #define GUC_LOG_VERBOSITY_HIGH (2 << GUC_LOG_VERBOSITY_SHIFT) 124 #define GUC_LOG_VERBOSITY_ULTRA (3 << GUC_LOG_VERBOSITY_SHIFT) 125 /* Verbosity range-check limits, without the shift */ 126 #define GUC_LOG_VERBOSITY_MIN 0 127 #define GUC_LOG_VERBOSITY_MAX 3 128 #define GUC_LOG_VERBOSITY_MASK 0x0000000f 129 #define GUC_LOG_DESTINATION_MASK (3 << 4) 130 #define GUC_LOG_DISABLED (1 << 6) 131 #define GUC_PROFILE_ENABLED (1 << 7) 132 #define GUC_WQ_TRACK_ENABLED (1 << 8) 133 #define GUC_ADS_ENABLED (1 << 9) 134 #define GUC_DEBUG_RESERVED (1 << 10) 135 #define GUC_ADS_ADDR_SHIFT 11 136 #define GUC_ADS_ADDR_MASK 0xfffff800 137 138 #define GUC_CTL_RSRVD 9 139 140 #define GUC_CTL_MAX_DWORDS (SOFT_SCRATCH_COUNT - 2) /* [1..14] */ 141 142 /** 143 * DOC: GuC Firmware Layout 144 * 145 * The GuC firmware layout looks like this: 146 * 147 * +-------------------------------+ 148 * | uc_css_header | 149 * | | 150 * | contains major/minor version | 151 * +-------------------------------+ 152 * | uCode | 153 * +-------------------------------+ 154 * | RSA signature | 155 * +-------------------------------+ 156 * | modulus key | 157 * +-------------------------------+ 158 * | exponent val | 159 * +-------------------------------+ 160 * 161 * The firmware may or may not have modulus key and exponent data. The header, 162 * uCode and RSA signature are must-have components that will be used by driver. 163 * Length of each components, which is all in dwords, can be found in header. 164 * In the case that modulus and exponent are not present in fw, a.k.a truncated 165 * image, the length value still appears in header. 166 * 167 * Driver will do some basic fw size validation based on the following rules: 168 * 169 * 1. Header, uCode and RSA are must-have components. 170 * 2. All firmware components, if they present, are in the sequence illustrated 171 * in the layout table above. 172 * 3. Length info of each component can be found in header, in dwords. 173 * 4. Modulus and exponent key are not required by driver. They may not appear 174 * in fw. So driver will load a truncated firmware in this case. 175 * 176 * HuC firmware layout is same as GuC firmware. 177 * 178 * HuC firmware css header is different. However, the only difference is where 179 * the version information is saved. The uc_css_header is unified to support 180 * both. Driver should get HuC version from uc_css_header.huc_sw_version, while 181 * uc_css_header.guc_sw_version for GuC. 182 */ 183 184 struct uc_css_header { 185 uint32_t module_type; 186 /* header_size includes all non-uCode bits, including css_header, rsa 187 * key, modulus key and exponent data. */ 188 uint32_t header_size_dw; 189 uint32_t header_version; 190 uint32_t module_id; 191 uint32_t module_vendor; 192 union { 193 struct { 194 uint8_t day; 195 uint8_t month; 196 uint16_t year; 197 }; 198 uint32_t date; 199 }; 200 uint32_t size_dw; /* uCode plus header_size_dw */ 201 uint32_t key_size_dw; 202 uint32_t modulus_size_dw; 203 uint32_t exponent_size_dw; 204 union { 205 struct { 206 uint8_t hour; 207 uint8_t min; 208 uint16_t sec; 209 }; 210 uint32_t time; 211 }; 212 213 char username[8]; 214 char buildnumber[12]; 215 union { 216 struct { 217 uint32_t branch_client_version; 218 uint32_t sw_version; 219 } guc; 220 struct { 221 uint32_t sw_version; 222 uint32_t reserved; 223 } huc; 224 }; 225 uint32_t prod_preprod_fw; 226 uint32_t reserved[12]; 227 uint32_t header_info; 228 } __packed; 229 230 struct guc_doorbell_info { 231 u32 db_status; 232 u32 cookie; 233 u32 reserved[14]; 234 } __packed; 235 236 union guc_doorbell_qw { 237 struct { 238 u32 db_status; 239 u32 cookie; 240 }; 241 u64 value_qw; 242 } __packed; 243 244 #define GUC_NUM_DOORBELLS 256 245 #define GUC_DOORBELL_INVALID (GUC_NUM_DOORBELLS) 246 247 #define GUC_DB_SIZE (PAGE_SIZE) 248 #define GUC_WQ_SIZE (PAGE_SIZE * 2) 249 250 /* Work item for submitting workloads into work queue of GuC. */ 251 struct guc_wq_item { 252 u32 header; 253 u32 context_desc; 254 u32 submit_element_info; 255 u32 fence_id; 256 } __packed; 257 258 struct guc_process_desc { 259 u32 stage_id; 260 u64 db_base_addr; 261 u32 head; 262 u32 tail; 263 u32 error_offset; 264 u64 wq_base_addr; 265 u32 wq_size_bytes; 266 u32 wq_status; 267 u32 engine_presence; 268 u32 priority; 269 u32 reserved[30]; 270 } __packed; 271 272 /* engine id and context id is packed into guc_execlist_context.context_id*/ 273 #define GUC_ELC_CTXID_OFFSET 0 274 #define GUC_ELC_ENGINE_OFFSET 29 275 276 /* The execlist context including software and HW information */ 277 struct guc_execlist_context { 278 u32 context_desc; 279 u32 context_id; 280 u32 ring_status; 281 u32 ring_lrca; 282 u32 ring_begin; 283 u32 ring_end; 284 u32 ring_next_free_location; 285 u32 ring_current_tail_pointer_value; 286 u8 engine_state_submit_value; 287 u8 engine_state_wait_value; 288 u16 pagefault_count; 289 u16 engine_submit_queue_count; 290 } __packed; 291 292 /* 293 * This structure describes a stage set arranged for a particular communication 294 * between uKernel (GuC) and Driver (KMD). Technically, this is known as a 295 * "GuC Context descriptor" in the specs, but we use the term "stage descriptor" 296 * to avoid confusion with all the other things already named "context" in the 297 * driver. A static pool of these descriptors are stored inside a GEM object 298 * (stage_desc_pool) which is held for the entire lifetime of our interaction 299 * with the GuC, being allocated before the GuC is loaded with its firmware. 300 */ 301 struct guc_stage_desc { 302 u32 sched_common_area; 303 u32 stage_id; 304 u32 pas_id; 305 u8 engines_used; 306 u64 db_trigger_cpu; 307 u32 db_trigger_uk; 308 u64 db_trigger_phy; 309 u16 db_id; 310 311 struct guc_execlist_context lrc[GUC_MAX_ENGINES_NUM]; 312 313 u8 attribute; 314 315 u32 priority; 316 317 u32 wq_sampled_tail_offset; 318 u32 wq_total_submit_enqueues; 319 320 u32 process_desc; 321 u32 wq_addr; 322 u32 wq_size; 323 324 u32 engine_presence; 325 326 u8 engine_suspended; 327 328 u8 reserved0[3]; 329 u64 reserved1[1]; 330 331 u64 desc_private; 332 } __packed; 333 334 /* 335 * Describes single command transport buffer. 336 * Used by both guc-master and clients. 337 */ 338 struct guc_ct_buffer_desc { 339 u32 addr; /* gfx address */ 340 u64 host_private; /* host private data */ 341 u32 size; /* size in bytes */ 342 u32 head; /* offset updated by GuC*/ 343 u32 tail; /* offset updated by owner */ 344 u32 is_in_error; /* error indicator */ 345 u32 fence; /* fence updated by GuC */ 346 u32 status; /* status updated by GuC */ 347 u32 owner; /* id of the channel owner */ 348 u32 owner_sub_id; /* owner-defined field for extra tracking */ 349 u32 reserved[5]; 350 } __packed; 351 352 /* Type of command transport buffer */ 353 #define INTEL_GUC_CT_BUFFER_TYPE_SEND 0x0u 354 #define INTEL_GUC_CT_BUFFER_TYPE_RECV 0x1u 355 356 /* 357 * Definition of the command transport message header (DW0) 358 * 359 * bit[4..0] message len (in dwords) 360 * bit[7..5] reserved 361 * bit[8] write fence to desc 362 * bit[9] write status to H2G buff 363 * bit[10] send status (via G2H) 364 * bit[15..11] reserved 365 * bit[31..16] action code 366 */ 367 #define GUC_CT_MSG_LEN_SHIFT 0 368 #define GUC_CT_MSG_LEN_MASK 0x1F 369 #define GUC_CT_MSG_WRITE_FENCE_TO_DESC (1 << 8) 370 #define GUC_CT_MSG_WRITE_STATUS_TO_BUFF (1 << 9) 371 #define GUC_CT_MSG_SEND_STATUS (1 << 10) 372 #define GUC_CT_MSG_ACTION_SHIFT 16 373 #define GUC_CT_MSG_ACTION_MASK 0xFFFF 374 375 #define GUC_FORCEWAKE_RENDER (1 << 0) 376 #define GUC_FORCEWAKE_MEDIA (1 << 1) 377 378 #define GUC_POWER_UNSPECIFIED 0 379 #define GUC_POWER_D0 1 380 #define GUC_POWER_D1 2 381 #define GUC_POWER_D2 3 382 #define GUC_POWER_D3 4 383 384 /* Scheduling policy settings */ 385 386 /* Reset engine upon preempt failure */ 387 #define POLICY_RESET_ENGINE (1<<0) 388 /* Preempt to idle on quantum expiry */ 389 #define POLICY_PREEMPT_TO_IDLE (1<<1) 390 391 #define POLICY_MAX_NUM_WI 15 392 393 struct guc_policy { 394 /* Time for one workload to execute. (in micro seconds) */ 395 u32 execution_quantum; 396 u32 reserved1; 397 398 /* Time to wait for a preemption request to completed before issuing a 399 * reset. (in micro seconds). */ 400 u32 preemption_time; 401 402 /* How much time to allow to run after the first fault is observed. 403 * Then preempt afterwards. (in micro seconds) */ 404 u32 fault_time; 405 406 u32 policy_flags; 407 u32 reserved[2]; 408 } __packed; 409 410 struct guc_policies { 411 struct guc_policy policy[GUC_CLIENT_PRIORITY_NUM][GUC_MAX_ENGINES_NUM]; 412 413 /* In micro seconds. How much time to allow before DPC processing is 414 * called back via interrupt (to prevent DPC queue drain starving). 415 * Typically 1000s of micro seconds (example only, not granularity). */ 416 u32 dpc_promote_time; 417 418 /* Must be set to take these new values. */ 419 u32 is_valid; 420 421 /* Max number of WIs to process per call. A large value may keep CS 422 * idle. */ 423 u32 max_num_work_items; 424 425 u32 reserved[19]; 426 } __packed; 427 428 /* GuC MMIO reg state struct */ 429 430 #define GUC_REGSET_FLAGS_NONE 0x0 431 #define GUC_REGSET_POWERCYCLE 0x1 432 #define GUC_REGSET_MASKED 0x2 433 #define GUC_REGSET_ENGINERESET 0x4 434 #define GUC_REGSET_SAVE_DEFAULT_VALUE 0x8 435 #define GUC_REGSET_SAVE_CURRENT_VALUE 0x10 436 437 #define GUC_REGSET_MAX_REGISTERS 25 438 #define GUC_MMIO_WHITE_LIST_START 0x24d0 439 #define GUC_MMIO_WHITE_LIST_MAX 12 440 #define GUC_S3_SAVE_SPACE_PAGES 10 441 442 struct guc_mmio_regset { 443 struct __packed { 444 u32 offset; 445 u32 value; 446 u32 flags; 447 } registers[GUC_REGSET_MAX_REGISTERS]; 448 449 u32 values_valid; 450 u32 number_of_registers; 451 } __packed; 452 453 /* MMIO registers that are set as non privileged */ 454 struct mmio_white_list { 455 u32 mmio_start; 456 u32 offsets[GUC_MMIO_WHITE_LIST_MAX]; 457 u32 count; 458 } __packed; 459 460 struct guc_mmio_reg_state { 461 struct guc_mmio_regset global_reg; 462 struct guc_mmio_regset engine_reg[GUC_MAX_ENGINES_NUM]; 463 struct mmio_white_list white_list[GUC_MAX_ENGINES_NUM]; 464 } __packed; 465 466 /* GuC Additional Data Struct */ 467 468 struct guc_ads { 469 u32 reg_state_addr; 470 u32 reg_state_buffer; 471 u32 golden_context_lrca; 472 u32 scheduler_policies; 473 u32 reserved0[3]; 474 u32 eng_state_size[GUC_MAX_ENGINES_NUM]; 475 u32 reserved2[4]; 476 } __packed; 477 478 /* GuC logging structures */ 479 480 enum guc_log_buffer_type { 481 GUC_ISR_LOG_BUFFER, 482 GUC_DPC_LOG_BUFFER, 483 GUC_CRASH_DUMP_LOG_BUFFER, 484 GUC_MAX_LOG_BUFFER 485 }; 486 487 /** 488 * DOC: GuC Log buffer Layout 489 * 490 * Page0 +-------------------------------+ 491 * | ISR state header (32 bytes) | 492 * | DPC state header | 493 * | Crash dump state header | 494 * Page1 +-------------------------------+ 495 * | ISR logs | 496 * Page9 +-------------------------------+ 497 * | DPC logs | 498 * Page17 +-------------------------------+ 499 * | Crash Dump logs | 500 * +-------------------------------+ 501 * 502 * Below state structure is used for coordination of retrieval of GuC firmware 503 * logs. Separate state is maintained for each log buffer type. 504 * read_ptr points to the location where i915 read last in log buffer and 505 * is read only for GuC firmware. write_ptr is incremented by GuC with number 506 * of bytes written for each log entry and is read only for i915. 507 * When any type of log buffer becomes half full, GuC sends a flush interrupt. 508 * GuC firmware expects that while it is writing to 2nd half of the buffer, 509 * first half would get consumed by Host and then get a flush completed 510 * acknowledgment from Host, so that it does not end up doing any overwrite 511 * causing loss of logs. So when buffer gets half filled & i915 has requested 512 * for interrupt, GuC will set flush_to_file field, set the sampled_write_ptr 513 * to the value of write_ptr and raise the interrupt. 514 * On receiving the interrupt i915 should read the buffer, clear flush_to_file 515 * field and also update read_ptr with the value of sample_write_ptr, before 516 * sending an acknowledgment to GuC. marker & version fields are for internal 517 * usage of GuC and opaque to i915. buffer_full_cnt field is incremented every 518 * time GuC detects the log buffer overflow. 519 */ 520 struct guc_log_buffer_state { 521 u32 marker[2]; 522 u32 read_ptr; 523 u32 write_ptr; 524 u32 size; 525 u32 sampled_write_ptr; 526 union { 527 struct { 528 u32 flush_to_file:1; 529 u32 buffer_full_cnt:4; 530 u32 reserved:27; 531 }; 532 u32 flags; 533 }; 534 u32 version; 535 } __packed; 536 537 union guc_log_control { 538 struct { 539 u32 logging_enabled:1; 540 u32 reserved1:3; 541 u32 verbosity:4; 542 u32 reserved2:24; 543 }; 544 u32 value; 545 } __packed; 546 547 /* This Action will be programmed in C180 - SOFT_SCRATCH_O_REG */ 548 enum intel_guc_action { 549 INTEL_GUC_ACTION_DEFAULT = 0x0, 550 INTEL_GUC_ACTION_SAMPLE_FORCEWAKE = 0x6, 551 INTEL_GUC_ACTION_ALLOCATE_DOORBELL = 0x10, 552 INTEL_GUC_ACTION_DEALLOCATE_DOORBELL = 0x20, 553 INTEL_GUC_ACTION_LOG_BUFFER_FILE_FLUSH_COMPLETE = 0x30, 554 INTEL_GUC_ACTION_FORCE_LOG_BUFFER_FLUSH = 0x302, 555 INTEL_GUC_ACTION_ENTER_S_STATE = 0x501, 556 INTEL_GUC_ACTION_EXIT_S_STATE = 0x502, 557 INTEL_GUC_ACTION_SLPC_REQUEST = 0x3003, 558 INTEL_GUC_ACTION_AUTHENTICATE_HUC = 0x4000, 559 INTEL_GUC_ACTION_REGISTER_COMMAND_TRANSPORT_BUFFER = 0x4505, 560 INTEL_GUC_ACTION_DEREGISTER_COMMAND_TRANSPORT_BUFFER = 0x4506, 561 INTEL_GUC_ACTION_UK_LOG_ENABLE_LOGGING = 0x0E000, 562 INTEL_GUC_ACTION_LIMIT 563 }; 564 565 /* 566 * The GuC sends its response to a command by overwriting the 567 * command in SS0. The response is distinguishable from a command 568 * by the fact that all the MASK bits are set. The remaining bits 569 * give more detail. 570 */ 571 #define INTEL_GUC_RECV_MASK ((u32)0xF0000000) 572 #define INTEL_GUC_RECV_IS_RESPONSE(x) ((u32)(x) >= INTEL_GUC_RECV_MASK) 573 #define INTEL_GUC_RECV_STATUS(x) (INTEL_GUC_RECV_MASK | (x)) 574 575 /* GUC will return status back to SOFT_SCRATCH_O_REG */ 576 enum intel_guc_status { 577 INTEL_GUC_STATUS_SUCCESS = INTEL_GUC_RECV_STATUS(0x0), 578 INTEL_GUC_STATUS_ALLOCATE_DOORBELL_FAIL = INTEL_GUC_RECV_STATUS(0x10), 579 INTEL_GUC_STATUS_DEALLOCATE_DOORBELL_FAIL = INTEL_GUC_RECV_STATUS(0x20), 580 INTEL_GUC_STATUS_GENERIC_FAIL = INTEL_GUC_RECV_STATUS(0x0000F000) 581 }; 582 583 /* This action will be programmed in C1BC - SOFT_SCRATCH_15_REG */ 584 enum intel_guc_recv_message { 585 INTEL_GUC_RECV_MSG_CRASH_DUMP_POSTED = BIT(1), 586 INTEL_GUC_RECV_MSG_FLUSH_LOG_BUFFER = BIT(3) 587 }; 588 589 #endif 590