1 /*
2 * Copyright © 2016-2017 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21 * IN THE SOFTWARE.
22 *
23 */
24 #include <linux/firmware.h>
25 #include "i915_drv.h"
26 #include "intel_uc.h"
27
28 /**
29 * DOC: HuC Firmware
30 *
31 * Motivation:
32 * GEN9 introduces a new dedicated firmware for usage in media HEVC (High
33 * Efficiency Video Coding) operations. Userspace can use the firmware
34 * capabilities by adding HuC specific commands to batch buffers.
35 *
36 * Implementation:
37 * The same firmware loader is used as the GuC. However, the actual
38 * loading to HW is deferred until GEM initialization is done.
39 *
40 * Note that HuC firmware loading must be done before GuC loading.
41 */
42
43 #define BXT_HUC_FW_MAJOR 01
44 #define BXT_HUC_FW_MINOR 07
45 #define BXT_BLD_NUM 1398
46
47 #define SKL_HUC_FW_MAJOR 01
48 #define SKL_HUC_FW_MINOR 07
49 #define SKL_BLD_NUM 1398
50
51 #define KBL_HUC_FW_MAJOR 02
52 #define KBL_HUC_FW_MINOR 00
53 #define KBL_BLD_NUM 1810
54
55 #define HUC_FW_PATH(platform, major, minor, bld_num) \
56 "i915/" __stringify(platform) "_huc_ver" __stringify(major) "_" \
57 __stringify(minor) "_" __stringify(bld_num) ".bin"
58
59 #define I915_SKL_HUC_UCODE HUC_FW_PATH(skl, SKL_HUC_FW_MAJOR, \
60 SKL_HUC_FW_MINOR, SKL_BLD_NUM)
61 MODULE_FIRMWARE(I915_SKL_HUC_UCODE);
62
63 #define I915_BXT_HUC_UCODE HUC_FW_PATH(bxt, BXT_HUC_FW_MAJOR, \
64 BXT_HUC_FW_MINOR, BXT_BLD_NUM)
65 MODULE_FIRMWARE(I915_BXT_HUC_UCODE);
66
67 #define I915_KBL_HUC_UCODE HUC_FW_PATH(kbl, KBL_HUC_FW_MAJOR, \
68 KBL_HUC_FW_MINOR, KBL_BLD_NUM)
69 MODULE_FIRMWARE(I915_KBL_HUC_UCODE);
70
71 /**
72 * huc_ucode_xfer() - DMA's the firmware
73 * @dev_priv: the drm_i915_private device
74 *
75 * Transfer the firmware image to RAM for execution by the microcontroller.
76 *
77 * Return: 0 on success, non-zero on failure
78 */
huc_ucode_xfer(struct drm_i915_private * dev_priv)79 static int huc_ucode_xfer(struct drm_i915_private *dev_priv)
80 {
81 struct intel_uc_fw *huc_fw = &dev_priv->huc.fw;
82 struct i915_vma *vma;
83 unsigned long offset = 0;
84 u32 size;
85 int ret;
86
87 ret = i915_gem_object_set_to_gtt_domain(huc_fw->obj, false);
88 if (ret) {
89 DRM_DEBUG_DRIVER("set-domain failed %d\n", ret);
90 return ret;
91 }
92
93 vma = i915_gem_object_ggtt_pin(huc_fw->obj, NULL, 0, 0,
94 PIN_OFFSET_BIAS | GUC_WOPCM_TOP);
95 if (IS_ERR(vma)) {
96 DRM_DEBUG_DRIVER("pin failed %d\n", (int)PTR_ERR(vma));
97 return PTR_ERR(vma);
98 }
99
100 intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
101
102 /* Set the source address for the uCode */
103 offset = guc_ggtt_offset(vma) + huc_fw->header_offset;
104 I915_WRITE(DMA_ADDR_0_LOW, lower_32_bits(offset));
105 I915_WRITE(DMA_ADDR_0_HIGH, upper_32_bits(offset) & 0xFFFF);
106
107 /* Hardware doesn't look at destination address for HuC. Set it to 0,
108 * but still program the correct address space.
109 */
110 I915_WRITE(DMA_ADDR_1_LOW, 0);
111 I915_WRITE(DMA_ADDR_1_HIGH, DMA_ADDRESS_SPACE_WOPCM);
112
113 size = huc_fw->header_size + huc_fw->ucode_size;
114 I915_WRITE(DMA_COPY_SIZE, size);
115
116 /* Start the DMA */
117 I915_WRITE(DMA_CTRL, _MASKED_BIT_ENABLE(HUC_UKERNEL | START_DMA));
118
119 /* Wait for DMA to finish */
120 ret = wait_for((I915_READ(DMA_CTRL) & START_DMA) == 0, 100);
121
122 DRM_DEBUG_DRIVER("HuC DMA transfer wait over with ret %d\n", ret);
123
124 /* Disable the bits once DMA is over */
125 I915_WRITE(DMA_CTRL, _MASKED_BIT_DISABLE(HUC_UKERNEL));
126
127 intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
128
129 /*
130 * We keep the object pages for reuse during resume. But we can unpin it
131 * now that DMA has completed, so it doesn't continue to take up space.
132 */
133 i915_vma_unpin(vma);
134
135 return ret;
136 }
137
138 /**
139 * intel_huc_select_fw() - selects HuC firmware for loading
140 * @huc: intel_huc struct
141 */
intel_huc_select_fw(struct intel_huc * huc)142 void intel_huc_select_fw(struct intel_huc *huc)
143 {
144 struct drm_i915_private *dev_priv = huc_to_i915(huc);
145
146 huc->fw.path = NULL;
147 huc->fw.fetch_status = INTEL_UC_FIRMWARE_NONE;
148 huc->fw.load_status = INTEL_UC_FIRMWARE_NONE;
149 huc->fw.type = INTEL_UC_FW_TYPE_HUC;
150
151 if (i915.huc_firmware_path) {
152 huc->fw.path = i915.huc_firmware_path;
153 huc->fw.major_ver_wanted = 0;
154 huc->fw.minor_ver_wanted = 0;
155 } else if (IS_SKYLAKE(dev_priv)) {
156 huc->fw.path = I915_SKL_HUC_UCODE;
157 huc->fw.major_ver_wanted = SKL_HUC_FW_MAJOR;
158 huc->fw.minor_ver_wanted = SKL_HUC_FW_MINOR;
159 } else if (IS_BROXTON(dev_priv)) {
160 huc->fw.path = I915_BXT_HUC_UCODE;
161 huc->fw.major_ver_wanted = BXT_HUC_FW_MAJOR;
162 huc->fw.minor_ver_wanted = BXT_HUC_FW_MINOR;
163 } else if (IS_KABYLAKE(dev_priv) || IS_COFFEELAKE(dev_priv)) {
164 huc->fw.path = I915_KBL_HUC_UCODE;
165 huc->fw.major_ver_wanted = KBL_HUC_FW_MAJOR;
166 huc->fw.minor_ver_wanted = KBL_HUC_FW_MINOR;
167 } else {
168 DRM_ERROR("No HuC firmware known for platform with HuC!\n");
169 return;
170 }
171 }
172
173 /**
174 * intel_huc_init_hw() - load HuC uCode to device
175 * @huc: intel_huc structure
176 *
177 * Called from guc_setup() during driver loading and also after a GPU reset.
178 * Be note that HuC loading must be done before GuC loading.
179 *
180 * The firmware image should have already been fetched into memory by the
181 * earlier call to intel_huc_init(), so here we need only check that
182 * is succeeded, and then transfer the image to the h/w.
183 *
184 */
intel_huc_init_hw(struct intel_huc * huc)185 void intel_huc_init_hw(struct intel_huc *huc)
186 {
187 struct drm_i915_private *dev_priv = huc_to_i915(huc);
188 int err;
189
190 DRM_DEBUG_DRIVER("%s fw status: fetch %s, load %s\n",
191 huc->fw.path,
192 intel_uc_fw_status_repr(huc->fw.fetch_status),
193 intel_uc_fw_status_repr(huc->fw.load_status));
194
195 if (huc->fw.fetch_status != INTEL_UC_FIRMWARE_SUCCESS)
196 return;
197
198 huc->fw.load_status = INTEL_UC_FIRMWARE_PENDING;
199
200 err = huc_ucode_xfer(dev_priv);
201
202 huc->fw.load_status = err ?
203 INTEL_UC_FIRMWARE_FAIL : INTEL_UC_FIRMWARE_SUCCESS;
204
205 DRM_DEBUG_DRIVER("%s fw status: fetch %s, load %s\n",
206 huc->fw.path,
207 intel_uc_fw_status_repr(huc->fw.fetch_status),
208 intel_uc_fw_status_repr(huc->fw.load_status));
209
210 if (huc->fw.load_status != INTEL_UC_FIRMWARE_SUCCESS)
211 DRM_ERROR("Failed to complete HuC uCode load with ret %d\n", err);
212
213 return;
214 }
215
216 /**
217 * intel_guc_auth_huc() - authenticate ucode
218 * @dev_priv: the drm_i915_device
219 *
220 * Triggers a HuC fw authentication request to the GuC via intel_guc_action_
221 * authenticate_huc interface.
222 */
intel_guc_auth_huc(struct drm_i915_private * dev_priv)223 void intel_guc_auth_huc(struct drm_i915_private *dev_priv)
224 {
225 struct intel_guc *guc = &dev_priv->guc;
226 struct intel_huc *huc = &dev_priv->huc;
227 struct i915_vma *vma;
228 int ret;
229 u32 data[2];
230
231 if (huc->fw.load_status != INTEL_UC_FIRMWARE_SUCCESS)
232 return;
233
234 vma = i915_gem_object_ggtt_pin(huc->fw.obj, NULL, 0, 0,
235 PIN_OFFSET_BIAS | GUC_WOPCM_TOP);
236 if (IS_ERR(vma)) {
237 DRM_ERROR("failed to pin huc fw object %d\n",
238 (int)PTR_ERR(vma));
239 return;
240 }
241
242 /* Specify auth action and where public signature is. */
243 data[0] = INTEL_GUC_ACTION_AUTHENTICATE_HUC;
244 data[1] = guc_ggtt_offset(vma) + huc->fw.rsa_offset;
245
246 ret = intel_guc_send(guc, data, ARRAY_SIZE(data));
247 if (ret) {
248 DRM_ERROR("HuC: GuC did not ack Auth request %d\n", ret);
249 goto out;
250 }
251
252 /* Check authentication status, it should be done by now */
253 ret = intel_wait_for_register(dev_priv,
254 HUC_STATUS2,
255 HUC_FW_VERIFIED,
256 HUC_FW_VERIFIED,
257 50);
258
259 if (ret) {
260 DRM_ERROR("HuC: Authentication failed %d\n", ret);
261 goto out;
262 }
263
264 out:
265 i915_vma_unpin(vma);
266 }
267
268