1 /*
2 * Copyright © 2014 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
21 * DEALINGS IN THE SOFTWARE.
22 */
23
24 /**
25 * DOC: Panel Self Refresh (PSR/SRD)
26 *
27 * Since Haswell Display controller supports Panel Self-Refresh on display
28 * panels witch have a remote frame buffer (RFB) implemented according to PSR
29 * spec in eDP1.3. PSR feature allows the display to go to lower standby states
30 * when system is idle but display is on as it eliminates display refresh
31 * request to DDR memory completely as long as the frame buffer for that
32 * display is unchanged.
33 *
34 * Panel Self Refresh must be supported by both Hardware (source) and
35 * Panel (sink).
36 *
37 * PSR saves power by caching the framebuffer in the panel RFB, which allows us
38 * to power down the link and memory controller. For DSI panels the same idea
39 * is called "manual mode".
40 *
41 * The implementation uses the hardware-based PSR support which automatically
42 * enters/exits self-refresh mode. The hardware takes care of sending the
43 * required DP aux message and could even retrain the link (that part isn't
44 * enabled yet though). The hardware also keeps track of any frontbuffer
45 * changes to know when to exit self-refresh mode again. Unfortunately that
46 * part doesn't work too well, hence why the i915 PSR support uses the
47 * software frontbuffer tracking to make sure it doesn't miss a screen
48 * update. For this integration intel_psr_invalidate() and intel_psr_flush()
49 * get called by the frontbuffer tracking code. Note that because of locking
50 * issues the self-refresh re-enable code is done from a work queue, which
51 * must be correctly synchronized/cancelled when shutting down the pipe."
52 */
53
54 #include <drm/drmP.h>
55
56 #include "intel_drv.h"
57 #include "i915_drv.h"
58
is_edp_psr(struct intel_dp * intel_dp)59 static bool is_edp_psr(struct intel_dp *intel_dp)
60 {
61 return intel_dp->psr_dpcd[0] & DP_PSR_IS_SUPPORTED;
62 }
63
vlv_is_psr_active_on_pipe(struct drm_device * dev,int pipe)64 static bool vlv_is_psr_active_on_pipe(struct drm_device *dev, int pipe)
65 {
66 struct drm_i915_private *dev_priv = to_i915(dev);
67 uint32_t val;
68
69 val = I915_READ(VLV_PSRSTAT(pipe)) &
70 VLV_EDP_PSR_CURR_STATE_MASK;
71 return (val == VLV_EDP_PSR_ACTIVE_NORFB_UP) ||
72 (val == VLV_EDP_PSR_ACTIVE_SF_UPDATE);
73 }
74
intel_psr_write_vsc(struct intel_dp * intel_dp,const struct edp_vsc_psr * vsc_psr)75 static void intel_psr_write_vsc(struct intel_dp *intel_dp,
76 const struct edp_vsc_psr *vsc_psr)
77 {
78 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
79 struct drm_device *dev = dig_port->base.base.dev;
80 struct drm_i915_private *dev_priv = to_i915(dev);
81 struct intel_crtc *crtc = to_intel_crtc(dig_port->base.base.crtc);
82 enum transcoder cpu_transcoder = crtc->config->cpu_transcoder;
83 i915_reg_t ctl_reg = HSW_TVIDEO_DIP_CTL(cpu_transcoder);
84 uint32_t *data = (uint32_t *) vsc_psr;
85 unsigned int i;
86
87 /* As per BSPec (Pipe Video Data Island Packet), we need to disable
88 the video DIP being updated before program video DIP data buffer
89 registers for DIP being updated. */
90 I915_WRITE(ctl_reg, 0);
91 POSTING_READ(ctl_reg);
92
93 for (i = 0; i < sizeof(*vsc_psr); i += 4) {
94 I915_WRITE(HSW_TVIDEO_DIP_VSC_DATA(cpu_transcoder,
95 i >> 2), *data);
96 data++;
97 }
98 for (; i < VIDEO_DIP_VSC_DATA_SIZE; i += 4)
99 I915_WRITE(HSW_TVIDEO_DIP_VSC_DATA(cpu_transcoder,
100 i >> 2), 0);
101
102 I915_WRITE(ctl_reg, VIDEO_DIP_ENABLE_VSC_HSW);
103 POSTING_READ(ctl_reg);
104 }
105
vlv_psr_setup_vsc(struct intel_dp * intel_dp)106 static void vlv_psr_setup_vsc(struct intel_dp *intel_dp)
107 {
108 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
109 struct drm_device *dev = intel_dig_port->base.base.dev;
110 struct drm_i915_private *dev_priv = to_i915(dev);
111 struct drm_crtc *crtc = intel_dig_port->base.base.crtc;
112 enum pipe pipe = to_intel_crtc(crtc)->pipe;
113 uint32_t val;
114
115 /* VLV auto-generate VSC package as per EDP 1.3 spec, Table 3.10 */
116 val = I915_READ(VLV_VSCSDP(pipe));
117 val &= ~VLV_EDP_PSR_SDP_FREQ_MASK;
118 val |= VLV_EDP_PSR_SDP_FREQ_EVFRAME;
119 I915_WRITE(VLV_VSCSDP(pipe), val);
120 }
121
skl_psr_setup_su_vsc(struct intel_dp * intel_dp)122 static void skl_psr_setup_su_vsc(struct intel_dp *intel_dp)
123 {
124 struct edp_vsc_psr psr_vsc;
125 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
126 struct drm_device *dev = intel_dig_port->base.base.dev;
127 struct drm_i915_private *dev_priv = to_i915(dev);
128
129 /* Prepare VSC Header for SU as per EDP 1.4 spec, Table 6.11 */
130 memset(&psr_vsc, 0, sizeof(psr_vsc));
131 psr_vsc.sdp_header.HB0 = 0;
132 psr_vsc.sdp_header.HB1 = 0x7;
133 if (dev_priv->psr.colorimetry_support &&
134 dev_priv->psr.y_cord_support) {
135 psr_vsc.sdp_header.HB2 = 0x5;
136 psr_vsc.sdp_header.HB3 = 0x13;
137 } else if (dev_priv->psr.y_cord_support) {
138 psr_vsc.sdp_header.HB2 = 0x4;
139 psr_vsc.sdp_header.HB3 = 0xe;
140 } else {
141 psr_vsc.sdp_header.HB2 = 0x3;
142 psr_vsc.sdp_header.HB3 = 0xc;
143 }
144
145 intel_psr_write_vsc(intel_dp, &psr_vsc);
146 }
147
hsw_psr_setup_vsc(struct intel_dp * intel_dp)148 static void hsw_psr_setup_vsc(struct intel_dp *intel_dp)
149 {
150 struct edp_vsc_psr psr_vsc;
151
152 /* Prepare VSC packet as per EDP 1.3 spec, Table 3.10 */
153 memset(&psr_vsc, 0, sizeof(psr_vsc));
154 psr_vsc.sdp_header.HB0 = 0;
155 psr_vsc.sdp_header.HB1 = 0x7;
156 psr_vsc.sdp_header.HB2 = 0x2;
157 psr_vsc.sdp_header.HB3 = 0x8;
158 intel_psr_write_vsc(intel_dp, &psr_vsc);
159 }
160
vlv_psr_enable_sink(struct intel_dp * intel_dp)161 static void vlv_psr_enable_sink(struct intel_dp *intel_dp)
162 {
163 drm_dp_dpcd_writeb(&intel_dp->aux, DP_PSR_EN_CFG,
164 DP_PSR_ENABLE | DP_PSR_MAIN_LINK_ACTIVE);
165 }
166
psr_aux_ctl_reg(struct drm_i915_private * dev_priv,enum port port)167 static i915_reg_t psr_aux_ctl_reg(struct drm_i915_private *dev_priv,
168 enum port port)
169 {
170 if (INTEL_INFO(dev_priv)->gen >= 9)
171 return DP_AUX_CH_CTL(port);
172 else
173 return EDP_PSR_AUX_CTL;
174 }
175
psr_aux_data_reg(struct drm_i915_private * dev_priv,enum port port,int index)176 static i915_reg_t psr_aux_data_reg(struct drm_i915_private *dev_priv,
177 enum port port, int index)
178 {
179 if (INTEL_INFO(dev_priv)->gen >= 9)
180 return DP_AUX_CH_DATA(port, index);
181 else
182 return EDP_PSR_AUX_DATA(index);
183 }
184
hsw_psr_enable_sink(struct intel_dp * intel_dp)185 static void hsw_psr_enable_sink(struct intel_dp *intel_dp)
186 {
187 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
188 struct drm_device *dev = dig_port->base.base.dev;
189 struct drm_i915_private *dev_priv = to_i915(dev);
190 uint32_t aux_clock_divider;
191 i915_reg_t aux_ctl_reg;
192 static const uint8_t aux_msg[] = {
193 [0] = DP_AUX_NATIVE_WRITE << 4,
194 [1] = DP_SET_POWER >> 8,
195 [2] = DP_SET_POWER & 0xff,
196 [3] = 1 - 1,
197 [4] = DP_SET_POWER_D0,
198 };
199 enum port port = dig_port->port;
200 u32 aux_ctl;
201 int i;
202
203 BUILD_BUG_ON(sizeof(aux_msg) > 20);
204
205 aux_clock_divider = intel_dp->get_aux_clock_divider(intel_dp, 0);
206
207 /* Enable AUX frame sync at sink */
208 if (dev_priv->psr.aux_frame_sync)
209 drm_dp_dpcd_writeb(&intel_dp->aux,
210 DP_SINK_DEVICE_AUX_FRAME_SYNC_CONF,
211 DP_AUX_FRAME_SYNC_ENABLE);
212 /* Enable ALPM at sink for psr2 */
213 if (dev_priv->psr.psr2_support && dev_priv->psr.alpm)
214 drm_dp_dpcd_writeb(&intel_dp->aux,
215 DP_RECEIVER_ALPM_CONFIG,
216 DP_ALPM_ENABLE);
217 if (dev_priv->psr.link_standby)
218 drm_dp_dpcd_writeb(&intel_dp->aux, DP_PSR_EN_CFG,
219 DP_PSR_ENABLE | DP_PSR_MAIN_LINK_ACTIVE);
220 else
221 drm_dp_dpcd_writeb(&intel_dp->aux, DP_PSR_EN_CFG,
222 DP_PSR_ENABLE);
223
224 aux_ctl_reg = psr_aux_ctl_reg(dev_priv, port);
225
226 /* Setup AUX registers */
227 for (i = 0; i < sizeof(aux_msg); i += 4)
228 I915_WRITE(psr_aux_data_reg(dev_priv, port, i >> 2),
229 intel_dp_pack_aux(&aux_msg[i], sizeof(aux_msg) - i));
230
231 aux_ctl = intel_dp->get_aux_send_ctl(intel_dp, 0, sizeof(aux_msg),
232 aux_clock_divider);
233 I915_WRITE(aux_ctl_reg, aux_ctl);
234 }
235
vlv_psr_enable_source(struct intel_dp * intel_dp)236 static void vlv_psr_enable_source(struct intel_dp *intel_dp)
237 {
238 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
239 struct drm_device *dev = dig_port->base.base.dev;
240 struct drm_i915_private *dev_priv = to_i915(dev);
241 struct drm_crtc *crtc = dig_port->base.base.crtc;
242 enum pipe pipe = to_intel_crtc(crtc)->pipe;
243
244 /* Transition from PSR_state 0 to PSR_state 1, i.e. PSR Inactive */
245 I915_WRITE(VLV_PSRCTL(pipe),
246 VLV_EDP_PSR_MODE_SW_TIMER |
247 VLV_EDP_PSR_SRC_TRANSMITTER_STATE |
248 VLV_EDP_PSR_ENABLE);
249 }
250
vlv_psr_activate(struct intel_dp * intel_dp)251 static void vlv_psr_activate(struct intel_dp *intel_dp)
252 {
253 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
254 struct drm_device *dev = dig_port->base.base.dev;
255 struct drm_i915_private *dev_priv = to_i915(dev);
256 struct drm_crtc *crtc = dig_port->base.base.crtc;
257 enum pipe pipe = to_intel_crtc(crtc)->pipe;
258
259 /* Let's do the transition from PSR_state 1 to PSR_state 2
260 * that is PSR transition to active - static frame transmission.
261 * Then Hardware is responsible for the transition to PSR_state 3
262 * that is PSR active - no Remote Frame Buffer (RFB) update.
263 */
264 I915_WRITE(VLV_PSRCTL(pipe), I915_READ(VLV_PSRCTL(pipe)) |
265 VLV_EDP_PSR_ACTIVE_ENTRY);
266 }
267
intel_enable_source_psr1(struct intel_dp * intel_dp)268 static void intel_enable_source_psr1(struct intel_dp *intel_dp)
269 {
270 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
271 struct drm_device *dev = dig_port->base.base.dev;
272 struct drm_i915_private *dev_priv = to_i915(dev);
273
274 uint32_t max_sleep_time = 0x1f;
275 /*
276 * Let's respect VBT in case VBT asks a higher idle_frame value.
277 * Let's use 6 as the minimum to cover all known cases including
278 * the off-by-one issue that HW has in some cases. Also there are
279 * cases where sink should be able to train
280 * with the 5 or 6 idle patterns.
281 */
282 uint32_t idle_frames = max(6, dev_priv->vbt.psr.idle_frames);
283 uint32_t val = EDP_PSR_ENABLE;
284
285 val |= max_sleep_time << EDP_PSR_MAX_SLEEP_TIME_SHIFT;
286 val |= idle_frames << EDP_PSR_IDLE_FRAME_SHIFT;
287
288 if (IS_HASWELL(dev_priv))
289 val |= EDP_PSR_MIN_LINK_ENTRY_TIME_8_LINES;
290
291 if (dev_priv->psr.link_standby)
292 val |= EDP_PSR_LINK_STANDBY;
293
294 if (dev_priv->vbt.psr.tp1_wakeup_time > 5)
295 val |= EDP_PSR_TP1_TIME_2500us;
296 else if (dev_priv->vbt.psr.tp1_wakeup_time > 1)
297 val |= EDP_PSR_TP1_TIME_500us;
298 else if (dev_priv->vbt.psr.tp1_wakeup_time > 0)
299 val |= EDP_PSR_TP1_TIME_100us;
300 else
301 val |= EDP_PSR_TP1_TIME_0us;
302
303 if (dev_priv->vbt.psr.tp2_tp3_wakeup_time > 5)
304 val |= EDP_PSR_TP2_TP3_TIME_2500us;
305 else if (dev_priv->vbt.psr.tp2_tp3_wakeup_time > 1)
306 val |= EDP_PSR_TP2_TP3_TIME_500us;
307 else if (dev_priv->vbt.psr.tp2_tp3_wakeup_time > 0)
308 val |= EDP_PSR_TP2_TP3_TIME_100us;
309 else
310 val |= EDP_PSR_TP2_TP3_TIME_0us;
311
312 if (intel_dp_source_supports_hbr2(intel_dp) &&
313 drm_dp_tps3_supported(intel_dp->dpcd))
314 val |= EDP_PSR_TP1_TP3_SEL;
315 else
316 val |= EDP_PSR_TP1_TP2_SEL;
317
318 val |= I915_READ(EDP_PSR_CTL) & EDP_PSR_RESTORE_PSR_ACTIVE_CTX_MASK;
319 I915_WRITE(EDP_PSR_CTL, val);
320 }
321
intel_enable_source_psr2(struct intel_dp * intel_dp)322 static void intel_enable_source_psr2(struct intel_dp *intel_dp)
323 {
324 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
325 struct drm_device *dev = dig_port->base.base.dev;
326 struct drm_i915_private *dev_priv = to_i915(dev);
327 /*
328 * Let's respect VBT in case VBT asks a higher idle_frame value.
329 * Let's use 6 as the minimum to cover all known cases including
330 * the off-by-one issue that HW has in some cases. Also there are
331 * cases where sink should be able to train
332 * with the 5 or 6 idle patterns.
333 */
334 uint32_t idle_frames = max(6, dev_priv->vbt.psr.idle_frames);
335 uint32_t val;
336
337 val = idle_frames << EDP_PSR_IDLE_FRAME_SHIFT;
338
339 /* FIXME: selective update is probably totally broken because it doesn't
340 * mesh at all with our frontbuffer tracking. And the hw alone isn't
341 * good enough. */
342 val |= EDP_PSR2_ENABLE |
343 EDP_SU_TRACK_ENABLE |
344 EDP_FRAMES_BEFORE_SU_ENTRY;
345
346 if (dev_priv->vbt.psr.tp2_tp3_wakeup_time > 5)
347 val |= EDP_PSR2_TP2_TIME_2500;
348 else if (dev_priv->vbt.psr.tp2_tp3_wakeup_time > 1)
349 val |= EDP_PSR2_TP2_TIME_500;
350 else if (dev_priv->vbt.psr.tp2_tp3_wakeup_time > 0)
351 val |= EDP_PSR2_TP2_TIME_100;
352 else
353 val |= EDP_PSR2_TP2_TIME_50;
354
355 I915_WRITE(EDP_PSR2_CTL, val);
356 }
357
hsw_psr_enable_source(struct intel_dp * intel_dp)358 static void hsw_psr_enable_source(struct intel_dp *intel_dp)
359 {
360 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
361 struct drm_device *dev = dig_port->base.base.dev;
362 struct drm_i915_private *dev_priv = to_i915(dev);
363
364 /* psr1 and psr2 are mutually exclusive.*/
365 if (dev_priv->psr.psr2_support)
366 intel_enable_source_psr2(intel_dp);
367 else
368 intel_enable_source_psr1(intel_dp);
369 }
370
intel_psr_match_conditions(struct intel_dp * intel_dp)371 static bool intel_psr_match_conditions(struct intel_dp *intel_dp)
372 {
373 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
374 struct drm_device *dev = dig_port->base.base.dev;
375 struct drm_i915_private *dev_priv = to_i915(dev);
376 struct drm_crtc *crtc = dig_port->base.base.crtc;
377 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
378 const struct drm_display_mode *adjusted_mode =
379 &intel_crtc->config->base.adjusted_mode;
380 int psr_setup_time;
381
382 lockdep_assert_held(&dev_priv->psr.lock);
383 WARN_ON(!drm_modeset_is_locked(&dev->mode_config.connection_mutex));
384 WARN_ON(!drm_modeset_is_locked(&crtc->mutex));
385
386 dev_priv->psr.source_ok = false;
387
388 /*
389 * HSW spec explicitly says PSR is tied to port A.
390 * BDW+ platforms with DDI implementation of PSR have different
391 * PSR registers per transcoder and we only implement transcoder EDP
392 * ones. Since by Display design transcoder EDP is tied to port A
393 * we can safely escape based on the port A.
394 */
395 if (HAS_DDI(dev_priv) && dig_port->port != PORT_A) {
396 DRM_DEBUG_KMS("PSR condition failed: Port not supported\n");
397 return false;
398 }
399
400 if (!i915.enable_psr) {
401 DRM_DEBUG_KMS("PSR disable by flag\n");
402 return false;
403 }
404
405 if ((IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) &&
406 !dev_priv->psr.link_standby) {
407 DRM_ERROR("PSR condition failed: Link off requested but not supported on this platform\n");
408 return false;
409 }
410
411 if (IS_HASWELL(dev_priv) &&
412 I915_READ(HSW_STEREO_3D_CTL(intel_crtc->config->cpu_transcoder)) &
413 S3D_ENABLE) {
414 DRM_DEBUG_KMS("PSR condition failed: Stereo 3D is Enabled\n");
415 return false;
416 }
417
418 if (IS_HASWELL(dev_priv) &&
419 adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) {
420 DRM_DEBUG_KMS("PSR condition failed: Interlaced is Enabled\n");
421 return false;
422 }
423
424 psr_setup_time = drm_dp_psr_setup_time(intel_dp->psr_dpcd);
425 if (psr_setup_time < 0) {
426 DRM_DEBUG_KMS("PSR condition failed: Invalid PSR setup time (0x%02x)\n",
427 intel_dp->psr_dpcd[1]);
428 return false;
429 }
430
431 if (intel_usecs_to_scanlines(adjusted_mode, psr_setup_time) >
432 adjusted_mode->crtc_vtotal - adjusted_mode->crtc_vdisplay - 1) {
433 DRM_DEBUG_KMS("PSR condition failed: PSR setup time (%d us) too long\n",
434 psr_setup_time);
435 return false;
436 }
437
438 /* PSR2 is restricted to work with panel resolutions upto 3200x2000 */
439 if (dev_priv->psr.psr2_support &&
440 (intel_crtc->config->pipe_src_w > 3200 ||
441 intel_crtc->config->pipe_src_h > 2000)) {
442 dev_priv->psr.psr2_support = false;
443 return false;
444 }
445
446 /*
447 * FIXME:enable psr2 only for y-cordinate psr2 panels
448 * After gtc implementation , remove this restriction.
449 */
450 if (!dev_priv->psr.y_cord_support && dev_priv->psr.psr2_support) {
451 DRM_DEBUG_KMS("PSR2 disabled, panel does not support Y coordinate\n");
452 return false;
453 }
454
455 dev_priv->psr.source_ok = true;
456 return true;
457 }
458
intel_psr_activate(struct intel_dp * intel_dp)459 static void intel_psr_activate(struct intel_dp *intel_dp)
460 {
461 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
462 struct drm_device *dev = intel_dig_port->base.base.dev;
463 struct drm_i915_private *dev_priv = to_i915(dev);
464
465 if (dev_priv->psr.psr2_support)
466 WARN_ON(I915_READ(EDP_PSR2_CTL) & EDP_PSR2_ENABLE);
467 else
468 WARN_ON(I915_READ(EDP_PSR_CTL) & EDP_PSR_ENABLE);
469 WARN_ON(dev_priv->psr.active);
470 lockdep_assert_held(&dev_priv->psr.lock);
471
472 /* Enable/Re-enable PSR on the host */
473 if (HAS_DDI(dev_priv))
474 /* On HSW+ after we enable PSR on source it will activate it
475 * as soon as it match configure idle_frame count. So
476 * we just actually enable it here on activation time.
477 */
478 hsw_psr_enable_source(intel_dp);
479 else
480 vlv_psr_activate(intel_dp);
481
482 dev_priv->psr.active = true;
483 }
484
485 /**
486 * intel_psr_enable - Enable PSR
487 * @intel_dp: Intel DP
488 *
489 * This function can only be called after the pipe is fully trained and enabled.
490 */
intel_psr_enable(struct intel_dp * intel_dp)491 void intel_psr_enable(struct intel_dp *intel_dp)
492 {
493 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
494 struct drm_device *dev = intel_dig_port->base.base.dev;
495 struct drm_i915_private *dev_priv = to_i915(dev);
496 struct intel_crtc *crtc = to_intel_crtc(intel_dig_port->base.base.crtc);
497 enum transcoder cpu_transcoder = crtc->config->cpu_transcoder;
498 u32 chicken;
499
500 if (!HAS_PSR(dev_priv)) {
501 DRM_DEBUG_KMS("PSR not supported on this platform\n");
502 return;
503 }
504
505 if (!is_edp_psr(intel_dp)) {
506 DRM_DEBUG_KMS("PSR not supported by this panel\n");
507 return;
508 }
509
510 mutex_lock(&dev_priv->psr.lock);
511 if (dev_priv->psr.enabled) {
512 DRM_DEBUG_KMS("PSR already in use\n");
513 goto unlock;
514 }
515
516 if (!intel_psr_match_conditions(intel_dp))
517 goto unlock;
518
519 dev_priv->psr.busy_frontbuffer_bits = 0;
520
521 if (HAS_DDI(dev_priv)) {
522 if (dev_priv->psr.psr2_support) {
523 skl_psr_setup_su_vsc(intel_dp);
524 chicken = PSR2_VSC_ENABLE_PROG_HEADER;
525 if (dev_priv->psr.y_cord_support)
526 chicken |= PSR2_ADD_VERTICAL_LINE_COUNT;
527 I915_WRITE(CHICKEN_TRANS(cpu_transcoder), chicken);
528 I915_WRITE(EDP_PSR_DEBUG_CTL,
529 EDP_PSR_DEBUG_MASK_MEMUP |
530 EDP_PSR_DEBUG_MASK_HPD |
531 EDP_PSR_DEBUG_MASK_LPSP |
532 EDP_PSR_DEBUG_MASK_MAX_SLEEP |
533 EDP_PSR_DEBUG_MASK_DISP_REG_WRITE);
534 } else {
535 /* set up vsc header for psr1 */
536 hsw_psr_setup_vsc(intel_dp);
537 /*
538 * Per Spec: Avoid continuous PSR exit by masking MEMUP
539 * and HPD. also mask LPSP to avoid dependency on other
540 * drivers that might block runtime_pm besides
541 * preventing other hw tracking issues now we can rely
542 * on frontbuffer tracking.
543 */
544 I915_WRITE(EDP_PSR_DEBUG_CTL,
545 EDP_PSR_DEBUG_MASK_MEMUP |
546 EDP_PSR_DEBUG_MASK_HPD |
547 EDP_PSR_DEBUG_MASK_LPSP);
548 }
549
550 /* Enable PSR on the panel */
551 hsw_psr_enable_sink(intel_dp);
552
553 if (INTEL_GEN(dev_priv) >= 9)
554 intel_psr_activate(intel_dp);
555 } else {
556 vlv_psr_setup_vsc(intel_dp);
557
558 /* Enable PSR on the panel */
559 vlv_psr_enable_sink(intel_dp);
560
561 /* On HSW+ enable_source also means go to PSR entry/active
562 * state as soon as idle_frame achieved and here would be
563 * to soon. However on VLV enable_source just enable PSR
564 * but let it on inactive state. So we might do this prior
565 * to active transition, i.e. here.
566 */
567 vlv_psr_enable_source(intel_dp);
568 }
569
570 /*
571 * FIXME: Activation should happen immediately since this function
572 * is just called after pipe is fully trained and enabled.
573 * However on every platform we face issues when first activation
574 * follows a modeset so quickly.
575 * - On VLV/CHV we get bank screen on first activation
576 * - On HSW/BDW we get a recoverable frozen screen until next
577 * exit-activate sequence.
578 */
579 if (INTEL_GEN(dev_priv) < 9)
580 schedule_delayed_work(&dev_priv->psr.work,
581 msecs_to_jiffies(intel_dp->panel_power_cycle_delay * 5));
582
583 dev_priv->psr.enabled = intel_dp;
584 unlock:
585 mutex_unlock(&dev_priv->psr.lock);
586 }
587
vlv_psr_disable(struct intel_dp * intel_dp)588 static void vlv_psr_disable(struct intel_dp *intel_dp)
589 {
590 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
591 struct drm_device *dev = intel_dig_port->base.base.dev;
592 struct drm_i915_private *dev_priv = to_i915(dev);
593 struct intel_crtc *intel_crtc =
594 to_intel_crtc(intel_dig_port->base.base.crtc);
595 uint32_t val;
596
597 if (dev_priv->psr.active) {
598 /* Put VLV PSR back to PSR_state 0 that is PSR Disabled. */
599 if (intel_wait_for_register(dev_priv,
600 VLV_PSRSTAT(intel_crtc->pipe),
601 VLV_EDP_PSR_IN_TRANS,
602 0,
603 1))
604 WARN(1, "PSR transition took longer than expected\n");
605
606 val = I915_READ(VLV_PSRCTL(intel_crtc->pipe));
607 val &= ~VLV_EDP_PSR_ACTIVE_ENTRY;
608 val &= ~VLV_EDP_PSR_ENABLE;
609 val &= ~VLV_EDP_PSR_MODE_MASK;
610 I915_WRITE(VLV_PSRCTL(intel_crtc->pipe), val);
611
612 dev_priv->psr.active = false;
613 } else {
614 WARN_ON(vlv_is_psr_active_on_pipe(dev, intel_crtc->pipe));
615 }
616 }
617
hsw_psr_disable(struct intel_dp * intel_dp)618 static void hsw_psr_disable(struct intel_dp *intel_dp)
619 {
620 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
621 struct drm_device *dev = intel_dig_port->base.base.dev;
622 struct drm_i915_private *dev_priv = to_i915(dev);
623
624 if (dev_priv->psr.active) {
625 i915_reg_t psr_ctl;
626 u32 psr_status_mask;
627
628 if (dev_priv->psr.aux_frame_sync)
629 drm_dp_dpcd_writeb(&intel_dp->aux,
630 DP_SINK_DEVICE_AUX_FRAME_SYNC_CONF,
631 0);
632
633 if (dev_priv->psr.psr2_support) {
634 psr_ctl = EDP_PSR2_CTL;
635 psr_status_mask = EDP_PSR2_STATUS_STATE_MASK;
636
637 I915_WRITE(psr_ctl,
638 I915_READ(psr_ctl) &
639 ~(EDP_PSR2_ENABLE | EDP_SU_TRACK_ENABLE));
640
641 } else {
642 psr_ctl = EDP_PSR_STATUS_CTL;
643 psr_status_mask = EDP_PSR_STATUS_STATE_MASK;
644
645 I915_WRITE(psr_ctl,
646 I915_READ(psr_ctl) & ~EDP_PSR_ENABLE);
647 }
648
649 /* Wait till PSR is idle */
650 if (intel_wait_for_register(dev_priv,
651 psr_ctl, psr_status_mask, 0,
652 2000))
653 DRM_ERROR("Timed out waiting for PSR Idle State\n");
654
655 dev_priv->psr.active = false;
656 } else {
657 if (dev_priv->psr.psr2_support)
658 WARN_ON(I915_READ(EDP_PSR2_CTL) & EDP_PSR2_ENABLE);
659 else
660 WARN_ON(I915_READ(EDP_PSR_CTL) & EDP_PSR_ENABLE);
661 }
662 }
663
664 /**
665 * intel_psr_disable - Disable PSR
666 * @intel_dp: Intel DP
667 *
668 * This function needs to be called before disabling pipe.
669 */
intel_psr_disable(struct intel_dp * intel_dp)670 void intel_psr_disable(struct intel_dp *intel_dp)
671 {
672 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
673 struct drm_device *dev = intel_dig_port->base.base.dev;
674 struct drm_i915_private *dev_priv = to_i915(dev);
675
676 mutex_lock(&dev_priv->psr.lock);
677 if (!dev_priv->psr.enabled) {
678 mutex_unlock(&dev_priv->psr.lock);
679 return;
680 }
681
682 /* Disable PSR on Source */
683 if (HAS_DDI(dev_priv))
684 hsw_psr_disable(intel_dp);
685 else
686 vlv_psr_disable(intel_dp);
687
688 /* Disable PSR on Sink */
689 drm_dp_dpcd_writeb(&intel_dp->aux, DP_PSR_EN_CFG, 0);
690
691 dev_priv->psr.enabled = NULL;
692 mutex_unlock(&dev_priv->psr.lock);
693
694 cancel_delayed_work_sync(&dev_priv->psr.work);
695 }
696
intel_psr_work(struct work_struct * work)697 static void intel_psr_work(struct work_struct *work)
698 {
699 struct drm_i915_private *dev_priv =
700 container_of(work, typeof(*dev_priv), psr.work.work);
701 struct intel_dp *intel_dp = dev_priv->psr.enabled;
702 struct drm_crtc *crtc = dp_to_dig_port(intel_dp)->base.base.crtc;
703 enum pipe pipe = to_intel_crtc(crtc)->pipe;
704
705 /* We have to make sure PSR is ready for re-enable
706 * otherwise it keeps disabled until next full enable/disable cycle.
707 * PSR might take some time to get fully disabled
708 * and be ready for re-enable.
709 */
710 if (HAS_DDI(dev_priv)) {
711 if (dev_priv->psr.psr2_support) {
712 if (intel_wait_for_register(dev_priv,
713 EDP_PSR2_STATUS_CTL,
714 EDP_PSR2_STATUS_STATE_MASK,
715 0,
716 50)) {
717 DRM_ERROR("Timed out waiting for PSR2 Idle for re-enable\n");
718 return;
719 }
720 } else {
721 if (intel_wait_for_register(dev_priv,
722 EDP_PSR_STATUS_CTL,
723 EDP_PSR_STATUS_STATE_MASK,
724 0,
725 50)) {
726 DRM_ERROR("Timed out waiting for PSR Idle for re-enable\n");
727 return;
728 }
729 }
730 } else {
731 if (intel_wait_for_register(dev_priv,
732 VLV_PSRSTAT(pipe),
733 VLV_EDP_PSR_IN_TRANS,
734 0,
735 1)) {
736 DRM_ERROR("Timed out waiting for PSR Idle for re-enable\n");
737 return;
738 }
739 }
740 mutex_lock(&dev_priv->psr.lock);
741 intel_dp = dev_priv->psr.enabled;
742
743 if (!intel_dp)
744 goto unlock;
745
746 /*
747 * The delayed work can race with an invalidate hence we need to
748 * recheck. Since psr_flush first clears this and then reschedules we
749 * won't ever miss a flush when bailing out here.
750 */
751 if (dev_priv->psr.busy_frontbuffer_bits)
752 goto unlock;
753
754 intel_psr_activate(intel_dp);
755 unlock:
756 mutex_unlock(&dev_priv->psr.lock);
757 }
758
intel_psr_exit(struct drm_i915_private * dev_priv)759 static void intel_psr_exit(struct drm_i915_private *dev_priv)
760 {
761 struct intel_dp *intel_dp = dev_priv->psr.enabled;
762 struct drm_crtc *crtc = dp_to_dig_port(intel_dp)->base.base.crtc;
763 enum pipe pipe = to_intel_crtc(crtc)->pipe;
764 u32 val;
765
766 if (!dev_priv->psr.active)
767 return;
768
769 if (HAS_DDI(dev_priv)) {
770 if (dev_priv->psr.aux_frame_sync)
771 drm_dp_dpcd_writeb(&intel_dp->aux,
772 DP_SINK_DEVICE_AUX_FRAME_SYNC_CONF,
773 0);
774 if (dev_priv->psr.psr2_support) {
775 val = I915_READ(EDP_PSR2_CTL);
776 WARN_ON(!(val & EDP_PSR2_ENABLE));
777 I915_WRITE(EDP_PSR2_CTL, val & ~EDP_PSR2_ENABLE);
778 } else {
779 val = I915_READ(EDP_PSR_CTL);
780 WARN_ON(!(val & EDP_PSR_ENABLE));
781 I915_WRITE(EDP_PSR_CTL, val & ~EDP_PSR_ENABLE);
782 }
783 } else {
784 val = I915_READ(VLV_PSRCTL(pipe));
785
786 /* Here we do the transition from PSR_state 3 to PSR_state 5
787 * directly once PSR State 4 that is active with single frame
788 * update can be skipped. PSR_state 5 that is PSR exit then
789 * Hardware is responsible to transition back to PSR_state 1
790 * that is PSR inactive. Same state after
791 * vlv_edp_psr_enable_source.
792 */
793 val &= ~VLV_EDP_PSR_ACTIVE_ENTRY;
794 I915_WRITE(VLV_PSRCTL(pipe), val);
795
796 /* Send AUX wake up - Spec says after transitioning to PSR
797 * active we have to send AUX wake up by writing 01h in DPCD
798 * 600h of sink device.
799 * XXX: This might slow down the transition, but without this
800 * HW doesn't complete the transition to PSR_state 1 and we
801 * never get the screen updated.
802 */
803 drm_dp_dpcd_writeb(&intel_dp->aux, DP_SET_POWER,
804 DP_SET_POWER_D0);
805 }
806
807 dev_priv->psr.active = false;
808 }
809
810 /**
811 * intel_psr_single_frame_update - Single Frame Update
812 * @dev_priv: i915 device
813 * @frontbuffer_bits: frontbuffer plane tracking bits
814 *
815 * Some platforms support a single frame update feature that is used to
816 * send and update only one frame on Remote Frame Buffer.
817 * So far it is only implemented for Valleyview and Cherryview because
818 * hardware requires this to be done before a page flip.
819 */
intel_psr_single_frame_update(struct drm_i915_private * dev_priv,unsigned frontbuffer_bits)820 void intel_psr_single_frame_update(struct drm_i915_private *dev_priv,
821 unsigned frontbuffer_bits)
822 {
823 struct drm_crtc *crtc;
824 enum pipe pipe;
825 u32 val;
826
827 /*
828 * Single frame update is already supported on BDW+ but it requires
829 * many W/A and it isn't really needed.
830 */
831 if (!IS_VALLEYVIEW(dev_priv) && !IS_CHERRYVIEW(dev_priv))
832 return;
833
834 mutex_lock(&dev_priv->psr.lock);
835 if (!dev_priv->psr.enabled) {
836 mutex_unlock(&dev_priv->psr.lock);
837 return;
838 }
839
840 crtc = dp_to_dig_port(dev_priv->psr.enabled)->base.base.crtc;
841 pipe = to_intel_crtc(crtc)->pipe;
842
843 if (frontbuffer_bits & INTEL_FRONTBUFFER_ALL_MASK(pipe)) {
844 val = I915_READ(VLV_PSRCTL(pipe));
845
846 /*
847 * We need to set this bit before writing registers for a flip.
848 * This bit will be self-clear when it gets to the PSR active state.
849 */
850 I915_WRITE(VLV_PSRCTL(pipe), val | VLV_EDP_PSR_SINGLE_FRAME_UPDATE);
851 }
852 mutex_unlock(&dev_priv->psr.lock);
853 }
854
855 /**
856 * intel_psr_invalidate - Invalidade PSR
857 * @dev_priv: i915 device
858 * @frontbuffer_bits: frontbuffer plane tracking bits
859 *
860 * Since the hardware frontbuffer tracking has gaps we need to integrate
861 * with the software frontbuffer tracking. This function gets called every
862 * time frontbuffer rendering starts and a buffer gets dirtied. PSR must be
863 * disabled if the frontbuffer mask contains a buffer relevant to PSR.
864 *
865 * Dirty frontbuffers relevant to PSR are tracked in busy_frontbuffer_bits."
866 */
intel_psr_invalidate(struct drm_i915_private * dev_priv,unsigned frontbuffer_bits)867 void intel_psr_invalidate(struct drm_i915_private *dev_priv,
868 unsigned frontbuffer_bits)
869 {
870 struct drm_crtc *crtc;
871 enum pipe pipe;
872
873 mutex_lock(&dev_priv->psr.lock);
874 if (!dev_priv->psr.enabled) {
875 mutex_unlock(&dev_priv->psr.lock);
876 return;
877 }
878
879 crtc = dp_to_dig_port(dev_priv->psr.enabled)->base.base.crtc;
880 pipe = to_intel_crtc(crtc)->pipe;
881
882 frontbuffer_bits &= INTEL_FRONTBUFFER_ALL_MASK(pipe);
883 dev_priv->psr.busy_frontbuffer_bits |= frontbuffer_bits;
884
885 if (frontbuffer_bits)
886 intel_psr_exit(dev_priv);
887
888 mutex_unlock(&dev_priv->psr.lock);
889 }
890
891 /**
892 * intel_psr_flush - Flush PSR
893 * @dev_priv: i915 device
894 * @frontbuffer_bits: frontbuffer plane tracking bits
895 * @origin: which operation caused the flush
896 *
897 * Since the hardware frontbuffer tracking has gaps we need to integrate
898 * with the software frontbuffer tracking. This function gets called every
899 * time frontbuffer rendering has completed and flushed out to memory. PSR
900 * can be enabled again if no other frontbuffer relevant to PSR is dirty.
901 *
902 * Dirty frontbuffers relevant to PSR are tracked in busy_frontbuffer_bits.
903 */
intel_psr_flush(struct drm_i915_private * dev_priv,unsigned frontbuffer_bits,enum fb_op_origin origin)904 void intel_psr_flush(struct drm_i915_private *dev_priv,
905 unsigned frontbuffer_bits, enum fb_op_origin origin)
906 {
907 struct drm_crtc *crtc;
908 enum pipe pipe;
909
910 mutex_lock(&dev_priv->psr.lock);
911 if (!dev_priv->psr.enabled) {
912 mutex_unlock(&dev_priv->psr.lock);
913 return;
914 }
915
916 crtc = dp_to_dig_port(dev_priv->psr.enabled)->base.base.crtc;
917 pipe = to_intel_crtc(crtc)->pipe;
918
919 frontbuffer_bits &= INTEL_FRONTBUFFER_ALL_MASK(pipe);
920 dev_priv->psr.busy_frontbuffer_bits &= ~frontbuffer_bits;
921
922 /* By definition flush = invalidate + flush */
923 if (frontbuffer_bits)
924 intel_psr_exit(dev_priv);
925
926 if (!dev_priv->psr.active && !dev_priv->psr.busy_frontbuffer_bits)
927 if (!work_busy(&dev_priv->psr.work.work))
928 schedule_delayed_work(&dev_priv->psr.work,
929 msecs_to_jiffies(100));
930 mutex_unlock(&dev_priv->psr.lock);
931 }
932
933 /**
934 * intel_psr_init - Init basic PSR work and mutex.
935 * @dev_priv: i915 device private
936 *
937 * This function is called only once at driver load to initialize basic
938 * PSR stuff.
939 */
intel_psr_init(struct drm_i915_private * dev_priv)940 void intel_psr_init(struct drm_i915_private *dev_priv)
941 {
942 dev_priv->psr_mmio_base = IS_HASWELL(dev_priv) ?
943 HSW_EDP_PSR_BASE : BDW_EDP_PSR_BASE;
944
945 /* Per platform default: all disabled. */
946 if (i915.enable_psr == -1)
947 i915.enable_psr = 0;
948
949 /* Set link_standby x link_off defaults */
950 if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv))
951 /* HSW and BDW require workarounds that we don't implement. */
952 dev_priv->psr.link_standby = false;
953 else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
954 /* On VLV and CHV only standby mode is supported. */
955 dev_priv->psr.link_standby = true;
956 else
957 /* For new platforms let's respect VBT back again */
958 dev_priv->psr.link_standby = dev_priv->vbt.psr.full_link;
959
960 /* Override link_standby x link_off defaults */
961 if (i915.enable_psr == 2 && !dev_priv->psr.link_standby) {
962 DRM_DEBUG_KMS("PSR: Forcing link standby\n");
963 dev_priv->psr.link_standby = true;
964 }
965 if (i915.enable_psr == 3 && dev_priv->psr.link_standby) {
966 DRM_DEBUG_KMS("PSR: Forcing main link off\n");
967 dev_priv->psr.link_standby = false;
968 }
969
970 INIT_DELAYED_WORK(&dev_priv->psr.work, intel_psr_work);
971 mutex_init(&dev_priv->psr.lock);
972 }
973