1 /*
2 * Copyright (c) 2012-2015, The Linux Foundation. All rights reserved.
3 *
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License version 2 and
6 * only version 2 as published by the Free Software Foundation.
7 *
8 * This program is distributed in the hope that it will be useful,
9 * but WITHOUT ANY WARRANTY; without even the implied warranty of
10 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
11 * GNU General Public License for more details.
12 */
13
14 #ifndef __DSI_PLL_H__
15 #define __DSI_PLL_H__
16
17 #include <linux/clk.h>
18 #include <linux/clk-provider.h>
19
20 #include "dsi.h"
21
22 #define NUM_DSI_CLOCKS_MAX 6
23 #define MAX_DSI_PLL_EN_SEQS 10
24
25 struct msm_dsi_pll {
26 enum msm_dsi_phy_type type;
27
28 struct clk_hw clk_hw;
29 bool pll_on;
30 bool state_saved;
31
32 unsigned long min_rate;
33 unsigned long max_rate;
34 u32 en_seq_cnt;
35
36 int (*enable_seqs[MAX_DSI_PLL_EN_SEQS])(struct msm_dsi_pll *pll);
37 void (*disable_seq)(struct msm_dsi_pll *pll);
38 int (*get_provider)(struct msm_dsi_pll *pll,
39 struct clk **byte_clk_provider,
40 struct clk **pixel_clk_provider);
41 void (*destroy)(struct msm_dsi_pll *pll);
42 void (*save_state)(struct msm_dsi_pll *pll);
43 int (*restore_state)(struct msm_dsi_pll *pll);
44 int (*set_usecase)(struct msm_dsi_pll *pll,
45 enum msm_dsi_phy_usecase uc);
46 };
47
48 #define hw_clk_to_pll(x) container_of(x, struct msm_dsi_pll, clk_hw)
49
pll_write(void __iomem * reg,u32 data)50 static inline void pll_write(void __iomem *reg, u32 data)
51 {
52 msm_writel(data, reg);
53 }
54
pll_read(const void __iomem * reg)55 static inline u32 pll_read(const void __iomem *reg)
56 {
57 return msm_readl(reg);
58 }
59
pll_write_udelay(void __iomem * reg,u32 data,u32 delay_us)60 static inline void pll_write_udelay(void __iomem *reg, u32 data, u32 delay_us)
61 {
62 pll_write(reg, data);
63 udelay(delay_us);
64 }
65
pll_write_ndelay(void __iomem * reg,u32 data,u32 delay_ns)66 static inline void pll_write_ndelay(void __iomem *reg, u32 data, u32 delay_ns)
67 {
68 pll_write((reg), data);
69 ndelay(delay_ns);
70 }
71
72 /*
73 * DSI PLL Helper functions
74 */
75
76 /* clock callbacks */
77 long msm_dsi_pll_helper_clk_round_rate(struct clk_hw *hw,
78 unsigned long rate, unsigned long *parent_rate);
79 int msm_dsi_pll_helper_clk_prepare(struct clk_hw *hw);
80 void msm_dsi_pll_helper_clk_unprepare(struct clk_hw *hw);
81 /* misc */
82 void msm_dsi_pll_helper_unregister_clks(struct platform_device *pdev,
83 struct clk **clks, u32 num_clks);
84
85 /*
86 * Initialization for Each PLL Type
87 */
88 #ifdef CONFIG_DRM_MSM_DSI_28NM_PHY
89 struct msm_dsi_pll *msm_dsi_pll_28nm_init(struct platform_device *pdev,
90 enum msm_dsi_phy_type type, int id);
91 #else
msm_dsi_pll_28nm_init(struct platform_device * pdev,enum msm_dsi_phy_type type,int id)92 static inline struct msm_dsi_pll *msm_dsi_pll_28nm_init(
93 struct platform_device *pdev, enum msm_dsi_phy_type type, int id)
94 {
95 return ERR_PTR(-ENODEV);
96 }
97 #endif
98 #ifdef CONFIG_DRM_MSM_DSI_28NM_8960_PHY
99 struct msm_dsi_pll *msm_dsi_pll_28nm_8960_init(struct platform_device *pdev,
100 int id);
101 #else
msm_dsi_pll_28nm_8960_init(struct platform_device * pdev,int id)102 static inline struct msm_dsi_pll *msm_dsi_pll_28nm_8960_init(
103 struct platform_device *pdev, int id)
104 {
105 return ERR_PTR(-ENODEV);
106 }
107 #endif
108
109 #ifdef CONFIG_DRM_MSM_DSI_14NM_PHY
110 struct msm_dsi_pll *msm_dsi_pll_14nm_init(struct platform_device *pdev, int id);
111 #else
112 static inline struct msm_dsi_pll *
msm_dsi_pll_14nm_init(struct platform_device * pdev,int id)113 msm_dsi_pll_14nm_init(struct platform_device *pdev, int id)
114 {
115 return ERR_PTR(-ENODEV);
116 }
117 #endif
118 #endif /* __DSI_PLL_H__ */
119
120