1 /*
2 * Copyright (C) 2013 Red Hat
3 * Author: Rob Clark <robdclark@gmail.com>
4 *
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms of the GNU General Public License version 2 as published by
7 * the Free Software Foundation.
8 *
9 * This program is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
12 * more details.
13 *
14 * You should have received a copy of the GNU General Public License along with
15 * this program. If not, see <http://www.gnu.org/licenses/>.
16 */
17
18 #include <drm/drm_crtc.h>
19 #include <drm/drm_crtc_helper.h>
20 #include <drm/drm_flip_work.h>
21 #include <drm/drm_mode.h>
22
23 #include "mdp4_kms.h"
24
25 struct mdp4_crtc {
26 struct drm_crtc base;
27 char name[8];
28 int id;
29 int ovlp;
30 enum mdp4_dma dma;
31 bool enabled;
32
33 /* which mixer/encoder we route output to: */
34 int mixer;
35
36 struct {
37 spinlock_t lock;
38 bool stale;
39 uint32_t width, height;
40 uint32_t x, y;
41
42 /* next cursor to scan-out: */
43 uint32_t next_iova;
44 struct drm_gem_object *next_bo;
45
46 /* current cursor being scanned out: */
47 struct drm_gem_object *scanout_bo;
48 } cursor;
49
50
51 /* if there is a pending flip, these will be non-null: */
52 struct drm_pending_vblank_event *event;
53
54 /* Bits have been flushed at the last commit,
55 * used to decide if a vsync has happened since last commit.
56 */
57 u32 flushed_mask;
58
59 #define PENDING_CURSOR 0x1
60 #define PENDING_FLIP 0x2
61 atomic_t pending;
62
63 /* for unref'ing cursor bo's after scanout completes: */
64 struct drm_flip_work unref_cursor_work;
65
66 struct mdp_irq vblank;
67 struct mdp_irq err;
68 };
69 #define to_mdp4_crtc(x) container_of(x, struct mdp4_crtc, base)
70
get_kms(struct drm_crtc * crtc)71 static struct mdp4_kms *get_kms(struct drm_crtc *crtc)
72 {
73 struct msm_drm_private *priv = crtc->dev->dev_private;
74 return to_mdp4_kms(to_mdp_kms(priv->kms));
75 }
76
request_pending(struct drm_crtc * crtc,uint32_t pending)77 static void request_pending(struct drm_crtc *crtc, uint32_t pending)
78 {
79 struct mdp4_crtc *mdp4_crtc = to_mdp4_crtc(crtc);
80
81 atomic_or(pending, &mdp4_crtc->pending);
82 mdp_irq_register(&get_kms(crtc)->base, &mdp4_crtc->vblank);
83 }
84
crtc_flush(struct drm_crtc * crtc)85 static void crtc_flush(struct drm_crtc *crtc)
86 {
87 struct mdp4_crtc *mdp4_crtc = to_mdp4_crtc(crtc);
88 struct mdp4_kms *mdp4_kms = get_kms(crtc);
89 struct drm_plane *plane;
90 uint32_t flush = 0;
91
92 drm_atomic_crtc_for_each_plane(plane, crtc) {
93 enum mdp4_pipe pipe_id = mdp4_plane_pipe(plane);
94 flush |= pipe2flush(pipe_id);
95 }
96
97 flush |= ovlp2flush(mdp4_crtc->ovlp);
98
99 DBG("%s: flush=%08x", mdp4_crtc->name, flush);
100
101 mdp4_crtc->flushed_mask = flush;
102
103 mdp4_write(mdp4_kms, REG_MDP4_OVERLAY_FLUSH, flush);
104 }
105
106 /* if file!=NULL, this is preclose potential cancel-flip path */
complete_flip(struct drm_crtc * crtc,struct drm_file * file)107 static void complete_flip(struct drm_crtc *crtc, struct drm_file *file)
108 {
109 struct mdp4_crtc *mdp4_crtc = to_mdp4_crtc(crtc);
110 struct drm_device *dev = crtc->dev;
111 struct drm_pending_vblank_event *event;
112 unsigned long flags;
113
114 spin_lock_irqsave(&dev->event_lock, flags);
115 event = mdp4_crtc->event;
116 if (event) {
117 mdp4_crtc->event = NULL;
118 DBG("%s: send event: %p", mdp4_crtc->name, event);
119 drm_crtc_send_vblank_event(crtc, event);
120 }
121 spin_unlock_irqrestore(&dev->event_lock, flags);
122 }
123
unref_cursor_worker(struct drm_flip_work * work,void * val)124 static void unref_cursor_worker(struct drm_flip_work *work, void *val)
125 {
126 struct mdp4_crtc *mdp4_crtc =
127 container_of(work, struct mdp4_crtc, unref_cursor_work);
128 struct mdp4_kms *mdp4_kms = get_kms(&mdp4_crtc->base);
129 struct msm_kms *kms = &mdp4_kms->base.base;
130
131 msm_gem_put_iova(val, kms->aspace);
132 drm_gem_object_unreference_unlocked(val);
133 }
134
mdp4_crtc_destroy(struct drm_crtc * crtc)135 static void mdp4_crtc_destroy(struct drm_crtc *crtc)
136 {
137 struct mdp4_crtc *mdp4_crtc = to_mdp4_crtc(crtc);
138
139 drm_crtc_cleanup(crtc);
140 drm_flip_work_cleanup(&mdp4_crtc->unref_cursor_work);
141
142 kfree(mdp4_crtc);
143 }
144
145 /* statically (for now) map planes to mixer stage (z-order): */
146 static const int idxs[] = {
147 [VG1] = 1,
148 [VG2] = 2,
149 [RGB1] = 0,
150 [RGB2] = 0,
151 [RGB3] = 0,
152 [VG3] = 3,
153 [VG4] = 4,
154
155 };
156
157 /* setup mixer config, for which we need to consider all crtc's and
158 * the planes attached to them
159 *
160 * TODO may possibly need some extra locking here
161 */
setup_mixer(struct mdp4_kms * mdp4_kms)162 static void setup_mixer(struct mdp4_kms *mdp4_kms)
163 {
164 struct drm_mode_config *config = &mdp4_kms->dev->mode_config;
165 struct drm_crtc *crtc;
166 uint32_t mixer_cfg = 0;
167 static const enum mdp_mixer_stage_id stages[] = {
168 STAGE_BASE, STAGE0, STAGE1, STAGE2, STAGE3,
169 };
170
171 list_for_each_entry(crtc, &config->crtc_list, head) {
172 struct mdp4_crtc *mdp4_crtc = to_mdp4_crtc(crtc);
173 struct drm_plane *plane;
174
175 drm_atomic_crtc_for_each_plane(plane, crtc) {
176 enum mdp4_pipe pipe_id = mdp4_plane_pipe(plane);
177 int idx = idxs[pipe_id];
178 mixer_cfg = mixercfg(mixer_cfg, mdp4_crtc->mixer,
179 pipe_id, stages[idx]);
180 }
181 }
182
183 mdp4_write(mdp4_kms, REG_MDP4_LAYERMIXER_IN_CFG, mixer_cfg);
184 }
185
blend_setup(struct drm_crtc * crtc)186 static void blend_setup(struct drm_crtc *crtc)
187 {
188 struct mdp4_crtc *mdp4_crtc = to_mdp4_crtc(crtc);
189 struct mdp4_kms *mdp4_kms = get_kms(crtc);
190 struct drm_plane *plane;
191 int i, ovlp = mdp4_crtc->ovlp;
192 bool alpha[4]= { false, false, false, false };
193
194 mdp4_write(mdp4_kms, REG_MDP4_OVLP_TRANSP_LOW0(ovlp), 0);
195 mdp4_write(mdp4_kms, REG_MDP4_OVLP_TRANSP_LOW1(ovlp), 0);
196 mdp4_write(mdp4_kms, REG_MDP4_OVLP_TRANSP_HIGH0(ovlp), 0);
197 mdp4_write(mdp4_kms, REG_MDP4_OVLP_TRANSP_HIGH1(ovlp), 0);
198
199 drm_atomic_crtc_for_each_plane(plane, crtc) {
200 enum mdp4_pipe pipe_id = mdp4_plane_pipe(plane);
201 int idx = idxs[pipe_id];
202 if (idx > 0) {
203 const struct mdp_format *format =
204 to_mdp_format(msm_framebuffer_format(plane->fb));
205 alpha[idx-1] = format->alpha_enable;
206 }
207 }
208
209 for (i = 0; i < 4; i++) {
210 uint32_t op;
211
212 if (alpha[i]) {
213 op = MDP4_OVLP_STAGE_OP_FG_ALPHA(FG_PIXEL) |
214 MDP4_OVLP_STAGE_OP_BG_ALPHA(FG_PIXEL) |
215 MDP4_OVLP_STAGE_OP_BG_INV_ALPHA;
216 } else {
217 op = MDP4_OVLP_STAGE_OP_FG_ALPHA(FG_CONST) |
218 MDP4_OVLP_STAGE_OP_BG_ALPHA(BG_CONST);
219 }
220
221 mdp4_write(mdp4_kms, REG_MDP4_OVLP_STAGE_FG_ALPHA(ovlp, i), 0xff);
222 mdp4_write(mdp4_kms, REG_MDP4_OVLP_STAGE_BG_ALPHA(ovlp, i), 0x00);
223 mdp4_write(mdp4_kms, REG_MDP4_OVLP_STAGE_OP(ovlp, i), op);
224 mdp4_write(mdp4_kms, REG_MDP4_OVLP_STAGE_CO3(ovlp, i), 1);
225 mdp4_write(mdp4_kms, REG_MDP4_OVLP_STAGE_TRANSP_LOW0(ovlp, i), 0);
226 mdp4_write(mdp4_kms, REG_MDP4_OVLP_STAGE_TRANSP_LOW1(ovlp, i), 0);
227 mdp4_write(mdp4_kms, REG_MDP4_OVLP_STAGE_TRANSP_HIGH0(ovlp, i), 0);
228 mdp4_write(mdp4_kms, REG_MDP4_OVLP_STAGE_TRANSP_HIGH1(ovlp, i), 0);
229 }
230
231 setup_mixer(mdp4_kms);
232 }
233
mdp4_crtc_mode_set_nofb(struct drm_crtc * crtc)234 static void mdp4_crtc_mode_set_nofb(struct drm_crtc *crtc)
235 {
236 struct mdp4_crtc *mdp4_crtc = to_mdp4_crtc(crtc);
237 struct mdp4_kms *mdp4_kms = get_kms(crtc);
238 enum mdp4_dma dma = mdp4_crtc->dma;
239 int ovlp = mdp4_crtc->ovlp;
240 struct drm_display_mode *mode;
241
242 if (WARN_ON(!crtc->state))
243 return;
244
245 mode = &crtc->state->adjusted_mode;
246
247 DBG("%s: set mode: %d:\"%s\" %d %d %d %d %d %d %d %d %d %d 0x%x 0x%x",
248 mdp4_crtc->name, mode->base.id, mode->name,
249 mode->vrefresh, mode->clock,
250 mode->hdisplay, mode->hsync_start,
251 mode->hsync_end, mode->htotal,
252 mode->vdisplay, mode->vsync_start,
253 mode->vsync_end, mode->vtotal,
254 mode->type, mode->flags);
255
256 mdp4_write(mdp4_kms, REG_MDP4_DMA_SRC_SIZE(dma),
257 MDP4_DMA_SRC_SIZE_WIDTH(mode->hdisplay) |
258 MDP4_DMA_SRC_SIZE_HEIGHT(mode->vdisplay));
259
260 /* take data from pipe: */
261 mdp4_write(mdp4_kms, REG_MDP4_DMA_SRC_BASE(dma), 0);
262 mdp4_write(mdp4_kms, REG_MDP4_DMA_SRC_STRIDE(dma), 0);
263 mdp4_write(mdp4_kms, REG_MDP4_DMA_DST_SIZE(dma),
264 MDP4_DMA_DST_SIZE_WIDTH(0) |
265 MDP4_DMA_DST_SIZE_HEIGHT(0));
266
267 mdp4_write(mdp4_kms, REG_MDP4_OVLP_BASE(ovlp), 0);
268 mdp4_write(mdp4_kms, REG_MDP4_OVLP_SIZE(ovlp),
269 MDP4_OVLP_SIZE_WIDTH(mode->hdisplay) |
270 MDP4_OVLP_SIZE_HEIGHT(mode->vdisplay));
271 mdp4_write(mdp4_kms, REG_MDP4_OVLP_STRIDE(ovlp), 0);
272
273 mdp4_write(mdp4_kms, REG_MDP4_OVLP_CFG(ovlp), 1);
274
275 if (dma == DMA_E) {
276 mdp4_write(mdp4_kms, REG_MDP4_DMA_E_QUANT(0), 0x00ff0000);
277 mdp4_write(mdp4_kms, REG_MDP4_DMA_E_QUANT(1), 0x00ff0000);
278 mdp4_write(mdp4_kms, REG_MDP4_DMA_E_QUANT(2), 0x00ff0000);
279 }
280 }
281
mdp4_crtc_atomic_disable(struct drm_crtc * crtc,struct drm_crtc_state * old_state)282 static void mdp4_crtc_atomic_disable(struct drm_crtc *crtc,
283 struct drm_crtc_state *old_state)
284 {
285 struct mdp4_crtc *mdp4_crtc = to_mdp4_crtc(crtc);
286 struct mdp4_kms *mdp4_kms = get_kms(crtc);
287
288 DBG("%s", mdp4_crtc->name);
289
290 if (WARN_ON(!mdp4_crtc->enabled))
291 return;
292
293 mdp_irq_unregister(&mdp4_kms->base, &mdp4_crtc->err);
294 mdp4_disable(mdp4_kms);
295
296 mdp4_crtc->enabled = false;
297 }
298
mdp4_crtc_atomic_enable(struct drm_crtc * crtc,struct drm_crtc_state * old_state)299 static void mdp4_crtc_atomic_enable(struct drm_crtc *crtc,
300 struct drm_crtc_state *old_state)
301 {
302 struct mdp4_crtc *mdp4_crtc = to_mdp4_crtc(crtc);
303 struct mdp4_kms *mdp4_kms = get_kms(crtc);
304
305 DBG("%s", mdp4_crtc->name);
306
307 if (WARN_ON(mdp4_crtc->enabled))
308 return;
309
310 mdp4_enable(mdp4_kms);
311 mdp_irq_register(&mdp4_kms->base, &mdp4_crtc->err);
312
313 crtc_flush(crtc);
314
315 mdp4_crtc->enabled = true;
316 }
317
mdp4_crtc_atomic_check(struct drm_crtc * crtc,struct drm_crtc_state * state)318 static int mdp4_crtc_atomic_check(struct drm_crtc *crtc,
319 struct drm_crtc_state *state)
320 {
321 struct mdp4_crtc *mdp4_crtc = to_mdp4_crtc(crtc);
322 DBG("%s: check", mdp4_crtc->name);
323 // TODO anything else to check?
324 return 0;
325 }
326
mdp4_crtc_atomic_begin(struct drm_crtc * crtc,struct drm_crtc_state * old_crtc_state)327 static void mdp4_crtc_atomic_begin(struct drm_crtc *crtc,
328 struct drm_crtc_state *old_crtc_state)
329 {
330 struct mdp4_crtc *mdp4_crtc = to_mdp4_crtc(crtc);
331 DBG("%s: begin", mdp4_crtc->name);
332 }
333
mdp4_crtc_atomic_flush(struct drm_crtc * crtc,struct drm_crtc_state * old_crtc_state)334 static void mdp4_crtc_atomic_flush(struct drm_crtc *crtc,
335 struct drm_crtc_state *old_crtc_state)
336 {
337 struct mdp4_crtc *mdp4_crtc = to_mdp4_crtc(crtc);
338 struct drm_device *dev = crtc->dev;
339 unsigned long flags;
340
341 DBG("%s: event: %p", mdp4_crtc->name, crtc->state->event);
342
343 WARN_ON(mdp4_crtc->event);
344
345 spin_lock_irqsave(&dev->event_lock, flags);
346 mdp4_crtc->event = crtc->state->event;
347 spin_unlock_irqrestore(&dev->event_lock, flags);
348
349 blend_setup(crtc);
350 crtc_flush(crtc);
351 request_pending(crtc, PENDING_FLIP);
352 }
353
354 #define CURSOR_WIDTH 64
355 #define CURSOR_HEIGHT 64
356
357 /* called from IRQ to update cursor related registers (if needed). The
358 * cursor registers, other than x/y position, appear not to be double
359 * buffered, and changing them other than from vblank seems to trigger
360 * underflow.
361 */
update_cursor(struct drm_crtc * crtc)362 static void update_cursor(struct drm_crtc *crtc)
363 {
364 struct mdp4_crtc *mdp4_crtc = to_mdp4_crtc(crtc);
365 struct mdp4_kms *mdp4_kms = get_kms(crtc);
366 struct msm_kms *kms = &mdp4_kms->base.base;
367 enum mdp4_dma dma = mdp4_crtc->dma;
368 unsigned long flags;
369
370 spin_lock_irqsave(&mdp4_crtc->cursor.lock, flags);
371 if (mdp4_crtc->cursor.stale) {
372 struct drm_gem_object *next_bo = mdp4_crtc->cursor.next_bo;
373 struct drm_gem_object *prev_bo = mdp4_crtc->cursor.scanout_bo;
374 uint64_t iova = mdp4_crtc->cursor.next_iova;
375
376 if (next_bo) {
377 /* take a obj ref + iova ref when we start scanning out: */
378 drm_gem_object_reference(next_bo);
379 msm_gem_get_iova(next_bo, kms->aspace, &iova);
380
381 /* enable cursor: */
382 mdp4_write(mdp4_kms, REG_MDP4_DMA_CURSOR_SIZE(dma),
383 MDP4_DMA_CURSOR_SIZE_WIDTH(mdp4_crtc->cursor.width) |
384 MDP4_DMA_CURSOR_SIZE_HEIGHT(mdp4_crtc->cursor.height));
385 mdp4_write(mdp4_kms, REG_MDP4_DMA_CURSOR_BASE(dma), iova);
386 mdp4_write(mdp4_kms, REG_MDP4_DMA_CURSOR_BLEND_CONFIG(dma),
387 MDP4_DMA_CURSOR_BLEND_CONFIG_FORMAT(CURSOR_ARGB) |
388 MDP4_DMA_CURSOR_BLEND_CONFIG_CURSOR_EN);
389 } else {
390 /* disable cursor: */
391 mdp4_write(mdp4_kms, REG_MDP4_DMA_CURSOR_BASE(dma),
392 mdp4_kms->blank_cursor_iova);
393 }
394
395 /* and drop the iova ref + obj rev when done scanning out: */
396 if (prev_bo)
397 drm_flip_work_queue(&mdp4_crtc->unref_cursor_work, prev_bo);
398
399 mdp4_crtc->cursor.scanout_bo = next_bo;
400 mdp4_crtc->cursor.stale = false;
401 }
402
403 mdp4_write(mdp4_kms, REG_MDP4_DMA_CURSOR_POS(dma),
404 MDP4_DMA_CURSOR_POS_X(mdp4_crtc->cursor.x) |
405 MDP4_DMA_CURSOR_POS_Y(mdp4_crtc->cursor.y));
406
407 spin_unlock_irqrestore(&mdp4_crtc->cursor.lock, flags);
408 }
409
mdp4_crtc_cursor_set(struct drm_crtc * crtc,struct drm_file * file_priv,uint32_t handle,uint32_t width,uint32_t height)410 static int mdp4_crtc_cursor_set(struct drm_crtc *crtc,
411 struct drm_file *file_priv, uint32_t handle,
412 uint32_t width, uint32_t height)
413 {
414 struct mdp4_crtc *mdp4_crtc = to_mdp4_crtc(crtc);
415 struct mdp4_kms *mdp4_kms = get_kms(crtc);
416 struct msm_kms *kms = &mdp4_kms->base.base;
417 struct drm_device *dev = crtc->dev;
418 struct drm_gem_object *cursor_bo, *old_bo;
419 unsigned long flags;
420 uint64_t iova;
421 int ret;
422
423 if ((width > CURSOR_WIDTH) || (height > CURSOR_HEIGHT)) {
424 dev_err(dev->dev, "bad cursor size: %dx%d\n", width, height);
425 return -EINVAL;
426 }
427
428 if (handle) {
429 cursor_bo = drm_gem_object_lookup(file_priv, handle);
430 if (!cursor_bo)
431 return -ENOENT;
432 } else {
433 cursor_bo = NULL;
434 }
435
436 if (cursor_bo) {
437 ret = msm_gem_get_iova(cursor_bo, kms->aspace, &iova);
438 if (ret)
439 goto fail;
440 } else {
441 iova = 0;
442 }
443
444 spin_lock_irqsave(&mdp4_crtc->cursor.lock, flags);
445 old_bo = mdp4_crtc->cursor.next_bo;
446 mdp4_crtc->cursor.next_bo = cursor_bo;
447 mdp4_crtc->cursor.next_iova = iova;
448 mdp4_crtc->cursor.width = width;
449 mdp4_crtc->cursor.height = height;
450 mdp4_crtc->cursor.stale = true;
451 spin_unlock_irqrestore(&mdp4_crtc->cursor.lock, flags);
452
453 if (old_bo) {
454 /* drop our previous reference: */
455 drm_flip_work_queue(&mdp4_crtc->unref_cursor_work, old_bo);
456 }
457
458 request_pending(crtc, PENDING_CURSOR);
459
460 return 0;
461
462 fail:
463 drm_gem_object_unreference_unlocked(cursor_bo);
464 return ret;
465 }
466
mdp4_crtc_cursor_move(struct drm_crtc * crtc,int x,int y)467 static int mdp4_crtc_cursor_move(struct drm_crtc *crtc, int x, int y)
468 {
469 struct mdp4_crtc *mdp4_crtc = to_mdp4_crtc(crtc);
470 unsigned long flags;
471
472 spin_lock_irqsave(&mdp4_crtc->cursor.lock, flags);
473 mdp4_crtc->cursor.x = x;
474 mdp4_crtc->cursor.y = y;
475 spin_unlock_irqrestore(&mdp4_crtc->cursor.lock, flags);
476
477 crtc_flush(crtc);
478 request_pending(crtc, PENDING_CURSOR);
479
480 return 0;
481 }
482
483 static const struct drm_crtc_funcs mdp4_crtc_funcs = {
484 .set_config = drm_atomic_helper_set_config,
485 .destroy = mdp4_crtc_destroy,
486 .page_flip = drm_atomic_helper_page_flip,
487 .cursor_set = mdp4_crtc_cursor_set,
488 .cursor_move = mdp4_crtc_cursor_move,
489 .reset = drm_atomic_helper_crtc_reset,
490 .atomic_duplicate_state = drm_atomic_helper_crtc_duplicate_state,
491 .atomic_destroy_state = drm_atomic_helper_crtc_destroy_state,
492 };
493
494 static const struct drm_crtc_helper_funcs mdp4_crtc_helper_funcs = {
495 .mode_set_nofb = mdp4_crtc_mode_set_nofb,
496 .atomic_check = mdp4_crtc_atomic_check,
497 .atomic_begin = mdp4_crtc_atomic_begin,
498 .atomic_flush = mdp4_crtc_atomic_flush,
499 .atomic_enable = mdp4_crtc_atomic_enable,
500 .atomic_disable = mdp4_crtc_atomic_disable,
501 };
502
mdp4_crtc_vblank_irq(struct mdp_irq * irq,uint32_t irqstatus)503 static void mdp4_crtc_vblank_irq(struct mdp_irq *irq, uint32_t irqstatus)
504 {
505 struct mdp4_crtc *mdp4_crtc = container_of(irq, struct mdp4_crtc, vblank);
506 struct drm_crtc *crtc = &mdp4_crtc->base;
507 struct msm_drm_private *priv = crtc->dev->dev_private;
508 unsigned pending;
509
510 mdp_irq_unregister(&get_kms(crtc)->base, &mdp4_crtc->vblank);
511
512 pending = atomic_xchg(&mdp4_crtc->pending, 0);
513
514 if (pending & PENDING_FLIP) {
515 complete_flip(crtc, NULL);
516 }
517
518 if (pending & PENDING_CURSOR) {
519 update_cursor(crtc);
520 drm_flip_work_commit(&mdp4_crtc->unref_cursor_work, priv->wq);
521 }
522 }
523
mdp4_crtc_err_irq(struct mdp_irq * irq,uint32_t irqstatus)524 static void mdp4_crtc_err_irq(struct mdp_irq *irq, uint32_t irqstatus)
525 {
526 struct mdp4_crtc *mdp4_crtc = container_of(irq, struct mdp4_crtc, err);
527 struct drm_crtc *crtc = &mdp4_crtc->base;
528 DBG("%s: error: %08x", mdp4_crtc->name, irqstatus);
529 crtc_flush(crtc);
530 }
531
mdp4_crtc_wait_for_flush_done(struct drm_crtc * crtc)532 static void mdp4_crtc_wait_for_flush_done(struct drm_crtc *crtc)
533 {
534 struct drm_device *dev = crtc->dev;
535 struct mdp4_crtc *mdp4_crtc = to_mdp4_crtc(crtc);
536 struct mdp4_kms *mdp4_kms = get_kms(crtc);
537 int ret;
538
539 ret = drm_crtc_vblank_get(crtc);
540 if (ret)
541 return;
542
543 ret = wait_event_timeout(dev->vblank[drm_crtc_index(crtc)].queue,
544 !(mdp4_read(mdp4_kms, REG_MDP4_OVERLAY_FLUSH) &
545 mdp4_crtc->flushed_mask),
546 msecs_to_jiffies(50));
547 if (ret <= 0)
548 dev_warn(dev->dev, "vblank time out, crtc=%d\n", mdp4_crtc->id);
549
550 mdp4_crtc->flushed_mask = 0;
551
552 drm_crtc_vblank_put(crtc);
553 }
554
mdp4_crtc_vblank(struct drm_crtc * crtc)555 uint32_t mdp4_crtc_vblank(struct drm_crtc *crtc)
556 {
557 struct mdp4_crtc *mdp4_crtc = to_mdp4_crtc(crtc);
558 return mdp4_crtc->vblank.irqmask;
559 }
560
561 /* set dma config, ie. the format the encoder wants. */
mdp4_crtc_set_config(struct drm_crtc * crtc,uint32_t config)562 void mdp4_crtc_set_config(struct drm_crtc *crtc, uint32_t config)
563 {
564 struct mdp4_crtc *mdp4_crtc = to_mdp4_crtc(crtc);
565 struct mdp4_kms *mdp4_kms = get_kms(crtc);
566
567 mdp4_write(mdp4_kms, REG_MDP4_DMA_CONFIG(mdp4_crtc->dma), config);
568 }
569
570 /* set interface for routing crtc->encoder: */
mdp4_crtc_set_intf(struct drm_crtc * crtc,enum mdp4_intf intf,int mixer)571 void mdp4_crtc_set_intf(struct drm_crtc *crtc, enum mdp4_intf intf, int mixer)
572 {
573 struct mdp4_crtc *mdp4_crtc = to_mdp4_crtc(crtc);
574 struct mdp4_kms *mdp4_kms = get_kms(crtc);
575 uint32_t intf_sel;
576
577 intf_sel = mdp4_read(mdp4_kms, REG_MDP4_DISP_INTF_SEL);
578
579 switch (mdp4_crtc->dma) {
580 case DMA_P:
581 intf_sel &= ~MDP4_DISP_INTF_SEL_PRIM__MASK;
582 intf_sel |= MDP4_DISP_INTF_SEL_PRIM(intf);
583 break;
584 case DMA_S:
585 intf_sel &= ~MDP4_DISP_INTF_SEL_SEC__MASK;
586 intf_sel |= MDP4_DISP_INTF_SEL_SEC(intf);
587 break;
588 case DMA_E:
589 intf_sel &= ~MDP4_DISP_INTF_SEL_EXT__MASK;
590 intf_sel |= MDP4_DISP_INTF_SEL_EXT(intf);
591 break;
592 }
593
594 if (intf == INTF_DSI_VIDEO) {
595 intf_sel &= ~MDP4_DISP_INTF_SEL_DSI_CMD;
596 intf_sel |= MDP4_DISP_INTF_SEL_DSI_VIDEO;
597 } else if (intf == INTF_DSI_CMD) {
598 intf_sel &= ~MDP4_DISP_INTF_SEL_DSI_VIDEO;
599 intf_sel |= MDP4_DISP_INTF_SEL_DSI_CMD;
600 }
601
602 mdp4_crtc->mixer = mixer;
603
604 blend_setup(crtc);
605
606 DBG("%s: intf_sel=%08x", mdp4_crtc->name, intf_sel);
607
608 mdp4_write(mdp4_kms, REG_MDP4_DISP_INTF_SEL, intf_sel);
609 }
610
mdp4_crtc_wait_for_commit_done(struct drm_crtc * crtc)611 void mdp4_crtc_wait_for_commit_done(struct drm_crtc *crtc)
612 {
613 /* wait_for_flush_done is the only case for now.
614 * Later we will have command mode CRTC to wait for
615 * other event.
616 */
617 mdp4_crtc_wait_for_flush_done(crtc);
618 }
619
620 static const char *dma_names[] = {
621 "DMA_P", "DMA_S", "DMA_E",
622 };
623
624 /* initialize crtc */
mdp4_crtc_init(struct drm_device * dev,struct drm_plane * plane,int id,int ovlp_id,enum mdp4_dma dma_id)625 struct drm_crtc *mdp4_crtc_init(struct drm_device *dev,
626 struct drm_plane *plane, int id, int ovlp_id,
627 enum mdp4_dma dma_id)
628 {
629 struct drm_crtc *crtc = NULL;
630 struct mdp4_crtc *mdp4_crtc;
631
632 mdp4_crtc = kzalloc(sizeof(*mdp4_crtc), GFP_KERNEL);
633 if (!mdp4_crtc)
634 return ERR_PTR(-ENOMEM);
635
636 crtc = &mdp4_crtc->base;
637
638 mdp4_crtc->id = id;
639
640 mdp4_crtc->ovlp = ovlp_id;
641 mdp4_crtc->dma = dma_id;
642
643 mdp4_crtc->vblank.irqmask = dma2irq(mdp4_crtc->dma);
644 mdp4_crtc->vblank.irq = mdp4_crtc_vblank_irq;
645
646 mdp4_crtc->err.irqmask = dma2err(mdp4_crtc->dma);
647 mdp4_crtc->err.irq = mdp4_crtc_err_irq;
648
649 snprintf(mdp4_crtc->name, sizeof(mdp4_crtc->name), "%s:%d",
650 dma_names[dma_id], ovlp_id);
651
652 spin_lock_init(&mdp4_crtc->cursor.lock);
653
654 drm_flip_work_init(&mdp4_crtc->unref_cursor_work,
655 "unref cursor", unref_cursor_worker);
656
657 drm_crtc_init_with_planes(dev, crtc, plane, NULL, &mdp4_crtc_funcs,
658 NULL);
659 drm_crtc_helper_add(crtc, &mdp4_crtc_helper_funcs);
660 plane->crtc = crtc;
661
662 return crtc;
663 }
664