1 /*
2 * Copyright 2012 Red Hat Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 * Authors: Ben Skeggs
23 */
24 #include "dmacnv50.h"
25 #include "rootnv50.h"
26
27 #include <core/ramht.h>
28 #include <subdev/timer.h>
29
30 int
gf119_disp_dmac_bind(struct nv50_disp_dmac * chan,struct nvkm_object * object,u32 handle)31 gf119_disp_dmac_bind(struct nv50_disp_dmac *chan,
32 struct nvkm_object *object, u32 handle)
33 {
34 return nvkm_ramht_insert(chan->base.root->ramht, object,
35 chan->base.chid.user, -9, handle,
36 chan->base.chid.user << 27 | 0x00000001);
37 }
38
39 void
gf119_disp_dmac_fini(struct nv50_disp_dmac * chan)40 gf119_disp_dmac_fini(struct nv50_disp_dmac *chan)
41 {
42 struct nv50_disp *disp = chan->base.root->disp;
43 struct nvkm_subdev *subdev = &disp->base.engine.subdev;
44 struct nvkm_device *device = subdev->device;
45 int ctrl = chan->base.chid.ctrl;
46 int user = chan->base.chid.user;
47
48 /* deactivate channel */
49 nvkm_mask(device, 0x610490 + (ctrl * 0x0010), 0x00001010, 0x00001000);
50 nvkm_mask(device, 0x610490 + (ctrl * 0x0010), 0x00000003, 0x00000000);
51 if (nvkm_msec(device, 2000,
52 if (!(nvkm_rd32(device, 0x610490 + (ctrl * 0x10)) & 0x001e0000))
53 break;
54 ) < 0) {
55 nvkm_error(subdev, "ch %d fini: %08x\n", user,
56 nvkm_rd32(device, 0x610490 + (ctrl * 0x10)));
57 }
58
59 /* disable error reporting and completion notification */
60 nvkm_mask(device, 0x610090, 0x00000001 << user, 0x00000000);
61 nvkm_mask(device, 0x6100a0, 0x00000001 << user, 0x00000000);
62 }
63
64 static int
gf119_disp_dmac_init(struct nv50_disp_dmac * chan)65 gf119_disp_dmac_init(struct nv50_disp_dmac *chan)
66 {
67 struct nv50_disp *disp = chan->base.root->disp;
68 struct nvkm_subdev *subdev = &disp->base.engine.subdev;
69 struct nvkm_device *device = subdev->device;
70 int ctrl = chan->base.chid.ctrl;
71 int user = chan->base.chid.user;
72
73 /* enable error reporting */
74 nvkm_mask(device, 0x6100a0, 0x00000001 << user, 0x00000001 << user);
75
76 /* initialise channel for dma command submission */
77 nvkm_wr32(device, 0x610494 + (ctrl * 0x0010), chan->push);
78 nvkm_wr32(device, 0x610498 + (ctrl * 0x0010), 0x00010000);
79 nvkm_wr32(device, 0x61049c + (ctrl * 0x0010), 0x00000001);
80 nvkm_mask(device, 0x610490 + (ctrl * 0x0010), 0x00000010, 0x00000010);
81 nvkm_wr32(device, 0x640000 + (ctrl * 0x1000), 0x00000000);
82 nvkm_wr32(device, 0x610490 + (ctrl * 0x0010), 0x00000013);
83
84 /* wait for it to go inactive */
85 if (nvkm_msec(device, 2000,
86 if (!(nvkm_rd32(device, 0x610490 + (ctrl * 0x10)) & 0x80000000))
87 break;
88 ) < 0) {
89 nvkm_error(subdev, "ch %d init: %08x\n", user,
90 nvkm_rd32(device, 0x610490 + (ctrl * 0x10)));
91 return -EBUSY;
92 }
93
94 return 0;
95 }
96
97 const struct nv50_disp_dmac_func
98 gf119_disp_dmac_func = {
99 .init = gf119_disp_dmac_init,
100 .fini = gf119_disp_dmac_fini,
101 .bind = gf119_disp_dmac_bind,
102 };
103