1 /*
2 * Copyright (C) 2013, NVIDIA Corporation. All rights reserved.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sub license,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the
12 * next paragraph) shall be included in all copies or substantial portions
13 * of the Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
21 * DEALINGS IN THE SOFTWARE.
22 */
23
24 #include <linux/backlight.h>
25 #include <linux/gpio/consumer.h>
26 #include <linux/module.h>
27 #include <linux/of_platform.h>
28 #include <linux/platform_device.h>
29 #include <linux/regulator/consumer.h>
30
31 #include <drm/drmP.h>
32 #include <drm/drm_crtc.h>
33 #include <drm/drm_mipi_dsi.h>
34 #include <drm/drm_panel.h>
35
36 #include <video/display_timing.h>
37 #include <video/videomode.h>
38
39 struct panel_desc {
40 const struct drm_display_mode *modes;
41 unsigned int num_modes;
42 const struct display_timing *timings;
43 unsigned int num_timings;
44
45 unsigned int bpc;
46
47 /**
48 * @width: width (in millimeters) of the panel's active display area
49 * @height: height (in millimeters) of the panel's active display area
50 */
51 struct {
52 unsigned int width;
53 unsigned int height;
54 } size;
55
56 /**
57 * @prepare: the time (in milliseconds) that it takes for the panel to
58 * become ready and start receiving video data
59 * @enable: the time (in milliseconds) that it takes for the panel to
60 * display the first valid frame after starting to receive
61 * video data
62 * @disable: the time (in milliseconds) that it takes for the panel to
63 * turn the display off (no content is visible)
64 * @unprepare: the time (in milliseconds) that it takes for the panel
65 * to power itself down completely
66 */
67 struct {
68 unsigned int prepare;
69 unsigned int enable;
70 unsigned int disable;
71 unsigned int unprepare;
72 } delay;
73
74 u32 bus_format;
75 u32 bus_flags;
76 };
77
78 struct panel_simple {
79 struct drm_panel base;
80 bool prepared;
81 bool enabled;
82
83 const struct panel_desc *desc;
84
85 struct backlight_device *backlight;
86 struct regulator *supply;
87 struct i2c_adapter *ddc;
88
89 struct gpio_desc *enable_gpio;
90 };
91
to_panel_simple(struct drm_panel * panel)92 static inline struct panel_simple *to_panel_simple(struct drm_panel *panel)
93 {
94 return container_of(panel, struct panel_simple, base);
95 }
96
panel_simple_get_fixed_modes(struct panel_simple * panel)97 static int panel_simple_get_fixed_modes(struct panel_simple *panel)
98 {
99 struct drm_connector *connector = panel->base.connector;
100 struct drm_device *drm = panel->base.drm;
101 struct drm_display_mode *mode;
102 unsigned int i, num = 0;
103
104 if (!panel->desc)
105 return 0;
106
107 for (i = 0; i < panel->desc->num_timings; i++) {
108 const struct display_timing *dt = &panel->desc->timings[i];
109 struct videomode vm;
110
111 videomode_from_timing(dt, &vm);
112 mode = drm_mode_create(drm);
113 if (!mode) {
114 dev_err(drm->dev, "failed to add mode %ux%u\n",
115 dt->hactive.typ, dt->vactive.typ);
116 continue;
117 }
118
119 drm_display_mode_from_videomode(&vm, mode);
120
121 mode->type |= DRM_MODE_TYPE_DRIVER;
122
123 if (panel->desc->num_timings == 1)
124 mode->type |= DRM_MODE_TYPE_PREFERRED;
125
126 drm_mode_probed_add(connector, mode);
127 num++;
128 }
129
130 for (i = 0; i < panel->desc->num_modes; i++) {
131 const struct drm_display_mode *m = &panel->desc->modes[i];
132
133 mode = drm_mode_duplicate(drm, m);
134 if (!mode) {
135 dev_err(drm->dev, "failed to add mode %ux%u@%u\n",
136 m->hdisplay, m->vdisplay, m->vrefresh);
137 continue;
138 }
139
140 mode->type |= DRM_MODE_TYPE_DRIVER;
141
142 if (panel->desc->num_modes == 1)
143 mode->type |= DRM_MODE_TYPE_PREFERRED;
144
145 drm_mode_set_name(mode);
146
147 drm_mode_probed_add(connector, mode);
148 num++;
149 }
150
151 connector->display_info.bpc = panel->desc->bpc;
152 connector->display_info.width_mm = panel->desc->size.width;
153 connector->display_info.height_mm = panel->desc->size.height;
154 if (panel->desc->bus_format)
155 drm_display_info_set_bus_formats(&connector->display_info,
156 &panel->desc->bus_format, 1);
157 connector->display_info.bus_flags = panel->desc->bus_flags;
158
159 return num;
160 }
161
panel_simple_disable(struct drm_panel * panel)162 static int panel_simple_disable(struct drm_panel *panel)
163 {
164 struct panel_simple *p = to_panel_simple(panel);
165
166 if (!p->enabled)
167 return 0;
168
169 if (p->backlight) {
170 p->backlight->props.power = FB_BLANK_POWERDOWN;
171 p->backlight->props.state |= BL_CORE_FBBLANK;
172 backlight_update_status(p->backlight);
173 }
174
175 if (p->desc->delay.disable)
176 msleep(p->desc->delay.disable);
177
178 p->enabled = false;
179
180 return 0;
181 }
182
panel_simple_unprepare(struct drm_panel * panel)183 static int panel_simple_unprepare(struct drm_panel *panel)
184 {
185 struct panel_simple *p = to_panel_simple(panel);
186
187 if (!p->prepared)
188 return 0;
189
190 if (p->enable_gpio)
191 gpiod_set_value_cansleep(p->enable_gpio, 0);
192
193 regulator_disable(p->supply);
194
195 if (p->desc->delay.unprepare)
196 msleep(p->desc->delay.unprepare);
197
198 p->prepared = false;
199
200 return 0;
201 }
202
panel_simple_prepare(struct drm_panel * panel)203 static int panel_simple_prepare(struct drm_panel *panel)
204 {
205 struct panel_simple *p = to_panel_simple(panel);
206 int err;
207
208 if (p->prepared)
209 return 0;
210
211 err = regulator_enable(p->supply);
212 if (err < 0) {
213 dev_err(panel->dev, "failed to enable supply: %d\n", err);
214 return err;
215 }
216
217 if (p->enable_gpio)
218 gpiod_set_value_cansleep(p->enable_gpio, 1);
219
220 if (p->desc->delay.prepare)
221 msleep(p->desc->delay.prepare);
222
223 p->prepared = true;
224
225 return 0;
226 }
227
panel_simple_enable(struct drm_panel * panel)228 static int panel_simple_enable(struct drm_panel *panel)
229 {
230 struct panel_simple *p = to_panel_simple(panel);
231
232 if (p->enabled)
233 return 0;
234
235 if (p->desc->delay.enable)
236 msleep(p->desc->delay.enable);
237
238 if (p->backlight) {
239 p->backlight->props.state &= ~BL_CORE_FBBLANK;
240 p->backlight->props.power = FB_BLANK_UNBLANK;
241 backlight_update_status(p->backlight);
242 }
243
244 p->enabled = true;
245
246 return 0;
247 }
248
panel_simple_get_modes(struct drm_panel * panel)249 static int panel_simple_get_modes(struct drm_panel *panel)
250 {
251 struct panel_simple *p = to_panel_simple(panel);
252 int num = 0;
253
254 /* probe EDID if a DDC bus is available */
255 if (p->ddc) {
256 struct edid *edid = drm_get_edid(panel->connector, p->ddc);
257 drm_mode_connector_update_edid_property(panel->connector, edid);
258 if (edid) {
259 num += drm_add_edid_modes(panel->connector, edid);
260 kfree(edid);
261 }
262 }
263
264 /* add hard-coded panel modes */
265 num += panel_simple_get_fixed_modes(p);
266
267 return num;
268 }
269
panel_simple_get_timings(struct drm_panel * panel,unsigned int num_timings,struct display_timing * timings)270 static int panel_simple_get_timings(struct drm_panel *panel,
271 unsigned int num_timings,
272 struct display_timing *timings)
273 {
274 struct panel_simple *p = to_panel_simple(panel);
275 unsigned int i;
276
277 if (p->desc->num_timings < num_timings)
278 num_timings = p->desc->num_timings;
279
280 if (timings)
281 for (i = 0; i < num_timings; i++)
282 timings[i] = p->desc->timings[i];
283
284 return p->desc->num_timings;
285 }
286
287 static const struct drm_panel_funcs panel_simple_funcs = {
288 .disable = panel_simple_disable,
289 .unprepare = panel_simple_unprepare,
290 .prepare = panel_simple_prepare,
291 .enable = panel_simple_enable,
292 .get_modes = panel_simple_get_modes,
293 .get_timings = panel_simple_get_timings,
294 };
295
panel_simple_probe(struct device * dev,const struct panel_desc * desc)296 static int panel_simple_probe(struct device *dev, const struct panel_desc *desc)
297 {
298 struct device_node *backlight, *ddc;
299 struct panel_simple *panel;
300 int err;
301
302 panel = devm_kzalloc(dev, sizeof(*panel), GFP_KERNEL);
303 if (!panel)
304 return -ENOMEM;
305
306 panel->enabled = false;
307 panel->prepared = false;
308 panel->desc = desc;
309
310 panel->supply = devm_regulator_get(dev, "power");
311 if (IS_ERR(panel->supply))
312 return PTR_ERR(panel->supply);
313
314 panel->enable_gpio = devm_gpiod_get_optional(dev, "enable",
315 GPIOD_OUT_LOW);
316 if (IS_ERR(panel->enable_gpio)) {
317 err = PTR_ERR(panel->enable_gpio);
318 dev_err(dev, "failed to request GPIO: %d\n", err);
319 return err;
320 }
321
322 backlight = of_parse_phandle(dev->of_node, "backlight", 0);
323 if (backlight) {
324 panel->backlight = of_find_backlight_by_node(backlight);
325 of_node_put(backlight);
326
327 if (!panel->backlight)
328 return -EPROBE_DEFER;
329 }
330
331 ddc = of_parse_phandle(dev->of_node, "ddc-i2c-bus", 0);
332 if (ddc) {
333 panel->ddc = of_find_i2c_adapter_by_node(ddc);
334 of_node_put(ddc);
335
336 if (!panel->ddc) {
337 err = -EPROBE_DEFER;
338 goto free_backlight;
339 }
340 }
341
342 drm_panel_init(&panel->base);
343 panel->base.dev = dev;
344 panel->base.funcs = &panel_simple_funcs;
345
346 err = drm_panel_add(&panel->base);
347 if (err < 0)
348 goto free_ddc;
349
350 dev_set_drvdata(dev, panel);
351
352 return 0;
353
354 free_ddc:
355 if (panel->ddc)
356 put_device(&panel->ddc->dev);
357 free_backlight:
358 if (panel->backlight)
359 put_device(&panel->backlight->dev);
360
361 return err;
362 }
363
panel_simple_remove(struct device * dev)364 static int panel_simple_remove(struct device *dev)
365 {
366 struct panel_simple *panel = dev_get_drvdata(dev);
367
368 drm_panel_detach(&panel->base);
369 drm_panel_remove(&panel->base);
370
371 panel_simple_disable(&panel->base);
372 panel_simple_unprepare(&panel->base);
373
374 if (panel->ddc)
375 put_device(&panel->ddc->dev);
376
377 if (panel->backlight)
378 put_device(&panel->backlight->dev);
379
380 return 0;
381 }
382
panel_simple_shutdown(struct device * dev)383 static void panel_simple_shutdown(struct device *dev)
384 {
385 struct panel_simple *panel = dev_get_drvdata(dev);
386
387 panel_simple_disable(&panel->base);
388 panel_simple_unprepare(&panel->base);
389 }
390
391 static const struct drm_display_mode ampire_am_480272h3tmqw_t01h_mode = {
392 .clock = 9000,
393 .hdisplay = 480,
394 .hsync_start = 480 + 2,
395 .hsync_end = 480 + 2 + 41,
396 .htotal = 480 + 2 + 41 + 2,
397 .vdisplay = 272,
398 .vsync_start = 272 + 2,
399 .vsync_end = 272 + 2 + 10,
400 .vtotal = 272 + 2 + 10 + 2,
401 .vrefresh = 60,
402 .flags = DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC,
403 };
404
405 static const struct panel_desc ampire_am_480272h3tmqw_t01h = {
406 .modes = &ire_am_480272h3tmqw_t01h_mode,
407 .num_modes = 1,
408 .bpc = 8,
409 .size = {
410 .width = 105,
411 .height = 67,
412 },
413 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
414 };
415
416 static const struct drm_display_mode ampire_am800480r3tmqwa1h_mode = {
417 .clock = 33333,
418 .hdisplay = 800,
419 .hsync_start = 800 + 0,
420 .hsync_end = 800 + 0 + 255,
421 .htotal = 800 + 0 + 255 + 0,
422 .vdisplay = 480,
423 .vsync_start = 480 + 2,
424 .vsync_end = 480 + 2 + 45,
425 .vtotal = 480 + 2 + 45 + 0,
426 .vrefresh = 60,
427 .flags = DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC,
428 };
429
430 static const struct panel_desc ampire_am800480r3tmqwa1h = {
431 .modes = &ire_am800480r3tmqwa1h_mode,
432 .num_modes = 1,
433 .bpc = 6,
434 .size = {
435 .width = 152,
436 .height = 91,
437 },
438 .bus_format = MEDIA_BUS_FMT_RGB666_1X18,
439 };
440
441 static const struct drm_display_mode auo_b101aw03_mode = {
442 .clock = 51450,
443 .hdisplay = 1024,
444 .hsync_start = 1024 + 156,
445 .hsync_end = 1024 + 156 + 8,
446 .htotal = 1024 + 156 + 8 + 156,
447 .vdisplay = 600,
448 .vsync_start = 600 + 16,
449 .vsync_end = 600 + 16 + 6,
450 .vtotal = 600 + 16 + 6 + 16,
451 .vrefresh = 60,
452 };
453
454 static const struct panel_desc auo_b101aw03 = {
455 .modes = &auo_b101aw03_mode,
456 .num_modes = 1,
457 .bpc = 6,
458 .size = {
459 .width = 223,
460 .height = 125,
461 },
462 };
463
464 static const struct drm_display_mode auo_b101ean01_mode = {
465 .clock = 72500,
466 .hdisplay = 1280,
467 .hsync_start = 1280 + 119,
468 .hsync_end = 1280 + 119 + 32,
469 .htotal = 1280 + 119 + 32 + 21,
470 .vdisplay = 800,
471 .vsync_start = 800 + 4,
472 .vsync_end = 800 + 4 + 20,
473 .vtotal = 800 + 4 + 20 + 8,
474 .vrefresh = 60,
475 };
476
477 static const struct panel_desc auo_b101ean01 = {
478 .modes = &auo_b101ean01_mode,
479 .num_modes = 1,
480 .bpc = 6,
481 .size = {
482 .width = 217,
483 .height = 136,
484 },
485 };
486
487 static const struct drm_display_mode auo_b101xtn01_mode = {
488 .clock = 72000,
489 .hdisplay = 1366,
490 .hsync_start = 1366 + 20,
491 .hsync_end = 1366 + 20 + 70,
492 .htotal = 1366 + 20 + 70,
493 .vdisplay = 768,
494 .vsync_start = 768 + 14,
495 .vsync_end = 768 + 14 + 42,
496 .vtotal = 768 + 14 + 42,
497 .vrefresh = 60,
498 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC,
499 };
500
501 static const struct panel_desc auo_b101xtn01 = {
502 .modes = &auo_b101xtn01_mode,
503 .num_modes = 1,
504 .bpc = 6,
505 .size = {
506 .width = 223,
507 .height = 125,
508 },
509 };
510
511 static const struct drm_display_mode auo_b116xw03_mode = {
512 .clock = 70589,
513 .hdisplay = 1366,
514 .hsync_start = 1366 + 40,
515 .hsync_end = 1366 + 40 + 40,
516 .htotal = 1366 + 40 + 40 + 32,
517 .vdisplay = 768,
518 .vsync_start = 768 + 10,
519 .vsync_end = 768 + 10 + 12,
520 .vtotal = 768 + 10 + 12 + 6,
521 .vrefresh = 60,
522 };
523
524 static const struct panel_desc auo_b116xw03 = {
525 .modes = &auo_b116xw03_mode,
526 .num_modes = 1,
527 .bpc = 6,
528 .size = {
529 .width = 256,
530 .height = 144,
531 },
532 };
533
534 static const struct drm_display_mode auo_b133xtn01_mode = {
535 .clock = 69500,
536 .hdisplay = 1366,
537 .hsync_start = 1366 + 48,
538 .hsync_end = 1366 + 48 + 32,
539 .htotal = 1366 + 48 + 32 + 20,
540 .vdisplay = 768,
541 .vsync_start = 768 + 3,
542 .vsync_end = 768 + 3 + 6,
543 .vtotal = 768 + 3 + 6 + 13,
544 .vrefresh = 60,
545 };
546
547 static const struct panel_desc auo_b133xtn01 = {
548 .modes = &auo_b133xtn01_mode,
549 .num_modes = 1,
550 .bpc = 6,
551 .size = {
552 .width = 293,
553 .height = 165,
554 },
555 };
556
557 static const struct drm_display_mode auo_b133htn01_mode = {
558 .clock = 150660,
559 .hdisplay = 1920,
560 .hsync_start = 1920 + 172,
561 .hsync_end = 1920 + 172 + 80,
562 .htotal = 1920 + 172 + 80 + 60,
563 .vdisplay = 1080,
564 .vsync_start = 1080 + 25,
565 .vsync_end = 1080 + 25 + 10,
566 .vtotal = 1080 + 25 + 10 + 10,
567 .vrefresh = 60,
568 };
569
570 static const struct panel_desc auo_b133htn01 = {
571 .modes = &auo_b133htn01_mode,
572 .num_modes = 1,
573 .bpc = 6,
574 .size = {
575 .width = 293,
576 .height = 165,
577 },
578 .delay = {
579 .prepare = 105,
580 .enable = 20,
581 .unprepare = 50,
582 },
583 };
584
585 static const struct display_timing auo_g133han01_timings = {
586 .pixelclock = { 134000000, 141200000, 149000000 },
587 .hactive = { 1920, 1920, 1920 },
588 .hfront_porch = { 39, 58, 77 },
589 .hback_porch = { 59, 88, 117 },
590 .hsync_len = { 28, 42, 56 },
591 .vactive = { 1080, 1080, 1080 },
592 .vfront_porch = { 3, 8, 11 },
593 .vback_porch = { 5, 14, 19 },
594 .vsync_len = { 4, 14, 19 },
595 };
596
597 static const struct panel_desc auo_g133han01 = {
598 .timings = &auo_g133han01_timings,
599 .num_timings = 1,
600 .bpc = 8,
601 .size = {
602 .width = 293,
603 .height = 165,
604 },
605 .delay = {
606 .prepare = 200,
607 .enable = 50,
608 .disable = 50,
609 .unprepare = 1000,
610 },
611 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_JEIDA,
612 };
613
614 static const struct display_timing auo_g185han01_timings = {
615 .pixelclock = { 120000000, 144000000, 175000000 },
616 .hactive = { 1920, 1920, 1920 },
617 .hfront_porch = { 36, 120, 148 },
618 .hback_porch = { 24, 88, 108 },
619 .hsync_len = { 20, 48, 64 },
620 .vactive = { 1080, 1080, 1080 },
621 .vfront_porch = { 6, 10, 40 },
622 .vback_porch = { 2, 5, 20 },
623 .vsync_len = { 2, 5, 20 },
624 };
625
626 static const struct panel_desc auo_g185han01 = {
627 .timings = &auo_g185han01_timings,
628 .num_timings = 1,
629 .bpc = 8,
630 .size = {
631 .width = 409,
632 .height = 230,
633 },
634 .delay = {
635 .prepare = 50,
636 .enable = 200,
637 .disable = 110,
638 .unprepare = 1000,
639 },
640 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
641 };
642
643 static const struct display_timing auo_p320hvn03_timings = {
644 .pixelclock = { 106000000, 148500000, 164000000 },
645 .hactive = { 1920, 1920, 1920 },
646 .hfront_porch = { 25, 50, 130 },
647 .hback_porch = { 25, 50, 130 },
648 .hsync_len = { 20, 40, 105 },
649 .vactive = { 1080, 1080, 1080 },
650 .vfront_porch = { 8, 17, 150 },
651 .vback_porch = { 8, 17, 150 },
652 .vsync_len = { 4, 11, 100 },
653 };
654
655 static const struct panel_desc auo_p320hvn03 = {
656 .timings = &auo_p320hvn03_timings,
657 .num_timings = 1,
658 .bpc = 8,
659 .size = {
660 .width = 698,
661 .height = 393,
662 },
663 .delay = {
664 .prepare = 1,
665 .enable = 450,
666 .unprepare = 500,
667 },
668 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_JEIDA,
669 };
670
671 static const struct drm_display_mode auo_t215hvn01_mode = {
672 .clock = 148800,
673 .hdisplay = 1920,
674 .hsync_start = 1920 + 88,
675 .hsync_end = 1920 + 88 + 44,
676 .htotal = 1920 + 88 + 44 + 148,
677 .vdisplay = 1080,
678 .vsync_start = 1080 + 4,
679 .vsync_end = 1080 + 4 + 5,
680 .vtotal = 1080 + 4 + 5 + 36,
681 .vrefresh = 60,
682 };
683
684 static const struct panel_desc auo_t215hvn01 = {
685 .modes = &auo_t215hvn01_mode,
686 .num_modes = 1,
687 .bpc = 8,
688 .size = {
689 .width = 430,
690 .height = 270,
691 },
692 .delay = {
693 .disable = 5,
694 .unprepare = 1000,
695 }
696 };
697
698 static const struct drm_display_mode avic_tm070ddh03_mode = {
699 .clock = 51200,
700 .hdisplay = 1024,
701 .hsync_start = 1024 + 160,
702 .hsync_end = 1024 + 160 + 4,
703 .htotal = 1024 + 160 + 4 + 156,
704 .vdisplay = 600,
705 .vsync_start = 600 + 17,
706 .vsync_end = 600 + 17 + 1,
707 .vtotal = 600 + 17 + 1 + 17,
708 .vrefresh = 60,
709 };
710
711 static const struct panel_desc avic_tm070ddh03 = {
712 .modes = &avic_tm070ddh03_mode,
713 .num_modes = 1,
714 .bpc = 8,
715 .size = {
716 .width = 154,
717 .height = 90,
718 },
719 .delay = {
720 .prepare = 20,
721 .enable = 200,
722 .disable = 200,
723 },
724 };
725
726 static const struct drm_display_mode boe_nv101wxmn51_modes[] = {
727 {
728 .clock = 71900,
729 .hdisplay = 1280,
730 .hsync_start = 1280 + 48,
731 .hsync_end = 1280 + 48 + 32,
732 .htotal = 1280 + 48 + 32 + 80,
733 .vdisplay = 800,
734 .vsync_start = 800 + 3,
735 .vsync_end = 800 + 3 + 5,
736 .vtotal = 800 + 3 + 5 + 24,
737 .vrefresh = 60,
738 },
739 {
740 .clock = 57500,
741 .hdisplay = 1280,
742 .hsync_start = 1280 + 48,
743 .hsync_end = 1280 + 48 + 32,
744 .htotal = 1280 + 48 + 32 + 80,
745 .vdisplay = 800,
746 .vsync_start = 800 + 3,
747 .vsync_end = 800 + 3 + 5,
748 .vtotal = 800 + 3 + 5 + 24,
749 .vrefresh = 48,
750 },
751 };
752
753 static const struct panel_desc boe_nv101wxmn51 = {
754 .modes = boe_nv101wxmn51_modes,
755 .num_modes = ARRAY_SIZE(boe_nv101wxmn51_modes),
756 .bpc = 8,
757 .size = {
758 .width = 217,
759 .height = 136,
760 },
761 .delay = {
762 .prepare = 210,
763 .enable = 50,
764 .unprepare = 160,
765 },
766 };
767
768 static const struct drm_display_mode chunghwa_claa070wp03xg_mode = {
769 .clock = 66770,
770 .hdisplay = 800,
771 .hsync_start = 800 + 49,
772 .hsync_end = 800 + 49 + 33,
773 .htotal = 800 + 49 + 33 + 17,
774 .vdisplay = 1280,
775 .vsync_start = 1280 + 1,
776 .vsync_end = 1280 + 1 + 7,
777 .vtotal = 1280 + 1 + 7 + 15,
778 .vrefresh = 60,
779 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC,
780 };
781
782 static const struct panel_desc chunghwa_claa070wp03xg = {
783 .modes = &chunghwa_claa070wp03xg_mode,
784 .num_modes = 1,
785 .bpc = 6,
786 .size = {
787 .width = 94,
788 .height = 150,
789 },
790 };
791
792 static const struct drm_display_mode chunghwa_claa101wa01a_mode = {
793 .clock = 72070,
794 .hdisplay = 1366,
795 .hsync_start = 1366 + 58,
796 .hsync_end = 1366 + 58 + 58,
797 .htotal = 1366 + 58 + 58 + 58,
798 .vdisplay = 768,
799 .vsync_start = 768 + 4,
800 .vsync_end = 768 + 4 + 4,
801 .vtotal = 768 + 4 + 4 + 4,
802 .vrefresh = 60,
803 };
804
805 static const struct panel_desc chunghwa_claa101wa01a = {
806 .modes = &chunghwa_claa101wa01a_mode,
807 .num_modes = 1,
808 .bpc = 6,
809 .size = {
810 .width = 220,
811 .height = 120,
812 },
813 };
814
815 static const struct drm_display_mode chunghwa_claa101wb01_mode = {
816 .clock = 69300,
817 .hdisplay = 1366,
818 .hsync_start = 1366 + 48,
819 .hsync_end = 1366 + 48 + 32,
820 .htotal = 1366 + 48 + 32 + 20,
821 .vdisplay = 768,
822 .vsync_start = 768 + 16,
823 .vsync_end = 768 + 16 + 8,
824 .vtotal = 768 + 16 + 8 + 16,
825 .vrefresh = 60,
826 };
827
828 static const struct panel_desc chunghwa_claa101wb01 = {
829 .modes = &chunghwa_claa101wb01_mode,
830 .num_modes = 1,
831 .bpc = 6,
832 .size = {
833 .width = 223,
834 .height = 125,
835 },
836 };
837
838 static const struct drm_display_mode edt_et057090dhu_mode = {
839 .clock = 25175,
840 .hdisplay = 640,
841 .hsync_start = 640 + 16,
842 .hsync_end = 640 + 16 + 30,
843 .htotal = 640 + 16 + 30 + 114,
844 .vdisplay = 480,
845 .vsync_start = 480 + 10,
846 .vsync_end = 480 + 10 + 3,
847 .vtotal = 480 + 10 + 3 + 32,
848 .vrefresh = 60,
849 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC,
850 };
851
852 static const struct panel_desc edt_et057090dhu = {
853 .modes = &edt_et057090dhu_mode,
854 .num_modes = 1,
855 .bpc = 6,
856 .size = {
857 .width = 115,
858 .height = 86,
859 },
860 .bus_format = MEDIA_BUS_FMT_RGB666_1X18,
861 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_NEGEDGE,
862 };
863
864 static const struct drm_display_mode edt_etm0700g0dh6_mode = {
865 .clock = 33260,
866 .hdisplay = 800,
867 .hsync_start = 800 + 40,
868 .hsync_end = 800 + 40 + 128,
869 .htotal = 800 + 40 + 128 + 88,
870 .vdisplay = 480,
871 .vsync_start = 480 + 10,
872 .vsync_end = 480 + 10 + 2,
873 .vtotal = 480 + 10 + 2 + 33,
874 .vrefresh = 60,
875 .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC,
876 };
877
878 static const struct panel_desc edt_etm0700g0dh6 = {
879 .modes = &edt_etm0700g0dh6_mode,
880 .num_modes = 1,
881 .bpc = 6,
882 .size = {
883 .width = 152,
884 .height = 91,
885 },
886 .bus_format = MEDIA_BUS_FMT_RGB666_1X18,
887 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_NEGEDGE,
888 };
889
890 static const struct drm_display_mode foxlink_fl500wvr00_a0t_mode = {
891 .clock = 32260,
892 .hdisplay = 800,
893 .hsync_start = 800 + 168,
894 .hsync_end = 800 + 168 + 64,
895 .htotal = 800 + 168 + 64 + 88,
896 .vdisplay = 480,
897 .vsync_start = 480 + 37,
898 .vsync_end = 480 + 37 + 2,
899 .vtotal = 480 + 37 + 2 + 8,
900 .vrefresh = 60,
901 };
902
903 static const struct panel_desc foxlink_fl500wvr00_a0t = {
904 .modes = &foxlink_fl500wvr00_a0t_mode,
905 .num_modes = 1,
906 .bpc = 8,
907 .size = {
908 .width = 108,
909 .height = 65,
910 },
911 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
912 };
913
914 static const struct drm_display_mode giantplus_gpg482739qs5_mode = {
915 .clock = 9000,
916 .hdisplay = 480,
917 .hsync_start = 480 + 5,
918 .hsync_end = 480 + 5 + 1,
919 .htotal = 480 + 5 + 1 + 40,
920 .vdisplay = 272,
921 .vsync_start = 272 + 8,
922 .vsync_end = 272 + 8 + 1,
923 .vtotal = 272 + 8 + 1 + 8,
924 .vrefresh = 60,
925 };
926
927 static const struct panel_desc giantplus_gpg482739qs5 = {
928 .modes = &giantplus_gpg482739qs5_mode,
929 .num_modes = 1,
930 .bpc = 8,
931 .size = {
932 .width = 95,
933 .height = 54,
934 },
935 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
936 };
937
938 static const struct display_timing hannstar_hsd070pww1_timing = {
939 .pixelclock = { 64300000, 71100000, 82000000 },
940 .hactive = { 1280, 1280, 1280 },
941 .hfront_porch = { 1, 1, 10 },
942 .hback_porch = { 1, 1, 10 },
943 /*
944 * According to the data sheet, the minimum horizontal blanking interval
945 * is 54 clocks (1 + 52 + 1), but tests with a Nitrogen6X have shown the
946 * minimum working horizontal blanking interval to be 60 clocks.
947 */
948 .hsync_len = { 58, 158, 661 },
949 .vactive = { 800, 800, 800 },
950 .vfront_porch = { 1, 1, 10 },
951 .vback_porch = { 1, 1, 10 },
952 .vsync_len = { 1, 21, 203 },
953 .flags = DISPLAY_FLAGS_DE_HIGH,
954 };
955
956 static const struct panel_desc hannstar_hsd070pww1 = {
957 .timings = &hannstar_hsd070pww1_timing,
958 .num_timings = 1,
959 .bpc = 6,
960 .size = {
961 .width = 151,
962 .height = 94,
963 },
964 .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG,
965 };
966
967 static const struct display_timing hannstar_hsd100pxn1_timing = {
968 .pixelclock = { 55000000, 65000000, 75000000 },
969 .hactive = { 1024, 1024, 1024 },
970 .hfront_porch = { 40, 40, 40 },
971 .hback_porch = { 220, 220, 220 },
972 .hsync_len = { 20, 60, 100 },
973 .vactive = { 768, 768, 768 },
974 .vfront_porch = { 7, 7, 7 },
975 .vback_porch = { 21, 21, 21 },
976 .vsync_len = { 10, 10, 10 },
977 .flags = DISPLAY_FLAGS_DE_HIGH,
978 };
979
980 static const struct panel_desc hannstar_hsd100pxn1 = {
981 .timings = &hannstar_hsd100pxn1_timing,
982 .num_timings = 1,
983 .bpc = 6,
984 .size = {
985 .width = 203,
986 .height = 152,
987 },
988 .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG,
989 };
990
991 static const struct drm_display_mode hitachi_tx23d38vm0caa_mode = {
992 .clock = 33333,
993 .hdisplay = 800,
994 .hsync_start = 800 + 85,
995 .hsync_end = 800 + 85 + 86,
996 .htotal = 800 + 85 + 86 + 85,
997 .vdisplay = 480,
998 .vsync_start = 480 + 16,
999 .vsync_end = 480 + 16 + 13,
1000 .vtotal = 480 + 16 + 13 + 16,
1001 .vrefresh = 60,
1002 };
1003
1004 static const struct panel_desc hitachi_tx23d38vm0caa = {
1005 .modes = &hitachi_tx23d38vm0caa_mode,
1006 .num_modes = 1,
1007 .bpc = 6,
1008 .size = {
1009 .width = 195,
1010 .height = 117,
1011 },
1012 };
1013
1014 static const struct drm_display_mode innolux_at043tn24_mode = {
1015 .clock = 9000,
1016 .hdisplay = 480,
1017 .hsync_start = 480 + 2,
1018 .hsync_end = 480 + 2 + 41,
1019 .htotal = 480 + 2 + 41 + 2,
1020 .vdisplay = 272,
1021 .vsync_start = 272 + 2,
1022 .vsync_end = 272 + 2 + 11,
1023 .vtotal = 272 + 2 + 11 + 2,
1024 .vrefresh = 60,
1025 .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC,
1026 };
1027
1028 static const struct panel_desc innolux_at043tn24 = {
1029 .modes = &innolux_at043tn24_mode,
1030 .num_modes = 1,
1031 .bpc = 8,
1032 .size = {
1033 .width = 95,
1034 .height = 54,
1035 },
1036 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
1037 };
1038
1039 static const struct drm_display_mode innolux_at070tn92_mode = {
1040 .clock = 33333,
1041 .hdisplay = 800,
1042 .hsync_start = 800 + 210,
1043 .hsync_end = 800 + 210 + 20,
1044 .htotal = 800 + 210 + 20 + 46,
1045 .vdisplay = 480,
1046 .vsync_start = 480 + 22,
1047 .vsync_end = 480 + 22 + 10,
1048 .vtotal = 480 + 22 + 23 + 10,
1049 .vrefresh = 60,
1050 };
1051
1052 static const struct panel_desc innolux_at070tn92 = {
1053 .modes = &innolux_at070tn92_mode,
1054 .num_modes = 1,
1055 .size = {
1056 .width = 154,
1057 .height = 86,
1058 },
1059 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
1060 };
1061
1062 static const struct display_timing innolux_g101ice_l01_timing = {
1063 .pixelclock = { 60400000, 71100000, 74700000 },
1064 .hactive = { 1280, 1280, 1280 },
1065 .hfront_porch = { 41, 80, 100 },
1066 .hback_porch = { 40, 79, 99 },
1067 .hsync_len = { 1, 1, 1 },
1068 .vactive = { 800, 800, 800 },
1069 .vfront_porch = { 5, 11, 14 },
1070 .vback_porch = { 4, 11, 14 },
1071 .vsync_len = { 1, 1, 1 },
1072 .flags = DISPLAY_FLAGS_DE_HIGH,
1073 };
1074
1075 static const struct panel_desc innolux_g101ice_l01 = {
1076 .timings = &innolux_g101ice_l01_timing,
1077 .num_timings = 1,
1078 .bpc = 8,
1079 .size = {
1080 .width = 217,
1081 .height = 135,
1082 },
1083 .delay = {
1084 .enable = 200,
1085 .disable = 200,
1086 },
1087 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
1088 };
1089
1090 static const struct display_timing innolux_g121i1_l01_timing = {
1091 .pixelclock = { 67450000, 71000000, 74550000 },
1092 .hactive = { 1280, 1280, 1280 },
1093 .hfront_porch = { 40, 80, 160 },
1094 .hback_porch = { 39, 79, 159 },
1095 .hsync_len = { 1, 1, 1 },
1096 .vactive = { 800, 800, 800 },
1097 .vfront_porch = { 5, 11, 100 },
1098 .vback_porch = { 4, 11, 99 },
1099 .vsync_len = { 1, 1, 1 },
1100 };
1101
1102 static const struct panel_desc innolux_g121i1_l01 = {
1103 .timings = &innolux_g121i1_l01_timing,
1104 .num_timings = 1,
1105 .bpc = 6,
1106 .size = {
1107 .width = 261,
1108 .height = 163,
1109 },
1110 .delay = {
1111 .enable = 200,
1112 .disable = 20,
1113 },
1114 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
1115 };
1116
1117 static const struct drm_display_mode innolux_g121x1_l03_mode = {
1118 .clock = 65000,
1119 .hdisplay = 1024,
1120 .hsync_start = 1024 + 0,
1121 .hsync_end = 1024 + 1,
1122 .htotal = 1024 + 0 + 1 + 320,
1123 .vdisplay = 768,
1124 .vsync_start = 768 + 38,
1125 .vsync_end = 768 + 38 + 1,
1126 .vtotal = 768 + 38 + 1 + 0,
1127 .vrefresh = 60,
1128 .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC,
1129 };
1130
1131 static const struct panel_desc innolux_g121x1_l03 = {
1132 .modes = &innolux_g121x1_l03_mode,
1133 .num_modes = 1,
1134 .bpc = 6,
1135 .size = {
1136 .width = 246,
1137 .height = 185,
1138 },
1139 .delay = {
1140 .enable = 200,
1141 .unprepare = 200,
1142 .disable = 400,
1143 },
1144 };
1145
1146 static const struct drm_display_mode innolux_n116bge_mode = {
1147 .clock = 76420,
1148 .hdisplay = 1366,
1149 .hsync_start = 1366 + 136,
1150 .hsync_end = 1366 + 136 + 30,
1151 .htotal = 1366 + 136 + 30 + 60,
1152 .vdisplay = 768,
1153 .vsync_start = 768 + 8,
1154 .vsync_end = 768 + 8 + 12,
1155 .vtotal = 768 + 8 + 12 + 12,
1156 .vrefresh = 60,
1157 .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC,
1158 };
1159
1160 static const struct panel_desc innolux_n116bge = {
1161 .modes = &innolux_n116bge_mode,
1162 .num_modes = 1,
1163 .bpc = 6,
1164 .size = {
1165 .width = 256,
1166 .height = 144,
1167 },
1168 };
1169
1170 static const struct drm_display_mode innolux_n156bge_l21_mode = {
1171 .clock = 69300,
1172 .hdisplay = 1366,
1173 .hsync_start = 1366 + 16,
1174 .hsync_end = 1366 + 16 + 34,
1175 .htotal = 1366 + 16 + 34 + 50,
1176 .vdisplay = 768,
1177 .vsync_start = 768 + 2,
1178 .vsync_end = 768 + 2 + 6,
1179 .vtotal = 768 + 2 + 6 + 12,
1180 .vrefresh = 60,
1181 };
1182
1183 static const struct panel_desc innolux_n156bge_l21 = {
1184 .modes = &innolux_n156bge_l21_mode,
1185 .num_modes = 1,
1186 .bpc = 6,
1187 .size = {
1188 .width = 344,
1189 .height = 193,
1190 },
1191 };
1192
1193 static const struct drm_display_mode innolux_zj070na_01p_mode = {
1194 .clock = 51501,
1195 .hdisplay = 1024,
1196 .hsync_start = 1024 + 128,
1197 .hsync_end = 1024 + 128 + 64,
1198 .htotal = 1024 + 128 + 64 + 128,
1199 .vdisplay = 600,
1200 .vsync_start = 600 + 16,
1201 .vsync_end = 600 + 16 + 4,
1202 .vtotal = 600 + 16 + 4 + 16,
1203 .vrefresh = 60,
1204 };
1205
1206 static const struct panel_desc innolux_zj070na_01p = {
1207 .modes = &innolux_zj070na_01p_mode,
1208 .num_modes = 1,
1209 .bpc = 6,
1210 .size = {
1211 .width = 154,
1212 .height = 90,
1213 },
1214 };
1215
1216 static const struct display_timing kyo_tcg121xglp_timing = {
1217 .pixelclock = { 52000000, 65000000, 71000000 },
1218 .hactive = { 1024, 1024, 1024 },
1219 .hfront_porch = { 2, 2, 2 },
1220 .hback_porch = { 2, 2, 2 },
1221 .hsync_len = { 86, 124, 244 },
1222 .vactive = { 768, 768, 768 },
1223 .vfront_porch = { 2, 2, 2 },
1224 .vback_porch = { 2, 2, 2 },
1225 .vsync_len = { 6, 34, 73 },
1226 .flags = DISPLAY_FLAGS_DE_HIGH,
1227 };
1228
1229 static const struct panel_desc kyo_tcg121xglp = {
1230 .timings = &kyo_tcg121xglp_timing,
1231 .num_timings = 1,
1232 .bpc = 8,
1233 .size = {
1234 .width = 246,
1235 .height = 184,
1236 },
1237 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
1238 };
1239
1240 static const struct drm_display_mode lg_lb070wv8_mode = {
1241 .clock = 33246,
1242 .hdisplay = 800,
1243 .hsync_start = 800 + 88,
1244 .hsync_end = 800 + 88 + 80,
1245 .htotal = 800 + 88 + 80 + 88,
1246 .vdisplay = 480,
1247 .vsync_start = 480 + 10,
1248 .vsync_end = 480 + 10 + 25,
1249 .vtotal = 480 + 10 + 25 + 10,
1250 .vrefresh = 60,
1251 };
1252
1253 static const struct panel_desc lg_lb070wv8 = {
1254 .modes = &lg_lb070wv8_mode,
1255 .num_modes = 1,
1256 .bpc = 16,
1257 .size = {
1258 .width = 151,
1259 .height = 91,
1260 },
1261 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
1262 };
1263
1264 static const struct drm_display_mode lg_lp079qx1_sp0v_mode = {
1265 .clock = 200000,
1266 .hdisplay = 1536,
1267 .hsync_start = 1536 + 12,
1268 .hsync_end = 1536 + 12 + 16,
1269 .htotal = 1536 + 12 + 16 + 48,
1270 .vdisplay = 2048,
1271 .vsync_start = 2048 + 8,
1272 .vsync_end = 2048 + 8 + 4,
1273 .vtotal = 2048 + 8 + 4 + 8,
1274 .vrefresh = 60,
1275 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC,
1276 };
1277
1278 static const struct panel_desc lg_lp079qx1_sp0v = {
1279 .modes = &lg_lp079qx1_sp0v_mode,
1280 .num_modes = 1,
1281 .size = {
1282 .width = 129,
1283 .height = 171,
1284 },
1285 };
1286
1287 static const struct drm_display_mode lg_lp097qx1_spa1_mode = {
1288 .clock = 205210,
1289 .hdisplay = 2048,
1290 .hsync_start = 2048 + 150,
1291 .hsync_end = 2048 + 150 + 5,
1292 .htotal = 2048 + 150 + 5 + 5,
1293 .vdisplay = 1536,
1294 .vsync_start = 1536 + 3,
1295 .vsync_end = 1536 + 3 + 1,
1296 .vtotal = 1536 + 3 + 1 + 9,
1297 .vrefresh = 60,
1298 };
1299
1300 static const struct panel_desc lg_lp097qx1_spa1 = {
1301 .modes = &lg_lp097qx1_spa1_mode,
1302 .num_modes = 1,
1303 .size = {
1304 .width = 208,
1305 .height = 147,
1306 },
1307 };
1308
1309 static const struct drm_display_mode lg_lp120up1_mode = {
1310 .clock = 162300,
1311 .hdisplay = 1920,
1312 .hsync_start = 1920 + 40,
1313 .hsync_end = 1920 + 40 + 40,
1314 .htotal = 1920 + 40 + 40+ 80,
1315 .vdisplay = 1280,
1316 .vsync_start = 1280 + 4,
1317 .vsync_end = 1280 + 4 + 4,
1318 .vtotal = 1280 + 4 + 4 + 12,
1319 .vrefresh = 60,
1320 };
1321
1322 static const struct panel_desc lg_lp120up1 = {
1323 .modes = &lg_lp120up1_mode,
1324 .num_modes = 1,
1325 .bpc = 8,
1326 .size = {
1327 .width = 267,
1328 .height = 183,
1329 },
1330 };
1331
1332 static const struct drm_display_mode lg_lp129qe_mode = {
1333 .clock = 285250,
1334 .hdisplay = 2560,
1335 .hsync_start = 2560 + 48,
1336 .hsync_end = 2560 + 48 + 32,
1337 .htotal = 2560 + 48 + 32 + 80,
1338 .vdisplay = 1700,
1339 .vsync_start = 1700 + 3,
1340 .vsync_end = 1700 + 3 + 10,
1341 .vtotal = 1700 + 3 + 10 + 36,
1342 .vrefresh = 60,
1343 };
1344
1345 static const struct panel_desc lg_lp129qe = {
1346 .modes = &lg_lp129qe_mode,
1347 .num_modes = 1,
1348 .bpc = 8,
1349 .size = {
1350 .width = 272,
1351 .height = 181,
1352 },
1353 };
1354
1355 static const struct display_timing nec_nl12880bc20_05_timing = {
1356 .pixelclock = { 67000000, 71000000, 75000000 },
1357 .hactive = { 1280, 1280, 1280 },
1358 .hfront_porch = { 2, 30, 30 },
1359 .hback_porch = { 6, 100, 100 },
1360 .hsync_len = { 2, 30, 30 },
1361 .vactive = { 800, 800, 800 },
1362 .vfront_porch = { 5, 5, 5 },
1363 .vback_porch = { 11, 11, 11 },
1364 .vsync_len = { 7, 7, 7 },
1365 };
1366
1367 static const struct panel_desc nec_nl12880bc20_05 = {
1368 .timings = &nec_nl12880bc20_05_timing,
1369 .num_timings = 1,
1370 .bpc = 8,
1371 .size = {
1372 .width = 261,
1373 .height = 163,
1374 },
1375 .delay = {
1376 .enable = 50,
1377 .disable = 50,
1378 },
1379 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
1380 };
1381
1382 static const struct drm_display_mode nec_nl4827hc19_05b_mode = {
1383 .clock = 10870,
1384 .hdisplay = 480,
1385 .hsync_start = 480 + 2,
1386 .hsync_end = 480 + 2 + 41,
1387 .htotal = 480 + 2 + 41 + 2,
1388 .vdisplay = 272,
1389 .vsync_start = 272 + 2,
1390 .vsync_end = 272 + 2 + 4,
1391 .vtotal = 272 + 2 + 4 + 2,
1392 .vrefresh = 74,
1393 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC,
1394 };
1395
1396 static const struct panel_desc nec_nl4827hc19_05b = {
1397 .modes = &nec_nl4827hc19_05b_mode,
1398 .num_modes = 1,
1399 .bpc = 8,
1400 .size = {
1401 .width = 95,
1402 .height = 54,
1403 },
1404 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
1405 .bus_flags = DRM_BUS_FLAG_PIXDATA_POSEDGE,
1406 };
1407
1408 static const struct drm_display_mode netron_dy_e231732_mode = {
1409 .clock = 66000,
1410 .hdisplay = 1024,
1411 .hsync_start = 1024 + 160,
1412 .hsync_end = 1024 + 160 + 70,
1413 .htotal = 1024 + 160 + 70 + 90,
1414 .vdisplay = 600,
1415 .vsync_start = 600 + 127,
1416 .vsync_end = 600 + 127 + 20,
1417 .vtotal = 600 + 127 + 20 + 3,
1418 .vrefresh = 60,
1419 };
1420
1421 static const struct panel_desc netron_dy_e231732 = {
1422 .modes = &netron_dy_e231732_mode,
1423 .num_modes = 1,
1424 .size = {
1425 .width = 154,
1426 .height = 87,
1427 },
1428 .bus_format = MEDIA_BUS_FMT_RGB666_1X18,
1429 };
1430
1431 static const struct display_timing nlt_nl192108ac18_02d_timing = {
1432 .pixelclock = { 130000000, 148350000, 163000000 },
1433 .hactive = { 1920, 1920, 1920 },
1434 .hfront_porch = { 80, 100, 100 },
1435 .hback_porch = { 100, 120, 120 },
1436 .hsync_len = { 50, 60, 60 },
1437 .vactive = { 1080, 1080, 1080 },
1438 .vfront_porch = { 12, 30, 30 },
1439 .vback_porch = { 4, 10, 10 },
1440 .vsync_len = { 4, 5, 5 },
1441 };
1442
1443 static const struct panel_desc nlt_nl192108ac18_02d = {
1444 .timings = &nlt_nl192108ac18_02d_timing,
1445 .num_timings = 1,
1446 .bpc = 8,
1447 .size = {
1448 .width = 344,
1449 .height = 194,
1450 },
1451 .delay = {
1452 .unprepare = 500,
1453 },
1454 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
1455 };
1456
1457 static const struct drm_display_mode nvd_9128_mode = {
1458 .clock = 29500,
1459 .hdisplay = 800,
1460 .hsync_start = 800 + 130,
1461 .hsync_end = 800 + 130 + 98,
1462 .htotal = 800 + 0 + 130 + 98,
1463 .vdisplay = 480,
1464 .vsync_start = 480 + 10,
1465 .vsync_end = 480 + 10 + 50,
1466 .vtotal = 480 + 0 + 10 + 50,
1467 };
1468
1469 static const struct panel_desc nvd_9128 = {
1470 .modes = &nvd_9128_mode,
1471 .num_modes = 1,
1472 .bpc = 8,
1473 .size = {
1474 .width = 156,
1475 .height = 88,
1476 },
1477 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
1478 };
1479
1480 static const struct display_timing okaya_rs800480t_7x0gp_timing = {
1481 .pixelclock = { 30000000, 30000000, 40000000 },
1482 .hactive = { 800, 800, 800 },
1483 .hfront_porch = { 40, 40, 40 },
1484 .hback_porch = { 40, 40, 40 },
1485 .hsync_len = { 1, 48, 48 },
1486 .vactive = { 480, 480, 480 },
1487 .vfront_porch = { 13, 13, 13 },
1488 .vback_porch = { 29, 29, 29 },
1489 .vsync_len = { 3, 3, 3 },
1490 .flags = DISPLAY_FLAGS_DE_HIGH,
1491 };
1492
1493 static const struct panel_desc okaya_rs800480t_7x0gp = {
1494 .timings = &okaya_rs800480t_7x0gp_timing,
1495 .num_timings = 1,
1496 .bpc = 6,
1497 .size = {
1498 .width = 154,
1499 .height = 87,
1500 },
1501 .delay = {
1502 .prepare = 41,
1503 .enable = 50,
1504 .unprepare = 41,
1505 .disable = 50,
1506 },
1507 .bus_format = MEDIA_BUS_FMT_RGB666_1X18,
1508 };
1509
1510 static const struct drm_display_mode olimex_lcd_olinuxino_43ts_mode = {
1511 .clock = 9000,
1512 .hdisplay = 480,
1513 .hsync_start = 480 + 5,
1514 .hsync_end = 480 + 5 + 30,
1515 .htotal = 480 + 5 + 30 + 10,
1516 .vdisplay = 272,
1517 .vsync_start = 272 + 8,
1518 .vsync_end = 272 + 8 + 5,
1519 .vtotal = 272 + 8 + 5 + 3,
1520 .vrefresh = 60,
1521 };
1522
1523 static const struct panel_desc olimex_lcd_olinuxino_43ts = {
1524 .modes = &olimex_lcd_olinuxino_43ts_mode,
1525 .num_modes = 1,
1526 .size = {
1527 .width = 105,
1528 .height = 67,
1529 },
1530 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
1531 };
1532
1533 /*
1534 * 800x480 CVT. The panel appears to be quite accepting, at least as far as
1535 * pixel clocks, but this is the timing that was being used in the Adafruit
1536 * installation instructions.
1537 */
1538 static const struct drm_display_mode ontat_yx700wv03_mode = {
1539 .clock = 29500,
1540 .hdisplay = 800,
1541 .hsync_start = 824,
1542 .hsync_end = 896,
1543 .htotal = 992,
1544 .vdisplay = 480,
1545 .vsync_start = 483,
1546 .vsync_end = 493,
1547 .vtotal = 500,
1548 .vrefresh = 60,
1549 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC,
1550 };
1551
1552 /*
1553 * Specification at:
1554 * https://www.adafruit.com/images/product-files/2406/c3163.pdf
1555 */
1556 static const struct panel_desc ontat_yx700wv03 = {
1557 .modes = &ontat_yx700wv03_mode,
1558 .num_modes = 1,
1559 .bpc = 8,
1560 .size = {
1561 .width = 154,
1562 .height = 83,
1563 },
1564 .bus_format = MEDIA_BUS_FMT_RGB666_1X18,
1565 };
1566
1567 static const struct drm_display_mode ortustech_com43h4m85ulc_mode = {
1568 .clock = 25000,
1569 .hdisplay = 480,
1570 .hsync_start = 480 + 10,
1571 .hsync_end = 480 + 10 + 10,
1572 .htotal = 480 + 10 + 10 + 15,
1573 .vdisplay = 800,
1574 .vsync_start = 800 + 3,
1575 .vsync_end = 800 + 3 + 3,
1576 .vtotal = 800 + 3 + 3 + 3,
1577 .vrefresh = 60,
1578 };
1579
1580 static const struct panel_desc ortustech_com43h4m85ulc = {
1581 .modes = &ortustech_com43h4m85ulc_mode,
1582 .num_modes = 1,
1583 .bpc = 8,
1584 .size = {
1585 .width = 56,
1586 .height = 93,
1587 },
1588 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
1589 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_POSEDGE,
1590 };
1591
1592 static const struct drm_display_mode qd43003c0_40_mode = {
1593 .clock = 9000,
1594 .hdisplay = 480,
1595 .hsync_start = 480 + 8,
1596 .hsync_end = 480 + 8 + 4,
1597 .htotal = 480 + 8 + 4 + 39,
1598 .vdisplay = 272,
1599 .vsync_start = 272 + 4,
1600 .vsync_end = 272 + 4 + 10,
1601 .vtotal = 272 + 4 + 10 + 2,
1602 .vrefresh = 60,
1603 };
1604
1605 static const struct panel_desc qd43003c0_40 = {
1606 .modes = &qd43003c0_40_mode,
1607 .num_modes = 1,
1608 .bpc = 8,
1609 .size = {
1610 .width = 95,
1611 .height = 53,
1612 },
1613 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
1614 };
1615
1616 static const struct drm_display_mode samsung_lsn122dl01_c01_mode = {
1617 .clock = 271560,
1618 .hdisplay = 2560,
1619 .hsync_start = 2560 + 48,
1620 .hsync_end = 2560 + 48 + 32,
1621 .htotal = 2560 + 48 + 32 + 80,
1622 .vdisplay = 1600,
1623 .vsync_start = 1600 + 2,
1624 .vsync_end = 1600 + 2 + 5,
1625 .vtotal = 1600 + 2 + 5 + 57,
1626 .vrefresh = 60,
1627 };
1628
1629 static const struct panel_desc samsung_lsn122dl01_c01 = {
1630 .modes = &samsung_lsn122dl01_c01_mode,
1631 .num_modes = 1,
1632 .size = {
1633 .width = 263,
1634 .height = 164,
1635 },
1636 };
1637
1638 static const struct drm_display_mode samsung_ltn101nt05_mode = {
1639 .clock = 54030,
1640 .hdisplay = 1024,
1641 .hsync_start = 1024 + 24,
1642 .hsync_end = 1024 + 24 + 136,
1643 .htotal = 1024 + 24 + 136 + 160,
1644 .vdisplay = 600,
1645 .vsync_start = 600 + 3,
1646 .vsync_end = 600 + 3 + 6,
1647 .vtotal = 600 + 3 + 6 + 61,
1648 .vrefresh = 60,
1649 };
1650
1651 static const struct panel_desc samsung_ltn101nt05 = {
1652 .modes = &samsung_ltn101nt05_mode,
1653 .num_modes = 1,
1654 .bpc = 6,
1655 .size = {
1656 .width = 223,
1657 .height = 125,
1658 },
1659 };
1660
1661 static const struct drm_display_mode samsung_ltn140at29_301_mode = {
1662 .clock = 76300,
1663 .hdisplay = 1366,
1664 .hsync_start = 1366 + 64,
1665 .hsync_end = 1366 + 64 + 48,
1666 .htotal = 1366 + 64 + 48 + 128,
1667 .vdisplay = 768,
1668 .vsync_start = 768 + 2,
1669 .vsync_end = 768 + 2 + 5,
1670 .vtotal = 768 + 2 + 5 + 17,
1671 .vrefresh = 60,
1672 };
1673
1674 static const struct panel_desc samsung_ltn140at29_301 = {
1675 .modes = &samsung_ltn140at29_301_mode,
1676 .num_modes = 1,
1677 .bpc = 6,
1678 .size = {
1679 .width = 320,
1680 .height = 187,
1681 },
1682 };
1683
1684 static const struct display_timing sharp_lq101k1ly04_timing = {
1685 .pixelclock = { 60000000, 65000000, 80000000 },
1686 .hactive = { 1280, 1280, 1280 },
1687 .hfront_porch = { 20, 20, 20 },
1688 .hback_porch = { 20, 20, 20 },
1689 .hsync_len = { 10, 10, 10 },
1690 .vactive = { 800, 800, 800 },
1691 .vfront_porch = { 4, 4, 4 },
1692 .vback_porch = { 4, 4, 4 },
1693 .vsync_len = { 4, 4, 4 },
1694 .flags = DISPLAY_FLAGS_PIXDATA_POSEDGE,
1695 };
1696
1697 static const struct panel_desc sharp_lq101k1ly04 = {
1698 .timings = &sharp_lq101k1ly04_timing,
1699 .num_timings = 1,
1700 .bpc = 8,
1701 .size = {
1702 .width = 217,
1703 .height = 136,
1704 },
1705 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_JEIDA,
1706 };
1707
1708 static const struct drm_display_mode sharp_lq123p1jx31_mode = {
1709 .clock = 252750,
1710 .hdisplay = 2400,
1711 .hsync_start = 2400 + 48,
1712 .hsync_end = 2400 + 48 + 32,
1713 .htotal = 2400 + 48 + 32 + 80,
1714 .vdisplay = 1600,
1715 .vsync_start = 1600 + 3,
1716 .vsync_end = 1600 + 3 + 10,
1717 .vtotal = 1600 + 3 + 10 + 33,
1718 .vrefresh = 60,
1719 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC,
1720 };
1721
1722 static const struct panel_desc sharp_lq123p1jx31 = {
1723 .modes = &sharp_lq123p1jx31_mode,
1724 .num_modes = 1,
1725 .bpc = 8,
1726 .size = {
1727 .width = 259,
1728 .height = 173,
1729 },
1730 .delay = {
1731 .prepare = 110,
1732 .enable = 50,
1733 .unprepare = 550,
1734 },
1735 };
1736
1737 static const struct drm_display_mode sharp_lq150x1lg11_mode = {
1738 .clock = 71100,
1739 .hdisplay = 1024,
1740 .hsync_start = 1024 + 168,
1741 .hsync_end = 1024 + 168 + 64,
1742 .htotal = 1024 + 168 + 64 + 88,
1743 .vdisplay = 768,
1744 .vsync_start = 768 + 37,
1745 .vsync_end = 768 + 37 + 2,
1746 .vtotal = 768 + 37 + 2 + 8,
1747 .vrefresh = 60,
1748 };
1749
1750 static const struct panel_desc sharp_lq150x1lg11 = {
1751 .modes = &sharp_lq150x1lg11_mode,
1752 .num_modes = 1,
1753 .bpc = 6,
1754 .size = {
1755 .width = 304,
1756 .height = 228,
1757 },
1758 .bus_format = MEDIA_BUS_FMT_RGB565_1X16,
1759 };
1760
1761 static const struct drm_display_mode shelly_sca07010_bfn_lnn_mode = {
1762 .clock = 33300,
1763 .hdisplay = 800,
1764 .hsync_start = 800 + 1,
1765 .hsync_end = 800 + 1 + 64,
1766 .htotal = 800 + 1 + 64 + 64,
1767 .vdisplay = 480,
1768 .vsync_start = 480 + 1,
1769 .vsync_end = 480 + 1 + 23,
1770 .vtotal = 480 + 1 + 23 + 22,
1771 .vrefresh = 60,
1772 };
1773
1774 static const struct panel_desc shelly_sca07010_bfn_lnn = {
1775 .modes = &shelly_sca07010_bfn_lnn_mode,
1776 .num_modes = 1,
1777 .size = {
1778 .width = 152,
1779 .height = 91,
1780 },
1781 .bus_format = MEDIA_BUS_FMT_RGB666_1X18,
1782 };
1783
1784 static const struct drm_display_mode starry_kr122ea0sra_mode = {
1785 .clock = 147000,
1786 .hdisplay = 1920,
1787 .hsync_start = 1920 + 16,
1788 .hsync_end = 1920 + 16 + 16,
1789 .htotal = 1920 + 16 + 16 + 32,
1790 .vdisplay = 1200,
1791 .vsync_start = 1200 + 15,
1792 .vsync_end = 1200 + 15 + 2,
1793 .vtotal = 1200 + 15 + 2 + 18,
1794 .vrefresh = 60,
1795 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC,
1796 };
1797
1798 static const struct panel_desc starry_kr122ea0sra = {
1799 .modes = &starry_kr122ea0sra_mode,
1800 .num_modes = 1,
1801 .size = {
1802 .width = 263,
1803 .height = 164,
1804 },
1805 .delay = {
1806 .prepare = 10 + 200,
1807 .enable = 50,
1808 .unprepare = 10 + 500,
1809 },
1810 };
1811
1812 static const struct display_timing tianma_tm070jdhg30_timing = {
1813 .pixelclock = { 62600000, 68200000, 78100000 },
1814 .hactive = { 1280, 1280, 1280 },
1815 .hfront_porch = { 15, 64, 159 },
1816 .hback_porch = { 5, 5, 5 },
1817 .hsync_len = { 1, 1, 256 },
1818 .vactive = { 800, 800, 800 },
1819 .vfront_porch = { 3, 40, 99 },
1820 .vback_porch = { 2, 2, 2 },
1821 .vsync_len = { 1, 1, 128 },
1822 .flags = DISPLAY_FLAGS_DE_HIGH,
1823 };
1824
1825 static const struct panel_desc tianma_tm070jdhg30 = {
1826 .timings = &tianma_tm070jdhg30_timing,
1827 .num_timings = 1,
1828 .bpc = 8,
1829 .size = {
1830 .width = 151,
1831 .height = 95,
1832 },
1833 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
1834 };
1835
1836 static const struct drm_display_mode tpk_f07a_0102_mode = {
1837 .clock = 33260,
1838 .hdisplay = 800,
1839 .hsync_start = 800 + 40,
1840 .hsync_end = 800 + 40 + 128,
1841 .htotal = 800 + 40 + 128 + 88,
1842 .vdisplay = 480,
1843 .vsync_start = 480 + 10,
1844 .vsync_end = 480 + 10 + 2,
1845 .vtotal = 480 + 10 + 2 + 33,
1846 .vrefresh = 60,
1847 };
1848
1849 static const struct panel_desc tpk_f07a_0102 = {
1850 .modes = &tpk_f07a_0102_mode,
1851 .num_modes = 1,
1852 .size = {
1853 .width = 152,
1854 .height = 91,
1855 },
1856 .bus_flags = DRM_BUS_FLAG_PIXDATA_POSEDGE,
1857 };
1858
1859 static const struct drm_display_mode tpk_f10a_0102_mode = {
1860 .clock = 45000,
1861 .hdisplay = 1024,
1862 .hsync_start = 1024 + 176,
1863 .hsync_end = 1024 + 176 + 5,
1864 .htotal = 1024 + 176 + 5 + 88,
1865 .vdisplay = 600,
1866 .vsync_start = 600 + 20,
1867 .vsync_end = 600 + 20 + 5,
1868 .vtotal = 600 + 20 + 5 + 25,
1869 .vrefresh = 60,
1870 };
1871
1872 static const struct panel_desc tpk_f10a_0102 = {
1873 .modes = &tpk_f10a_0102_mode,
1874 .num_modes = 1,
1875 .size = {
1876 .width = 223,
1877 .height = 125,
1878 },
1879 };
1880
1881 static const struct display_timing urt_umsh_8596md_timing = {
1882 .pixelclock = { 33260000, 33260000, 33260000 },
1883 .hactive = { 800, 800, 800 },
1884 .hfront_porch = { 41, 41, 41 },
1885 .hback_porch = { 216 - 128, 216 - 128, 216 - 128 },
1886 .hsync_len = { 71, 128, 128 },
1887 .vactive = { 480, 480, 480 },
1888 .vfront_porch = { 10, 10, 10 },
1889 .vback_porch = { 35 - 2, 35 - 2, 35 - 2 },
1890 .vsync_len = { 2, 2, 2 },
1891 .flags = DISPLAY_FLAGS_DE_HIGH | DISPLAY_FLAGS_PIXDATA_NEGEDGE |
1892 DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_LOW,
1893 };
1894
1895 static const struct panel_desc urt_umsh_8596md_lvds = {
1896 .timings = &urt_umsh_8596md_timing,
1897 .num_timings = 1,
1898 .bpc = 6,
1899 .size = {
1900 .width = 152,
1901 .height = 91,
1902 },
1903 .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG,
1904 };
1905
1906 static const struct panel_desc urt_umsh_8596md_parallel = {
1907 .timings = &urt_umsh_8596md_timing,
1908 .num_timings = 1,
1909 .bpc = 6,
1910 .size = {
1911 .width = 152,
1912 .height = 91,
1913 },
1914 .bus_format = MEDIA_BUS_FMT_RGB666_1X18,
1915 };
1916
1917 static const struct drm_display_mode winstar_wf35ltiacd_mode = {
1918 .clock = 6410,
1919 .hdisplay = 320,
1920 .hsync_start = 320 + 20,
1921 .hsync_end = 320 + 20 + 30,
1922 .htotal = 320 + 20 + 30 + 38,
1923 .vdisplay = 240,
1924 .vsync_start = 240 + 4,
1925 .vsync_end = 240 + 4 + 3,
1926 .vtotal = 240 + 4 + 3 + 15,
1927 .vrefresh = 60,
1928 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC,
1929 };
1930
1931 static const struct panel_desc winstar_wf35ltiacd = {
1932 .modes = &winstar_wf35ltiacd_mode,
1933 .num_modes = 1,
1934 .bpc = 8,
1935 .size = {
1936 .width = 70,
1937 .height = 53,
1938 },
1939 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
1940 };
1941
1942 static const struct of_device_id platform_of_match[] = {
1943 {
1944 .compatible = "ampire,am-480272h3tmqw-t01h",
1945 .data = &ire_am_480272h3tmqw_t01h,
1946 }, {
1947 .compatible = "ampire,am800480r3tmqwa1h",
1948 .data = &ire_am800480r3tmqwa1h,
1949 }, {
1950 .compatible = "auo,b101aw03",
1951 .data = &auo_b101aw03,
1952 }, {
1953 .compatible = "auo,b101ean01",
1954 .data = &auo_b101ean01,
1955 }, {
1956 .compatible = "auo,b101xtn01",
1957 .data = &auo_b101xtn01,
1958 }, {
1959 .compatible = "auo,b116xw03",
1960 .data = &auo_b116xw03,
1961 }, {
1962 .compatible = "auo,b133htn01",
1963 .data = &auo_b133htn01,
1964 }, {
1965 .compatible = "auo,b133xtn01",
1966 .data = &auo_b133xtn01,
1967 }, {
1968 .compatible = "auo,g133han01",
1969 .data = &auo_g133han01,
1970 }, {
1971 .compatible = "auo,g185han01",
1972 .data = &auo_g185han01,
1973 }, {
1974 .compatible = "auo,p320hvn03",
1975 .data = &auo_p320hvn03,
1976 }, {
1977 .compatible = "auo,t215hvn01",
1978 .data = &auo_t215hvn01,
1979 }, {
1980 .compatible = "avic,tm070ddh03",
1981 .data = &avic_tm070ddh03,
1982 }, {
1983 .compatible = "boe,nv101wxmn51",
1984 .data = &boe_nv101wxmn51,
1985 }, {
1986 .compatible = "chunghwa,claa070wp03xg",
1987 .data = &chunghwa_claa070wp03xg,
1988 }, {
1989 .compatible = "chunghwa,claa101wa01a",
1990 .data = &chunghwa_claa101wa01a
1991 }, {
1992 .compatible = "chunghwa,claa101wb01",
1993 .data = &chunghwa_claa101wb01
1994 }, {
1995 .compatible = "edt,et057090dhu",
1996 .data = &edt_et057090dhu,
1997 }, {
1998 .compatible = "edt,et070080dh6",
1999 .data = &edt_etm0700g0dh6,
2000 }, {
2001 .compatible = "edt,etm0700g0dh6",
2002 .data = &edt_etm0700g0dh6,
2003 }, {
2004 .compatible = "foxlink,fl500wvr00-a0t",
2005 .data = &foxlink_fl500wvr00_a0t,
2006 }, {
2007 .compatible = "giantplus,gpg482739qs5",
2008 .data = &giantplus_gpg482739qs5
2009 }, {
2010 .compatible = "hannstar,hsd070pww1",
2011 .data = &hannstar_hsd070pww1,
2012 }, {
2013 .compatible = "hannstar,hsd100pxn1",
2014 .data = &hannstar_hsd100pxn1,
2015 }, {
2016 .compatible = "hit,tx23d38vm0caa",
2017 .data = &hitachi_tx23d38vm0caa
2018 }, {
2019 .compatible = "innolux,at043tn24",
2020 .data = &innolux_at043tn24,
2021 }, {
2022 .compatible = "innolux,at070tn92",
2023 .data = &innolux_at070tn92,
2024 }, {
2025 .compatible ="innolux,g101ice-l01",
2026 .data = &innolux_g101ice_l01
2027 }, {
2028 .compatible ="innolux,g121i1-l01",
2029 .data = &innolux_g121i1_l01
2030 }, {
2031 .compatible = "innolux,g121x1-l03",
2032 .data = &innolux_g121x1_l03,
2033 }, {
2034 .compatible = "innolux,n116bge",
2035 .data = &innolux_n116bge,
2036 }, {
2037 .compatible = "innolux,n156bge-l21",
2038 .data = &innolux_n156bge_l21,
2039 }, {
2040 .compatible = "innolux,zj070na-01p",
2041 .data = &innolux_zj070na_01p,
2042 }, {
2043 .compatible = "kyo,tcg121xglp",
2044 .data = &kyo_tcg121xglp,
2045 }, {
2046 .compatible = "lg,lb070wv8",
2047 .data = &lg_lb070wv8,
2048 }, {
2049 .compatible = "lg,lp079qx1-sp0v",
2050 .data = &lg_lp079qx1_sp0v,
2051 }, {
2052 .compatible = "lg,lp097qx1-spa1",
2053 .data = &lg_lp097qx1_spa1,
2054 }, {
2055 .compatible = "lg,lp120up1",
2056 .data = &lg_lp120up1,
2057 }, {
2058 .compatible = "lg,lp129qe",
2059 .data = &lg_lp129qe,
2060 }, {
2061 .compatible = "nec,nl12880bc20-05",
2062 .data = &nec_nl12880bc20_05,
2063 }, {
2064 .compatible = "nec,nl4827hc19-05b",
2065 .data = &nec_nl4827hc19_05b,
2066 }, {
2067 .compatible = "netron-dy,e231732",
2068 .data = &netron_dy_e231732,
2069 }, {
2070 .compatible = "nlt,nl192108ac18-02d",
2071 .data = &nlt_nl192108ac18_02d,
2072 }, {
2073 .compatible = "nvd,9128",
2074 .data = &nvd_9128,
2075 }, {
2076 .compatible = "okaya,rs800480t-7x0gp",
2077 .data = &okaya_rs800480t_7x0gp,
2078 }, {
2079 .compatible = "olimex,lcd-olinuxino-43-ts",
2080 .data = &olimex_lcd_olinuxino_43ts,
2081 }, {
2082 .compatible = "ontat,yx700wv03",
2083 .data = &ontat_yx700wv03,
2084 }, {
2085 .compatible = "ortustech,com43h4m85ulc",
2086 .data = &ortustech_com43h4m85ulc,
2087 }, {
2088 .compatible = "qiaodian,qd43003c0-40",
2089 .data = &qd43003c0_40,
2090 }, {
2091 .compatible = "samsung,lsn122dl01-c01",
2092 .data = &samsung_lsn122dl01_c01,
2093 }, {
2094 .compatible = "samsung,ltn101nt05",
2095 .data = &samsung_ltn101nt05,
2096 }, {
2097 .compatible = "samsung,ltn140at29-301",
2098 .data = &samsung_ltn140at29_301,
2099 }, {
2100 .compatible = "sharp,lq101k1ly04",
2101 .data = &sharp_lq101k1ly04,
2102 }, {
2103 .compatible = "sharp,lq123p1jx31",
2104 .data = &sharp_lq123p1jx31,
2105 }, {
2106 .compatible = "sharp,lq150x1lg11",
2107 .data = &sharp_lq150x1lg11,
2108 }, {
2109 .compatible = "shelly,sca07010-bfn-lnn",
2110 .data = &shelly_sca07010_bfn_lnn,
2111 }, {
2112 .compatible = "starry,kr122ea0sra",
2113 .data = &starry_kr122ea0sra,
2114 }, {
2115 .compatible = "tianma,tm070jdhg30",
2116 .data = &tianma_tm070jdhg30,
2117 }, {
2118 .compatible = "tpk,f07a-0102",
2119 .data = &tpk_f07a_0102,
2120 }, {
2121 .compatible = "tpk,f10a-0102",
2122 .data = &tpk_f10a_0102,
2123 }, {
2124 .compatible = "urt,umsh-8596md-t",
2125 .data = &urt_umsh_8596md_parallel,
2126 }, {
2127 .compatible = "urt,umsh-8596md-1t",
2128 .data = &urt_umsh_8596md_parallel,
2129 }, {
2130 .compatible = "urt,umsh-8596md-7t",
2131 .data = &urt_umsh_8596md_parallel,
2132 }, {
2133 .compatible = "urt,umsh-8596md-11t",
2134 .data = &urt_umsh_8596md_lvds,
2135 }, {
2136 .compatible = "urt,umsh-8596md-19t",
2137 .data = &urt_umsh_8596md_lvds,
2138 }, {
2139 .compatible = "urt,umsh-8596md-20t",
2140 .data = &urt_umsh_8596md_parallel,
2141 }, {
2142 .compatible = "winstar,wf35ltiacd",
2143 .data = &winstar_wf35ltiacd,
2144 }, {
2145 /* sentinel */
2146 }
2147 };
2148 MODULE_DEVICE_TABLE(of, platform_of_match);
2149
panel_simple_platform_probe(struct platform_device * pdev)2150 static int panel_simple_platform_probe(struct platform_device *pdev)
2151 {
2152 const struct of_device_id *id;
2153
2154 id = of_match_node(platform_of_match, pdev->dev.of_node);
2155 if (!id)
2156 return -ENODEV;
2157
2158 return panel_simple_probe(&pdev->dev, id->data);
2159 }
2160
panel_simple_platform_remove(struct platform_device * pdev)2161 static int panel_simple_platform_remove(struct platform_device *pdev)
2162 {
2163 return panel_simple_remove(&pdev->dev);
2164 }
2165
panel_simple_platform_shutdown(struct platform_device * pdev)2166 static void panel_simple_platform_shutdown(struct platform_device *pdev)
2167 {
2168 panel_simple_shutdown(&pdev->dev);
2169 }
2170
2171 static struct platform_driver panel_simple_platform_driver = {
2172 .driver = {
2173 .name = "panel-simple",
2174 .of_match_table = platform_of_match,
2175 },
2176 .probe = panel_simple_platform_probe,
2177 .remove = panel_simple_platform_remove,
2178 .shutdown = panel_simple_platform_shutdown,
2179 };
2180
2181 struct panel_desc_dsi {
2182 struct panel_desc desc;
2183
2184 unsigned long flags;
2185 enum mipi_dsi_pixel_format format;
2186 unsigned int lanes;
2187 };
2188
2189 static const struct drm_display_mode auo_b080uan01_mode = {
2190 .clock = 154500,
2191 .hdisplay = 1200,
2192 .hsync_start = 1200 + 62,
2193 .hsync_end = 1200 + 62 + 4,
2194 .htotal = 1200 + 62 + 4 + 62,
2195 .vdisplay = 1920,
2196 .vsync_start = 1920 + 9,
2197 .vsync_end = 1920 + 9 + 2,
2198 .vtotal = 1920 + 9 + 2 + 8,
2199 .vrefresh = 60,
2200 };
2201
2202 static const struct panel_desc_dsi auo_b080uan01 = {
2203 .desc = {
2204 .modes = &auo_b080uan01_mode,
2205 .num_modes = 1,
2206 .bpc = 8,
2207 .size = {
2208 .width = 108,
2209 .height = 272,
2210 },
2211 },
2212 .flags = MIPI_DSI_MODE_VIDEO | MIPI_DSI_CLOCK_NON_CONTINUOUS,
2213 .format = MIPI_DSI_FMT_RGB888,
2214 .lanes = 4,
2215 };
2216
2217 static const struct drm_display_mode boe_tv080wum_nl0_mode = {
2218 .clock = 160000,
2219 .hdisplay = 1200,
2220 .hsync_start = 1200 + 120,
2221 .hsync_end = 1200 + 120 + 20,
2222 .htotal = 1200 + 120 + 20 + 21,
2223 .vdisplay = 1920,
2224 .vsync_start = 1920 + 21,
2225 .vsync_end = 1920 + 21 + 3,
2226 .vtotal = 1920 + 21 + 3 + 18,
2227 .vrefresh = 60,
2228 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC,
2229 };
2230
2231 static const struct panel_desc_dsi boe_tv080wum_nl0 = {
2232 .desc = {
2233 .modes = &boe_tv080wum_nl0_mode,
2234 .num_modes = 1,
2235 .size = {
2236 .width = 107,
2237 .height = 172,
2238 },
2239 },
2240 .flags = MIPI_DSI_MODE_VIDEO |
2241 MIPI_DSI_MODE_VIDEO_BURST |
2242 MIPI_DSI_MODE_VIDEO_SYNC_PULSE,
2243 .format = MIPI_DSI_FMT_RGB888,
2244 .lanes = 4,
2245 };
2246
2247 static const struct drm_display_mode lg_ld070wx3_sl01_mode = {
2248 .clock = 71000,
2249 .hdisplay = 800,
2250 .hsync_start = 800 + 32,
2251 .hsync_end = 800 + 32 + 1,
2252 .htotal = 800 + 32 + 1 + 57,
2253 .vdisplay = 1280,
2254 .vsync_start = 1280 + 28,
2255 .vsync_end = 1280 + 28 + 1,
2256 .vtotal = 1280 + 28 + 1 + 14,
2257 .vrefresh = 60,
2258 };
2259
2260 static const struct panel_desc_dsi lg_ld070wx3_sl01 = {
2261 .desc = {
2262 .modes = &lg_ld070wx3_sl01_mode,
2263 .num_modes = 1,
2264 .bpc = 8,
2265 .size = {
2266 .width = 94,
2267 .height = 151,
2268 },
2269 },
2270 .flags = MIPI_DSI_MODE_VIDEO | MIPI_DSI_CLOCK_NON_CONTINUOUS,
2271 .format = MIPI_DSI_FMT_RGB888,
2272 .lanes = 4,
2273 };
2274
2275 static const struct drm_display_mode lg_lh500wx1_sd03_mode = {
2276 .clock = 67000,
2277 .hdisplay = 720,
2278 .hsync_start = 720 + 12,
2279 .hsync_end = 720 + 12 + 4,
2280 .htotal = 720 + 12 + 4 + 112,
2281 .vdisplay = 1280,
2282 .vsync_start = 1280 + 8,
2283 .vsync_end = 1280 + 8 + 4,
2284 .vtotal = 1280 + 8 + 4 + 12,
2285 .vrefresh = 60,
2286 };
2287
2288 static const struct panel_desc_dsi lg_lh500wx1_sd03 = {
2289 .desc = {
2290 .modes = &lg_lh500wx1_sd03_mode,
2291 .num_modes = 1,
2292 .bpc = 8,
2293 .size = {
2294 .width = 62,
2295 .height = 110,
2296 },
2297 },
2298 .flags = MIPI_DSI_MODE_VIDEO,
2299 .format = MIPI_DSI_FMT_RGB888,
2300 .lanes = 4,
2301 };
2302
2303 static const struct drm_display_mode panasonic_vvx10f004b00_mode = {
2304 .clock = 157200,
2305 .hdisplay = 1920,
2306 .hsync_start = 1920 + 154,
2307 .hsync_end = 1920 + 154 + 16,
2308 .htotal = 1920 + 154 + 16 + 32,
2309 .vdisplay = 1200,
2310 .vsync_start = 1200 + 17,
2311 .vsync_end = 1200 + 17 + 2,
2312 .vtotal = 1200 + 17 + 2 + 16,
2313 .vrefresh = 60,
2314 };
2315
2316 static const struct panel_desc_dsi panasonic_vvx10f004b00 = {
2317 .desc = {
2318 .modes = &panasonic_vvx10f004b00_mode,
2319 .num_modes = 1,
2320 .bpc = 8,
2321 .size = {
2322 .width = 217,
2323 .height = 136,
2324 },
2325 },
2326 .flags = MIPI_DSI_MODE_VIDEO | MIPI_DSI_MODE_VIDEO_SYNC_PULSE |
2327 MIPI_DSI_CLOCK_NON_CONTINUOUS,
2328 .format = MIPI_DSI_FMT_RGB888,
2329 .lanes = 4,
2330 };
2331
2332 static const struct of_device_id dsi_of_match[] = {
2333 {
2334 .compatible = "auo,b080uan01",
2335 .data = &auo_b080uan01
2336 }, {
2337 .compatible = "boe,tv080wum-nl0",
2338 .data = &boe_tv080wum_nl0
2339 }, {
2340 .compatible = "lg,ld070wx3-sl01",
2341 .data = &lg_ld070wx3_sl01
2342 }, {
2343 .compatible = "lg,lh500wx1-sd03",
2344 .data = &lg_lh500wx1_sd03
2345 }, {
2346 .compatible = "panasonic,vvx10f004b00",
2347 .data = &panasonic_vvx10f004b00
2348 }, {
2349 /* sentinel */
2350 }
2351 };
2352 MODULE_DEVICE_TABLE(of, dsi_of_match);
2353
panel_simple_dsi_probe(struct mipi_dsi_device * dsi)2354 static int panel_simple_dsi_probe(struct mipi_dsi_device *dsi)
2355 {
2356 const struct panel_desc_dsi *desc;
2357 const struct of_device_id *id;
2358 int err;
2359
2360 id = of_match_node(dsi_of_match, dsi->dev.of_node);
2361 if (!id)
2362 return -ENODEV;
2363
2364 desc = id->data;
2365
2366 err = panel_simple_probe(&dsi->dev, &desc->desc);
2367 if (err < 0)
2368 return err;
2369
2370 dsi->mode_flags = desc->flags;
2371 dsi->format = desc->format;
2372 dsi->lanes = desc->lanes;
2373
2374 err = mipi_dsi_attach(dsi);
2375 if (err) {
2376 struct panel_simple *panel = dev_get_drvdata(&dsi->dev);
2377
2378 drm_panel_remove(&panel->base);
2379 }
2380
2381 return err;
2382 }
2383
panel_simple_dsi_remove(struct mipi_dsi_device * dsi)2384 static int panel_simple_dsi_remove(struct mipi_dsi_device *dsi)
2385 {
2386 int err;
2387
2388 err = mipi_dsi_detach(dsi);
2389 if (err < 0)
2390 dev_err(&dsi->dev, "failed to detach from DSI host: %d\n", err);
2391
2392 return panel_simple_remove(&dsi->dev);
2393 }
2394
panel_simple_dsi_shutdown(struct mipi_dsi_device * dsi)2395 static void panel_simple_dsi_shutdown(struct mipi_dsi_device *dsi)
2396 {
2397 panel_simple_shutdown(&dsi->dev);
2398 }
2399
2400 static struct mipi_dsi_driver panel_simple_dsi_driver = {
2401 .driver = {
2402 .name = "panel-simple-dsi",
2403 .of_match_table = dsi_of_match,
2404 },
2405 .probe = panel_simple_dsi_probe,
2406 .remove = panel_simple_dsi_remove,
2407 .shutdown = panel_simple_dsi_shutdown,
2408 };
2409
panel_simple_init(void)2410 static int __init panel_simple_init(void)
2411 {
2412 int err;
2413
2414 err = platform_driver_register(&panel_simple_platform_driver);
2415 if (err < 0)
2416 return err;
2417
2418 if (IS_ENABLED(CONFIG_DRM_MIPI_DSI)) {
2419 err = mipi_dsi_driver_register(&panel_simple_dsi_driver);
2420 if (err < 0)
2421 return err;
2422 }
2423
2424 return 0;
2425 }
2426 module_init(panel_simple_init);
2427
panel_simple_exit(void)2428 static void __exit panel_simple_exit(void)
2429 {
2430 if (IS_ENABLED(CONFIG_DRM_MIPI_DSI))
2431 mipi_dsi_driver_unregister(&panel_simple_dsi_driver);
2432
2433 platform_driver_unregister(&panel_simple_platform_driver);
2434 }
2435 module_exit(panel_simple_exit);
2436
2437 MODULE_AUTHOR("Thierry Reding <treding@nvidia.com>");
2438 MODULE_DESCRIPTION("DRM Driver for Simple Panels");
2439 MODULE_LICENSE("GPL and additional rights");
2440