1 /*
2 * rcar_du_crtc.c -- R-Car Display Unit CRTCs
3 *
4 * Copyright (C) 2013-2015 Renesas Electronics Corporation
5 *
6 * Contact: Laurent Pinchart (laurent.pinchart@ideasonboard.com)
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation; either version 2 of the License, or
11 * (at your option) any later version.
12 */
13
14 #include <linux/clk.h>
15 #include <linux/mutex.h>
16 #include <linux/sys_soc.h>
17
18 #include <drm/drmP.h>
19 #include <drm/drm_atomic.h>
20 #include <drm/drm_atomic_helper.h>
21 #include <drm/drm_crtc.h>
22 #include <drm/drm_crtc_helper.h>
23 #include <drm/drm_fb_cma_helper.h>
24 #include <drm/drm_gem_cma_helper.h>
25 #include <drm/drm_plane_helper.h>
26
27 #include "rcar_du_crtc.h"
28 #include "rcar_du_drv.h"
29 #include "rcar_du_kms.h"
30 #include "rcar_du_plane.h"
31 #include "rcar_du_regs.h"
32 #include "rcar_du_vsp.h"
33
rcar_du_crtc_read(struct rcar_du_crtc * rcrtc,u32 reg)34 static u32 rcar_du_crtc_read(struct rcar_du_crtc *rcrtc, u32 reg)
35 {
36 struct rcar_du_device *rcdu = rcrtc->group->dev;
37
38 return rcar_du_read(rcdu, rcrtc->mmio_offset + reg);
39 }
40
rcar_du_crtc_write(struct rcar_du_crtc * rcrtc,u32 reg,u32 data)41 static void rcar_du_crtc_write(struct rcar_du_crtc *rcrtc, u32 reg, u32 data)
42 {
43 struct rcar_du_device *rcdu = rcrtc->group->dev;
44
45 rcar_du_write(rcdu, rcrtc->mmio_offset + reg, data);
46 }
47
rcar_du_crtc_clr(struct rcar_du_crtc * rcrtc,u32 reg,u32 clr)48 static void rcar_du_crtc_clr(struct rcar_du_crtc *rcrtc, u32 reg, u32 clr)
49 {
50 struct rcar_du_device *rcdu = rcrtc->group->dev;
51
52 rcar_du_write(rcdu, rcrtc->mmio_offset + reg,
53 rcar_du_read(rcdu, rcrtc->mmio_offset + reg) & ~clr);
54 }
55
rcar_du_crtc_set(struct rcar_du_crtc * rcrtc,u32 reg,u32 set)56 static void rcar_du_crtc_set(struct rcar_du_crtc *rcrtc, u32 reg, u32 set)
57 {
58 struct rcar_du_device *rcdu = rcrtc->group->dev;
59
60 rcar_du_write(rcdu, rcrtc->mmio_offset + reg,
61 rcar_du_read(rcdu, rcrtc->mmio_offset + reg) | set);
62 }
63
rcar_du_crtc_clr_set(struct rcar_du_crtc * rcrtc,u32 reg,u32 clr,u32 set)64 static void rcar_du_crtc_clr_set(struct rcar_du_crtc *rcrtc, u32 reg,
65 u32 clr, u32 set)
66 {
67 struct rcar_du_device *rcdu = rcrtc->group->dev;
68 u32 value = rcar_du_read(rcdu, rcrtc->mmio_offset + reg);
69
70 rcar_du_write(rcdu, rcrtc->mmio_offset + reg, (value & ~clr) | set);
71 }
72
rcar_du_crtc_get(struct rcar_du_crtc * rcrtc)73 static int rcar_du_crtc_get(struct rcar_du_crtc *rcrtc)
74 {
75 int ret;
76
77 ret = clk_prepare_enable(rcrtc->clock);
78 if (ret < 0)
79 return ret;
80
81 ret = clk_prepare_enable(rcrtc->extclock);
82 if (ret < 0)
83 goto error_clock;
84
85 ret = rcar_du_group_get(rcrtc->group);
86 if (ret < 0)
87 goto error_group;
88
89 return 0;
90
91 error_group:
92 clk_disable_unprepare(rcrtc->extclock);
93 error_clock:
94 clk_disable_unprepare(rcrtc->clock);
95 return ret;
96 }
97
rcar_du_crtc_put(struct rcar_du_crtc * rcrtc)98 static void rcar_du_crtc_put(struct rcar_du_crtc *rcrtc)
99 {
100 rcar_du_group_put(rcrtc->group);
101
102 clk_disable_unprepare(rcrtc->extclock);
103 clk_disable_unprepare(rcrtc->clock);
104 }
105
106 /* -----------------------------------------------------------------------------
107 * Hardware Setup
108 */
109
110 struct dpll_info {
111 unsigned int output;
112 unsigned int fdpll;
113 unsigned int n;
114 unsigned int m;
115 };
116
rcar_du_dpll_divider(struct rcar_du_crtc * rcrtc,struct dpll_info * dpll,unsigned long input,unsigned long target)117 static void rcar_du_dpll_divider(struct rcar_du_crtc *rcrtc,
118 struct dpll_info *dpll,
119 unsigned long input,
120 unsigned long target)
121 {
122 unsigned long best_diff = (unsigned long)-1;
123 unsigned long diff;
124 unsigned int fdpll;
125 unsigned int m;
126 unsigned int n;
127
128 for (n = 39; n < 120; n++) {
129 for (m = 0; m < 4; m++) {
130 for (fdpll = 1; fdpll < 32; fdpll++) {
131 unsigned long output;
132
133 output = input * (n + 1) / (m + 1)
134 / (fdpll + 1);
135 if (output >= 400000000)
136 continue;
137
138 diff = abs((long)output - (long)target);
139 if (best_diff > diff) {
140 best_diff = diff;
141 dpll->n = n;
142 dpll->m = m;
143 dpll->fdpll = fdpll;
144 dpll->output = output;
145 }
146
147 if (diff == 0)
148 goto done;
149 }
150 }
151 }
152
153 done:
154 dev_dbg(rcrtc->group->dev->dev,
155 "output:%u, fdpll:%u, n:%u, m:%u, diff:%lu\n",
156 dpll->output, dpll->fdpll, dpll->n, dpll->m,
157 best_diff);
158 }
159
160 static const struct soc_device_attribute rcar_du_r8a7795_es1[] = {
161 { .soc_id = "r8a7795", .revision = "ES1.*" },
162 { /* sentinel */ }
163 };
164
rcar_du_crtc_set_display_timing(struct rcar_du_crtc * rcrtc)165 static void rcar_du_crtc_set_display_timing(struct rcar_du_crtc *rcrtc)
166 {
167 const struct drm_display_mode *mode = &rcrtc->crtc.state->adjusted_mode;
168 struct rcar_du_device *rcdu = rcrtc->group->dev;
169 unsigned long mode_clock = mode->clock * 1000;
170 unsigned long clk;
171 u32 value;
172 u32 escr;
173 u32 div;
174
175 /*
176 * Compute the clock divisor and select the internal or external dot
177 * clock based on the requested frequency.
178 */
179 clk = clk_get_rate(rcrtc->clock);
180 div = DIV_ROUND_CLOSEST(clk, mode_clock);
181 div = clamp(div, 1U, 64U) - 1;
182 escr = div | ESCR_DCLKSEL_CLKS;
183
184 if (rcrtc->extclock) {
185 struct dpll_info dpll = { 0 };
186 unsigned long extclk;
187 unsigned long extrate;
188 unsigned long rate;
189 u32 extdiv;
190
191 extclk = clk_get_rate(rcrtc->extclock);
192 if (rcdu->info->dpll_ch & (1 << rcrtc->index)) {
193 unsigned long target = mode_clock;
194
195 /*
196 * The H3 ES1.x exhibits dot clock duty cycle stability
197 * issues. We can work around them by configuring the
198 * DPLL to twice the desired frequency, coupled with a
199 * /2 post-divider. This isn't needed on other SoCs and
200 * breaks HDMI output on M3-W for a currently unknown
201 * reason, so restrict the workaround to H3 ES1.x.
202 */
203 if (soc_device_match(rcar_du_r8a7795_es1))
204 target *= 2;
205
206 rcar_du_dpll_divider(rcrtc, &dpll, extclk, target);
207 extclk = dpll.output;
208 }
209
210 extdiv = DIV_ROUND_CLOSEST(extclk, mode_clock);
211 extdiv = clamp(extdiv, 1U, 64U) - 1;
212
213 rate = clk / (div + 1);
214 extrate = extclk / (extdiv + 1);
215
216 if (abs((long)extrate - (long)mode_clock) <
217 abs((long)rate - (long)mode_clock)) {
218
219 if (rcdu->info->dpll_ch & (1 << rcrtc->index)) {
220 u32 dpllcr = DPLLCR_CODE | DPLLCR_CLKE
221 | DPLLCR_FDPLL(dpll.fdpll)
222 | DPLLCR_N(dpll.n) | DPLLCR_M(dpll.m)
223 | DPLLCR_STBY;
224
225 if (rcrtc->index == 1)
226 dpllcr |= DPLLCR_PLCS1
227 | DPLLCR_INCS_DOTCLKIN1;
228 else
229 dpllcr |= DPLLCR_PLCS0
230 | DPLLCR_INCS_DOTCLKIN0;
231
232 rcar_du_group_write(rcrtc->group, DPLLCR,
233 dpllcr);
234 }
235
236 escr = ESCR_DCLKSEL_DCLKIN | extdiv;
237 }
238
239 dev_dbg(rcrtc->group->dev->dev,
240 "mode clock %lu extrate %lu rate %lu ESCR 0x%08x\n",
241 mode_clock, extrate, rate, escr);
242 }
243
244 rcar_du_group_write(rcrtc->group, rcrtc->index % 2 ? ESCR2 : ESCR,
245 escr);
246 rcar_du_group_write(rcrtc->group, rcrtc->index % 2 ? OTAR2 : OTAR, 0);
247
248 /* Signal polarities */
249 value = ((mode->flags & DRM_MODE_FLAG_PVSYNC) ? DSMR_VSL : 0)
250 | ((mode->flags & DRM_MODE_FLAG_PHSYNC) ? DSMR_HSL : 0)
251 | DSMR_DIPM_DISP | DSMR_CSPM;
252 rcar_du_crtc_write(rcrtc, DSMR, value);
253
254 /* Display timings */
255 rcar_du_crtc_write(rcrtc, HDSR, mode->htotal - mode->hsync_start - 19);
256 rcar_du_crtc_write(rcrtc, HDER, mode->htotal - mode->hsync_start +
257 mode->hdisplay - 19);
258 rcar_du_crtc_write(rcrtc, HSWR, mode->hsync_end -
259 mode->hsync_start - 1);
260 rcar_du_crtc_write(rcrtc, HCR, mode->htotal - 1);
261
262 rcar_du_crtc_write(rcrtc, VDSR, mode->crtc_vtotal -
263 mode->crtc_vsync_end - 2);
264 rcar_du_crtc_write(rcrtc, VDER, mode->crtc_vtotal -
265 mode->crtc_vsync_end +
266 mode->crtc_vdisplay - 2);
267 rcar_du_crtc_write(rcrtc, VSPR, mode->crtc_vtotal -
268 mode->crtc_vsync_end +
269 mode->crtc_vsync_start - 1);
270 rcar_du_crtc_write(rcrtc, VCR, mode->crtc_vtotal - 1);
271
272 rcar_du_crtc_write(rcrtc, DESR, mode->htotal - mode->hsync_start - 1);
273 rcar_du_crtc_write(rcrtc, DEWR, mode->hdisplay);
274 }
275
rcar_du_crtc_route_output(struct drm_crtc * crtc,enum rcar_du_output output)276 void rcar_du_crtc_route_output(struct drm_crtc *crtc,
277 enum rcar_du_output output)
278 {
279 struct rcar_du_crtc *rcrtc = to_rcar_crtc(crtc);
280 struct rcar_du_device *rcdu = rcrtc->group->dev;
281
282 /*
283 * Store the route from the CRTC output to the DU output. The DU will be
284 * configured when starting the CRTC.
285 */
286 rcrtc->outputs |= BIT(output);
287
288 /*
289 * Store RGB routing to DPAD0, the hardware will be configured when
290 * starting the CRTC.
291 */
292 if (output == RCAR_DU_OUTPUT_DPAD0)
293 rcdu->dpad0_source = rcrtc->index;
294 }
295
plane_zpos(struct rcar_du_plane * plane)296 static unsigned int plane_zpos(struct rcar_du_plane *plane)
297 {
298 return plane->plane.state->normalized_zpos;
299 }
300
301 static const struct rcar_du_format_info *
plane_format(struct rcar_du_plane * plane)302 plane_format(struct rcar_du_plane *plane)
303 {
304 return to_rcar_plane_state(plane->plane.state)->format;
305 }
306
rcar_du_crtc_update_planes(struct rcar_du_crtc * rcrtc)307 static void rcar_du_crtc_update_planes(struct rcar_du_crtc *rcrtc)
308 {
309 struct rcar_du_plane *planes[RCAR_DU_NUM_HW_PLANES];
310 struct rcar_du_device *rcdu = rcrtc->group->dev;
311 unsigned int num_planes = 0;
312 unsigned int dptsr_planes;
313 unsigned int hwplanes = 0;
314 unsigned int prio = 0;
315 unsigned int i;
316 u32 dspr = 0;
317
318 for (i = 0; i < rcrtc->group->num_planes; ++i) {
319 struct rcar_du_plane *plane = &rcrtc->group->planes[i];
320 unsigned int j;
321
322 if (plane->plane.state->crtc != &rcrtc->crtc)
323 continue;
324
325 /* Insert the plane in the sorted planes array. */
326 for (j = num_planes++; j > 0; --j) {
327 if (plane_zpos(planes[j-1]) <= plane_zpos(plane))
328 break;
329 planes[j] = planes[j-1];
330 }
331
332 planes[j] = plane;
333 prio += plane_format(plane)->planes * 4;
334 }
335
336 for (i = 0; i < num_planes; ++i) {
337 struct rcar_du_plane *plane = planes[i];
338 struct drm_plane_state *state = plane->plane.state;
339 unsigned int index = to_rcar_plane_state(state)->hwindex;
340
341 prio -= 4;
342 dspr |= (index + 1) << prio;
343 hwplanes |= 1 << index;
344
345 if (plane_format(plane)->planes == 2) {
346 index = (index + 1) % 8;
347
348 prio -= 4;
349 dspr |= (index + 1) << prio;
350 hwplanes |= 1 << index;
351 }
352 }
353
354 /* If VSP+DU integration is enabled the plane assignment is fixed. */
355 if (rcar_du_has(rcdu, RCAR_DU_FEATURE_VSP1_SOURCE)) {
356 if (rcdu->info->gen < 3) {
357 dspr = (rcrtc->index % 2) + 1;
358 hwplanes = 1 << (rcrtc->index % 2);
359 } else {
360 dspr = (rcrtc->index % 2) ? 3 : 1;
361 hwplanes = 1 << ((rcrtc->index % 2) ? 2 : 0);
362 }
363 }
364
365 /*
366 * Update the planes to display timing and dot clock generator
367 * associations.
368 *
369 * Updating the DPTSR register requires restarting the CRTC group,
370 * resulting in visible flicker. To mitigate the issue only update the
371 * association if needed by enabled planes. Planes being disabled will
372 * keep their current association.
373 */
374 mutex_lock(&rcrtc->group->lock);
375
376 dptsr_planes = rcrtc->index % 2 ? rcrtc->group->dptsr_planes | hwplanes
377 : rcrtc->group->dptsr_planes & ~hwplanes;
378
379 if (dptsr_planes != rcrtc->group->dptsr_planes) {
380 rcar_du_group_write(rcrtc->group, DPTSR,
381 (dptsr_planes << 16) | dptsr_planes);
382 rcrtc->group->dptsr_planes = dptsr_planes;
383
384 if (rcrtc->group->used_crtcs)
385 rcar_du_group_restart(rcrtc->group);
386 }
387
388 /* Restart the group if plane sources have changed. */
389 if (rcrtc->group->need_restart)
390 rcar_du_group_restart(rcrtc->group);
391
392 mutex_unlock(&rcrtc->group->lock);
393
394 rcar_du_group_write(rcrtc->group, rcrtc->index % 2 ? DS2PR : DS1PR,
395 dspr);
396 }
397
398 /* -----------------------------------------------------------------------------
399 * Page Flip
400 */
401
rcar_du_crtc_finish_page_flip(struct rcar_du_crtc * rcrtc)402 void rcar_du_crtc_finish_page_flip(struct rcar_du_crtc *rcrtc)
403 {
404 struct drm_pending_vblank_event *event;
405 struct drm_device *dev = rcrtc->crtc.dev;
406 unsigned long flags;
407
408 spin_lock_irqsave(&dev->event_lock, flags);
409 event = rcrtc->event;
410 rcrtc->event = NULL;
411 spin_unlock_irqrestore(&dev->event_lock, flags);
412
413 if (event == NULL)
414 return;
415
416 spin_lock_irqsave(&dev->event_lock, flags);
417 drm_crtc_send_vblank_event(&rcrtc->crtc, event);
418 wake_up(&rcrtc->flip_wait);
419 spin_unlock_irqrestore(&dev->event_lock, flags);
420
421 drm_crtc_vblank_put(&rcrtc->crtc);
422 }
423
rcar_du_crtc_page_flip_pending(struct rcar_du_crtc * rcrtc)424 static bool rcar_du_crtc_page_flip_pending(struct rcar_du_crtc *rcrtc)
425 {
426 struct drm_device *dev = rcrtc->crtc.dev;
427 unsigned long flags;
428 bool pending;
429
430 spin_lock_irqsave(&dev->event_lock, flags);
431 pending = rcrtc->event != NULL;
432 spin_unlock_irqrestore(&dev->event_lock, flags);
433
434 return pending;
435 }
436
rcar_du_crtc_wait_page_flip(struct rcar_du_crtc * rcrtc)437 static void rcar_du_crtc_wait_page_flip(struct rcar_du_crtc *rcrtc)
438 {
439 struct rcar_du_device *rcdu = rcrtc->group->dev;
440
441 if (wait_event_timeout(rcrtc->flip_wait,
442 !rcar_du_crtc_page_flip_pending(rcrtc),
443 msecs_to_jiffies(50)))
444 return;
445
446 dev_warn(rcdu->dev, "page flip timeout\n");
447
448 rcar_du_crtc_finish_page_flip(rcrtc);
449 }
450
451 /* -----------------------------------------------------------------------------
452 * Start/Stop and Suspend/Resume
453 */
454
rcar_du_crtc_setup(struct rcar_du_crtc * rcrtc)455 static void rcar_du_crtc_setup(struct rcar_du_crtc *rcrtc)
456 {
457 /* Set display off and background to black */
458 rcar_du_crtc_write(rcrtc, DOOR, DOOR_RGB(0, 0, 0));
459 rcar_du_crtc_write(rcrtc, BPOR, BPOR_RGB(0, 0, 0));
460
461 /* Configure display timings and output routing */
462 rcar_du_crtc_set_display_timing(rcrtc);
463 rcar_du_group_set_routing(rcrtc->group);
464
465 /* Start with all planes disabled. */
466 rcar_du_group_write(rcrtc->group, rcrtc->index % 2 ? DS2PR : DS1PR, 0);
467
468 /* Enable the VSP compositor. */
469 if (rcar_du_has(rcrtc->group->dev, RCAR_DU_FEATURE_VSP1_SOURCE))
470 rcar_du_vsp_enable(rcrtc);
471
472 /* Turn vertical blanking interrupt reporting on. */
473 drm_crtc_vblank_on(&rcrtc->crtc);
474 }
475
rcar_du_crtc_start(struct rcar_du_crtc * rcrtc)476 static void rcar_du_crtc_start(struct rcar_du_crtc *rcrtc)
477 {
478 bool interlaced;
479
480 /*
481 * Select master sync mode. This enables display operation in master
482 * sync mode (with the HSYNC and VSYNC signals configured as outputs and
483 * actively driven).
484 */
485 interlaced = rcrtc->crtc.mode.flags & DRM_MODE_FLAG_INTERLACE;
486 rcar_du_crtc_clr_set(rcrtc, DSYSR, DSYSR_TVM_MASK | DSYSR_SCM_MASK,
487 (interlaced ? DSYSR_SCM_INT_VIDEO : 0) |
488 DSYSR_TVM_MASTER);
489
490 rcar_du_group_start_stop(rcrtc->group, true);
491 }
492
rcar_du_crtc_disable_planes(struct rcar_du_crtc * rcrtc)493 static void rcar_du_crtc_disable_planes(struct rcar_du_crtc *rcrtc)
494 {
495 struct rcar_du_device *rcdu = rcrtc->group->dev;
496 struct drm_crtc *crtc = &rcrtc->crtc;
497 u32 status;
498
499 /* Make sure vblank interrupts are enabled. */
500 drm_crtc_vblank_get(crtc);
501
502 /*
503 * Disable planes and calculate how many vertical blanking interrupts we
504 * have to wait for. If a vertical blanking interrupt has been triggered
505 * but not processed yet, we don't know whether it occurred before or
506 * after the planes got disabled. We thus have to wait for two vblank
507 * interrupts in that case.
508 */
509 spin_lock_irq(&rcrtc->vblank_lock);
510 rcar_du_group_write(rcrtc->group, rcrtc->index % 2 ? DS2PR : DS1PR, 0);
511 status = rcar_du_crtc_read(rcrtc, DSSR);
512 rcrtc->vblank_count = status & DSSR_VBK ? 2 : 1;
513 spin_unlock_irq(&rcrtc->vblank_lock);
514
515 if (!wait_event_timeout(rcrtc->vblank_wait, rcrtc->vblank_count == 0,
516 msecs_to_jiffies(100)))
517 dev_warn(rcdu->dev, "vertical blanking timeout\n");
518
519 drm_crtc_vblank_put(crtc);
520 }
521
rcar_du_crtc_stop(struct rcar_du_crtc * rcrtc)522 static void rcar_du_crtc_stop(struct rcar_du_crtc *rcrtc)
523 {
524 struct drm_crtc *crtc = &rcrtc->crtc;
525
526 /*
527 * Disable all planes and wait for the change to take effect. This is
528 * required as the plane enable registers are updated on vblank, and no
529 * vblank will occur once the CRTC is stopped. Disabling planes when
530 * starting the CRTC thus wouldn't be enough as it would start scanning
531 * out immediately from old frame buffers until the next vblank.
532 *
533 * This increases the CRTC stop delay, especially when multiple CRTCs
534 * are stopped in one operation as we now wait for one vblank per CRTC.
535 * Whether this can be improved needs to be researched.
536 */
537 rcar_du_crtc_disable_planes(rcrtc);
538
539 /*
540 * Disable vertical blanking interrupt reporting. We first need to wait
541 * for page flip completion before stopping the CRTC as userspace
542 * expects page flips to eventually complete.
543 */
544 rcar_du_crtc_wait_page_flip(rcrtc);
545 drm_crtc_vblank_off(crtc);
546
547 /* Disable the VSP compositor. */
548 if (rcar_du_has(rcrtc->group->dev, RCAR_DU_FEATURE_VSP1_SOURCE))
549 rcar_du_vsp_disable(rcrtc);
550
551 /*
552 * Select switch sync mode. This stops display operation and configures
553 * the HSYNC and VSYNC signals as inputs.
554 */
555 rcar_du_crtc_clr_set(rcrtc, DSYSR, DSYSR_TVM_MASK, DSYSR_TVM_SWITCH);
556
557 rcar_du_group_start_stop(rcrtc->group, false);
558 }
559
rcar_du_crtc_suspend(struct rcar_du_crtc * rcrtc)560 void rcar_du_crtc_suspend(struct rcar_du_crtc *rcrtc)
561 {
562 if (rcar_du_has(rcrtc->group->dev, RCAR_DU_FEATURE_VSP1_SOURCE))
563 rcar_du_vsp_disable(rcrtc);
564
565 rcar_du_crtc_stop(rcrtc);
566 rcar_du_crtc_put(rcrtc);
567 }
568
rcar_du_crtc_resume(struct rcar_du_crtc * rcrtc)569 void rcar_du_crtc_resume(struct rcar_du_crtc *rcrtc)
570 {
571 unsigned int i;
572
573 if (!rcrtc->crtc.state->active)
574 return;
575
576 rcar_du_crtc_get(rcrtc);
577 rcar_du_crtc_setup(rcrtc);
578
579 /* Commit the planes state. */
580 if (!rcar_du_has(rcrtc->group->dev, RCAR_DU_FEATURE_VSP1_SOURCE)) {
581 for (i = 0; i < rcrtc->group->num_planes; ++i) {
582 struct rcar_du_plane *plane = &rcrtc->group->planes[i];
583
584 if (plane->plane.state->crtc != &rcrtc->crtc)
585 continue;
586
587 rcar_du_plane_setup(plane);
588 }
589 }
590
591 rcar_du_crtc_update_planes(rcrtc);
592 rcar_du_crtc_start(rcrtc);
593 }
594
595 /* -----------------------------------------------------------------------------
596 * CRTC Functions
597 */
598
rcar_du_crtc_atomic_enable(struct drm_crtc * crtc,struct drm_crtc_state * old_state)599 static void rcar_du_crtc_atomic_enable(struct drm_crtc *crtc,
600 struct drm_crtc_state *old_state)
601 {
602 struct rcar_du_crtc *rcrtc = to_rcar_crtc(crtc);
603
604 /*
605 * If the CRTC has already been setup by the .atomic_begin() handler we
606 * can skip the setup stage.
607 */
608 if (!rcrtc->initialized) {
609 rcar_du_crtc_get(rcrtc);
610 rcar_du_crtc_setup(rcrtc);
611 rcrtc->initialized = true;
612 }
613
614 rcar_du_crtc_start(rcrtc);
615 }
616
rcar_du_crtc_atomic_disable(struct drm_crtc * crtc,struct drm_crtc_state * old_state)617 static void rcar_du_crtc_atomic_disable(struct drm_crtc *crtc,
618 struct drm_crtc_state *old_state)
619 {
620 struct rcar_du_crtc *rcrtc = to_rcar_crtc(crtc);
621
622 rcar_du_crtc_stop(rcrtc);
623 rcar_du_crtc_put(rcrtc);
624
625 spin_lock_irq(&crtc->dev->event_lock);
626 if (crtc->state->event) {
627 drm_crtc_send_vblank_event(crtc, crtc->state->event);
628 crtc->state->event = NULL;
629 }
630 spin_unlock_irq(&crtc->dev->event_lock);
631
632 rcrtc->initialized = false;
633 rcrtc->outputs = 0;
634 }
635
rcar_du_crtc_atomic_begin(struct drm_crtc * crtc,struct drm_crtc_state * old_crtc_state)636 static void rcar_du_crtc_atomic_begin(struct drm_crtc *crtc,
637 struct drm_crtc_state *old_crtc_state)
638 {
639 struct rcar_du_crtc *rcrtc = to_rcar_crtc(crtc);
640
641 WARN_ON(!crtc->state->enable);
642
643 /*
644 * If a mode set is in progress we can be called with the CRTC disabled.
645 * We then need to first setup the CRTC in order to configure planes.
646 * The .atomic_enable() handler will notice and skip the CRTC setup.
647 */
648 if (!rcrtc->initialized) {
649 rcar_du_crtc_get(rcrtc);
650 rcar_du_crtc_setup(rcrtc);
651 rcrtc->initialized = true;
652 }
653
654 if (rcar_du_has(rcrtc->group->dev, RCAR_DU_FEATURE_VSP1_SOURCE))
655 rcar_du_vsp_atomic_begin(rcrtc);
656 }
657
rcar_du_crtc_atomic_flush(struct drm_crtc * crtc,struct drm_crtc_state * old_crtc_state)658 static void rcar_du_crtc_atomic_flush(struct drm_crtc *crtc,
659 struct drm_crtc_state *old_crtc_state)
660 {
661 struct rcar_du_crtc *rcrtc = to_rcar_crtc(crtc);
662 struct drm_device *dev = rcrtc->crtc.dev;
663 unsigned long flags;
664
665 rcar_du_crtc_update_planes(rcrtc);
666
667 if (crtc->state->event) {
668 WARN_ON(drm_crtc_vblank_get(crtc) != 0);
669
670 spin_lock_irqsave(&dev->event_lock, flags);
671 rcrtc->event = crtc->state->event;
672 crtc->state->event = NULL;
673 spin_unlock_irqrestore(&dev->event_lock, flags);
674 }
675
676 if (rcar_du_has(rcrtc->group->dev, RCAR_DU_FEATURE_VSP1_SOURCE))
677 rcar_du_vsp_atomic_flush(rcrtc);
678 }
679
680 static const struct drm_crtc_helper_funcs crtc_helper_funcs = {
681 .atomic_begin = rcar_du_crtc_atomic_begin,
682 .atomic_flush = rcar_du_crtc_atomic_flush,
683 .atomic_enable = rcar_du_crtc_atomic_enable,
684 .atomic_disable = rcar_du_crtc_atomic_disable,
685 };
686
rcar_du_crtc_enable_vblank(struct drm_crtc * crtc)687 static int rcar_du_crtc_enable_vblank(struct drm_crtc *crtc)
688 {
689 struct rcar_du_crtc *rcrtc = to_rcar_crtc(crtc);
690
691 rcar_du_crtc_write(rcrtc, DSRCR, DSRCR_VBCL);
692 rcar_du_crtc_set(rcrtc, DIER, DIER_VBE);
693 rcrtc->vblank_enable = true;
694
695 return 0;
696 }
697
rcar_du_crtc_disable_vblank(struct drm_crtc * crtc)698 static void rcar_du_crtc_disable_vblank(struct drm_crtc *crtc)
699 {
700 struct rcar_du_crtc *rcrtc = to_rcar_crtc(crtc);
701
702 rcar_du_crtc_clr(rcrtc, DIER, DIER_VBE);
703 rcrtc->vblank_enable = false;
704 }
705
706 static const struct drm_crtc_funcs crtc_funcs = {
707 .reset = drm_atomic_helper_crtc_reset,
708 .destroy = drm_crtc_cleanup,
709 .set_config = drm_atomic_helper_set_config,
710 .page_flip = drm_atomic_helper_page_flip,
711 .atomic_duplicate_state = drm_atomic_helper_crtc_duplicate_state,
712 .atomic_destroy_state = drm_atomic_helper_crtc_destroy_state,
713 .enable_vblank = rcar_du_crtc_enable_vblank,
714 .disable_vblank = rcar_du_crtc_disable_vblank,
715 };
716
717 /* -----------------------------------------------------------------------------
718 * Interrupt Handling
719 */
720
rcar_du_crtc_irq(int irq,void * arg)721 static irqreturn_t rcar_du_crtc_irq(int irq, void *arg)
722 {
723 struct rcar_du_crtc *rcrtc = arg;
724 struct rcar_du_device *rcdu = rcrtc->group->dev;
725 irqreturn_t ret = IRQ_NONE;
726 u32 status;
727
728 spin_lock(&rcrtc->vblank_lock);
729
730 status = rcar_du_crtc_read(rcrtc, DSSR);
731 rcar_du_crtc_write(rcrtc, DSRCR, status & DSRCR_MASK);
732
733 if (status & DSSR_VBK) {
734 /*
735 * Wake up the vblank wait if the counter reaches 0. This must
736 * be protected by the vblank_lock to avoid races in
737 * rcar_du_crtc_disable_planes().
738 */
739 if (rcrtc->vblank_count) {
740 if (--rcrtc->vblank_count == 0)
741 wake_up(&rcrtc->vblank_wait);
742 }
743 }
744
745 spin_unlock(&rcrtc->vblank_lock);
746
747 if (status & DSSR_VBK) {
748 if (rcdu->info->gen < 3) {
749 drm_crtc_handle_vblank(&rcrtc->crtc);
750 rcar_du_crtc_finish_page_flip(rcrtc);
751 }
752
753 ret = IRQ_HANDLED;
754 }
755
756 return ret;
757 }
758
759 /* -----------------------------------------------------------------------------
760 * Initialization
761 */
762
rcar_du_crtc_create(struct rcar_du_group * rgrp,unsigned int index)763 int rcar_du_crtc_create(struct rcar_du_group *rgrp, unsigned int index)
764 {
765 static const unsigned int mmio_offsets[] = {
766 DU0_REG_OFFSET, DU1_REG_OFFSET, DU2_REG_OFFSET, DU3_REG_OFFSET
767 };
768
769 struct rcar_du_device *rcdu = rgrp->dev;
770 struct platform_device *pdev = to_platform_device(rcdu->dev);
771 struct rcar_du_crtc *rcrtc = &rcdu->crtcs[index];
772 struct drm_crtc *crtc = &rcrtc->crtc;
773 struct drm_plane *primary;
774 unsigned int irqflags;
775 struct clk *clk;
776 char clk_name[9];
777 char *name;
778 int irq;
779 int ret;
780
781 /* Get the CRTC clock and the optional external clock. */
782 if (rcar_du_has(rcdu, RCAR_DU_FEATURE_CRTC_IRQ_CLOCK)) {
783 sprintf(clk_name, "du.%u", index);
784 name = clk_name;
785 } else {
786 name = NULL;
787 }
788
789 rcrtc->clock = devm_clk_get(rcdu->dev, name);
790 if (IS_ERR(rcrtc->clock)) {
791 dev_err(rcdu->dev, "no clock for CRTC %u\n", index);
792 return PTR_ERR(rcrtc->clock);
793 }
794
795 sprintf(clk_name, "dclkin.%u", index);
796 clk = devm_clk_get(rcdu->dev, clk_name);
797 if (!IS_ERR(clk)) {
798 rcrtc->extclock = clk;
799 } else if (PTR_ERR(rcrtc->clock) == -EPROBE_DEFER) {
800 dev_info(rcdu->dev, "can't get external clock %u\n", index);
801 return -EPROBE_DEFER;
802 }
803
804 init_waitqueue_head(&rcrtc->flip_wait);
805 init_waitqueue_head(&rcrtc->vblank_wait);
806 spin_lock_init(&rcrtc->vblank_lock);
807
808 rcrtc->group = rgrp;
809 rcrtc->mmio_offset = mmio_offsets[index];
810 rcrtc->index = index;
811
812 if (rcar_du_has(rcdu, RCAR_DU_FEATURE_VSP1_SOURCE))
813 primary = &rcrtc->vsp->planes[rcrtc->vsp_pipe].plane;
814 else
815 primary = &rgrp->planes[index % 2].plane;
816
817 ret = drm_crtc_init_with_planes(rcdu->ddev, crtc, primary,
818 NULL, &crtc_funcs, NULL);
819 if (ret < 0)
820 return ret;
821
822 drm_crtc_helper_add(crtc, &crtc_helper_funcs);
823
824 /* Start with vertical blanking interrupt reporting disabled. */
825 drm_crtc_vblank_off(crtc);
826
827 /* Register the interrupt handler. */
828 if (rcar_du_has(rcdu, RCAR_DU_FEATURE_CRTC_IRQ_CLOCK)) {
829 irq = platform_get_irq(pdev, index);
830 irqflags = 0;
831 } else {
832 irq = platform_get_irq(pdev, 0);
833 irqflags = IRQF_SHARED;
834 }
835
836 if (irq < 0) {
837 dev_err(rcdu->dev, "no IRQ for CRTC %u\n", index);
838 return irq;
839 }
840
841 ret = devm_request_irq(rcdu->dev, irq, rcar_du_crtc_irq, irqflags,
842 dev_name(rcdu->dev), rcrtc);
843 if (ret < 0) {
844 dev_err(rcdu->dev,
845 "failed to register IRQ for CRTC %u\n", index);
846 return ret;
847 }
848
849 return 0;
850 }
851