1 /*
2 * Copyright (C) 2016 Free Electrons
3 * Copyright (C) 2016 NextThing Co
4 *
5 * Maxime Ripard <maxime.ripard@free-electrons.com>
6 *
7 * This program is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU General Public License as
9 * published by the Free Software Foundation; either version 2 of
10 * the License, or (at your option) any later version.
11 */
12
13 #include <linux/clk-provider.h>
14 #include <linux/regmap.h>
15
16 #include "sun4i_tcon.h"
17 #include "sun4i_dotclock.h"
18
19 struct sun4i_dclk {
20 struct clk_hw hw;
21 struct regmap *regmap;
22 };
23
hw_to_dclk(struct clk_hw * hw)24 static inline struct sun4i_dclk *hw_to_dclk(struct clk_hw *hw)
25 {
26 return container_of(hw, struct sun4i_dclk, hw);
27 }
28
sun4i_dclk_disable(struct clk_hw * hw)29 static void sun4i_dclk_disable(struct clk_hw *hw)
30 {
31 struct sun4i_dclk *dclk = hw_to_dclk(hw);
32
33 regmap_update_bits(dclk->regmap, SUN4I_TCON0_DCLK_REG,
34 BIT(SUN4I_TCON0_DCLK_GATE_BIT), 0);
35 }
36
sun4i_dclk_enable(struct clk_hw * hw)37 static int sun4i_dclk_enable(struct clk_hw *hw)
38 {
39 struct sun4i_dclk *dclk = hw_to_dclk(hw);
40
41 return regmap_update_bits(dclk->regmap, SUN4I_TCON0_DCLK_REG,
42 BIT(SUN4I_TCON0_DCLK_GATE_BIT),
43 BIT(SUN4I_TCON0_DCLK_GATE_BIT));
44 }
45
sun4i_dclk_is_enabled(struct clk_hw * hw)46 static int sun4i_dclk_is_enabled(struct clk_hw *hw)
47 {
48 struct sun4i_dclk *dclk = hw_to_dclk(hw);
49 u32 val;
50
51 regmap_read(dclk->regmap, SUN4I_TCON0_DCLK_REG, &val);
52
53 return val & BIT(SUN4I_TCON0_DCLK_GATE_BIT);
54 }
55
sun4i_dclk_recalc_rate(struct clk_hw * hw,unsigned long parent_rate)56 static unsigned long sun4i_dclk_recalc_rate(struct clk_hw *hw,
57 unsigned long parent_rate)
58 {
59 struct sun4i_dclk *dclk = hw_to_dclk(hw);
60 u32 val;
61
62 regmap_read(dclk->regmap, SUN4I_TCON0_DCLK_REG, &val);
63
64 val >>= SUN4I_TCON0_DCLK_DIV_SHIFT;
65 val &= (1 << SUN4I_TCON0_DCLK_DIV_WIDTH) - 1;
66
67 if (!val)
68 val = 1;
69
70 return parent_rate / val;
71 }
72
sun4i_dclk_round_rate(struct clk_hw * hw,unsigned long rate,unsigned long * parent_rate)73 static long sun4i_dclk_round_rate(struct clk_hw *hw, unsigned long rate,
74 unsigned long *parent_rate)
75 {
76 unsigned long best_parent = 0;
77 u8 best_div = 1;
78 int i;
79
80 for (i = 6; i <= 127; i++) {
81 unsigned long ideal = rate * i;
82 unsigned long rounded;
83
84 rounded = clk_hw_round_rate(clk_hw_get_parent(hw),
85 ideal);
86
87 if (rounded == ideal) {
88 best_parent = rounded;
89 best_div = i;
90 goto out;
91 }
92
93 if (abs(rate - rounded / i) <
94 abs(rate - best_parent / best_div)) {
95 best_parent = rounded;
96 best_div = i;
97 }
98 }
99
100 out:
101 *parent_rate = best_parent;
102
103 return best_parent / best_div;
104 }
105
sun4i_dclk_set_rate(struct clk_hw * hw,unsigned long rate,unsigned long parent_rate)106 static int sun4i_dclk_set_rate(struct clk_hw *hw, unsigned long rate,
107 unsigned long parent_rate)
108 {
109 struct sun4i_dclk *dclk = hw_to_dclk(hw);
110 u8 div = parent_rate / rate;
111
112 return regmap_update_bits(dclk->regmap, SUN4I_TCON0_DCLK_REG,
113 GENMASK(6, 0), div);
114 }
115
sun4i_dclk_get_phase(struct clk_hw * hw)116 static int sun4i_dclk_get_phase(struct clk_hw *hw)
117 {
118 struct sun4i_dclk *dclk = hw_to_dclk(hw);
119 u32 val;
120
121 regmap_read(dclk->regmap, SUN4I_TCON0_IO_POL_REG, &val);
122
123 val >>= 28;
124 val &= 3;
125
126 return val * 120;
127 }
128
sun4i_dclk_set_phase(struct clk_hw * hw,int degrees)129 static int sun4i_dclk_set_phase(struct clk_hw *hw, int degrees)
130 {
131 struct sun4i_dclk *dclk = hw_to_dclk(hw);
132 u32 val = degrees / 120;
133
134 val <<= 28;
135
136 regmap_update_bits(dclk->regmap, SUN4I_TCON0_IO_POL_REG,
137 GENMASK(29, 28),
138 val);
139
140 return 0;
141 }
142
143 static const struct clk_ops sun4i_dclk_ops = {
144 .disable = sun4i_dclk_disable,
145 .enable = sun4i_dclk_enable,
146 .is_enabled = sun4i_dclk_is_enabled,
147
148 .recalc_rate = sun4i_dclk_recalc_rate,
149 .round_rate = sun4i_dclk_round_rate,
150 .set_rate = sun4i_dclk_set_rate,
151
152 .get_phase = sun4i_dclk_get_phase,
153 .set_phase = sun4i_dclk_set_phase,
154 };
155
sun4i_dclk_create(struct device * dev,struct sun4i_tcon * tcon)156 int sun4i_dclk_create(struct device *dev, struct sun4i_tcon *tcon)
157 {
158 const char *clk_name, *parent_name;
159 struct clk_init_data init;
160 struct sun4i_dclk *dclk;
161 int ret;
162
163 parent_name = __clk_get_name(tcon->sclk0);
164 ret = of_property_read_string_index(dev->of_node,
165 "clock-output-names", 0,
166 &clk_name);
167 if (ret)
168 return ret;
169
170 dclk = devm_kzalloc(dev, sizeof(*dclk), GFP_KERNEL);
171 if (!dclk)
172 return -ENOMEM;
173
174 init.name = clk_name;
175 init.ops = &sun4i_dclk_ops;
176 init.parent_names = &parent_name;
177 init.num_parents = 1;
178 init.flags = CLK_SET_RATE_PARENT;
179
180 dclk->regmap = tcon->regs;
181 dclk->hw.init = &init;
182
183 tcon->dclk = clk_register(dev, &dclk->hw);
184 if (IS_ERR(tcon->dclk))
185 return PTR_ERR(tcon->dclk);
186
187 return 0;
188 }
189 EXPORT_SYMBOL(sun4i_dclk_create);
190
sun4i_dclk_free(struct sun4i_tcon * tcon)191 int sun4i_dclk_free(struct sun4i_tcon *tcon)
192 {
193 clk_unregister(tcon->dclk);
194 return 0;
195 }
196 EXPORT_SYMBOL(sun4i_dclk_free);
197