1 /*
2 * Copyright (C) 2012-2014 Mentor Graphics Inc.
3 * Copyright (C) 2005-2009 Freescale Semiconductor, Inc.
4 *
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms of the GNU General Public License as published by the
7 * Free Software Foundation; either version 2 of the License, or (at your
8 * option) any later version.
9 *
10 * This program is distributed in the hope that it will be useful, but
11 * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
12 * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
13 * for more details.
14 */
15 #include <linux/export.h>
16 #include <linux/module.h>
17 #include <linux/types.h>
18 #include <linux/errno.h>
19 #include <linux/delay.h>
20 #include <linux/io.h>
21 #include <linux/err.h>
22 #include <linux/platform_device.h>
23 #include <linux/videodev2.h>
24 #include <uapi/linux/v4l2-mediabus.h>
25 #include <linux/clk.h>
26 #include <linux/clk-provider.h>
27 #include <linux/clkdev.h>
28
29 #include "ipu-prv.h"
30
31 struct ipu_csi {
32 void __iomem *base;
33 int id;
34 u32 module;
35 struct clk *clk_ipu; /* IPU bus clock */
36 spinlock_t lock;
37 bool inuse;
38 struct ipu_soc *ipu;
39 };
40
41 /* CSI Register Offsets */
42 #define CSI_SENS_CONF 0x0000
43 #define CSI_SENS_FRM_SIZE 0x0004
44 #define CSI_ACT_FRM_SIZE 0x0008
45 #define CSI_OUT_FRM_CTRL 0x000c
46 #define CSI_TST_CTRL 0x0010
47 #define CSI_CCIR_CODE_1 0x0014
48 #define CSI_CCIR_CODE_2 0x0018
49 #define CSI_CCIR_CODE_3 0x001c
50 #define CSI_MIPI_DI 0x0020
51 #define CSI_SKIP 0x0024
52 #define CSI_CPD_CTRL 0x0028
53 #define CSI_CPD_RC(n) (0x002c + ((n)*4))
54 #define CSI_CPD_RS(n) (0x004c + ((n)*4))
55 #define CSI_CPD_GRC(n) (0x005c + ((n)*4))
56 #define CSI_CPD_GRS(n) (0x007c + ((n)*4))
57 #define CSI_CPD_GBC(n) (0x008c + ((n)*4))
58 #define CSI_CPD_GBS(n) (0x00Ac + ((n)*4))
59 #define CSI_CPD_BC(n) (0x00Bc + ((n)*4))
60 #define CSI_CPD_BS(n) (0x00Dc + ((n)*4))
61 #define CSI_CPD_OFFSET1 0x00ec
62 #define CSI_CPD_OFFSET2 0x00f0
63
64 /* CSI Register Fields */
65 #define CSI_SENS_CONF_DATA_FMT_SHIFT 8
66 #define CSI_SENS_CONF_DATA_FMT_MASK 0x00000700
67 #define CSI_SENS_CONF_DATA_FMT_RGB_YUV444 0L
68 #define CSI_SENS_CONF_DATA_FMT_YUV422_YUYV 1L
69 #define CSI_SENS_CONF_DATA_FMT_YUV422_UYVY 2L
70 #define CSI_SENS_CONF_DATA_FMT_BAYER 3L
71 #define CSI_SENS_CONF_DATA_FMT_RGB565 4L
72 #define CSI_SENS_CONF_DATA_FMT_RGB555 5L
73 #define CSI_SENS_CONF_DATA_FMT_RGB444 6L
74 #define CSI_SENS_CONF_DATA_FMT_JPEG 7L
75
76 #define CSI_SENS_CONF_VSYNC_POL_SHIFT 0
77 #define CSI_SENS_CONF_HSYNC_POL_SHIFT 1
78 #define CSI_SENS_CONF_DATA_POL_SHIFT 2
79 #define CSI_SENS_CONF_PIX_CLK_POL_SHIFT 3
80 #define CSI_SENS_CONF_SENS_PRTCL_MASK 0x00000070
81 #define CSI_SENS_CONF_SENS_PRTCL_SHIFT 4
82 #define CSI_SENS_CONF_PACK_TIGHT_SHIFT 7
83 #define CSI_SENS_CONF_DATA_WIDTH_SHIFT 11
84 #define CSI_SENS_CONF_EXT_VSYNC_SHIFT 15
85 #define CSI_SENS_CONF_DIVRATIO_SHIFT 16
86
87 #define CSI_SENS_CONF_DIVRATIO_MASK 0x00ff0000
88 #define CSI_SENS_CONF_DATA_DEST_SHIFT 24
89 #define CSI_SENS_CONF_DATA_DEST_MASK 0x07000000
90 #define CSI_SENS_CONF_JPEG8_EN_SHIFT 27
91 #define CSI_SENS_CONF_JPEG_EN_SHIFT 28
92 #define CSI_SENS_CONF_FORCE_EOF_SHIFT 29
93 #define CSI_SENS_CONF_DATA_EN_POL_SHIFT 31
94
95 #define CSI_DATA_DEST_IC 2
96 #define CSI_DATA_DEST_IDMAC 4
97
98 #define CSI_CCIR_ERR_DET_EN 0x01000000
99 #define CSI_HORI_DOWNSIZE_EN 0x80000000
100 #define CSI_VERT_DOWNSIZE_EN 0x40000000
101 #define CSI_TEST_GEN_MODE_EN 0x01000000
102
103 #define CSI_HSC_MASK 0x1fff0000
104 #define CSI_HSC_SHIFT 16
105 #define CSI_VSC_MASK 0x00000fff
106 #define CSI_VSC_SHIFT 0
107
108 #define CSI_TEST_GEN_R_MASK 0x000000ff
109 #define CSI_TEST_GEN_R_SHIFT 0
110 #define CSI_TEST_GEN_G_MASK 0x0000ff00
111 #define CSI_TEST_GEN_G_SHIFT 8
112 #define CSI_TEST_GEN_B_MASK 0x00ff0000
113 #define CSI_TEST_GEN_B_SHIFT 16
114
115 #define CSI_MAX_RATIO_SKIP_SMFC_MASK 0x00000007
116 #define CSI_MAX_RATIO_SKIP_SMFC_SHIFT 0
117 #define CSI_SKIP_SMFC_MASK 0x000000f8
118 #define CSI_SKIP_SMFC_SHIFT 3
119 #define CSI_ID_2_SKIP_MASK 0x00000300
120 #define CSI_ID_2_SKIP_SHIFT 8
121
122 #define CSI_COLOR_FIRST_ROW_MASK 0x00000002
123 #define CSI_COLOR_FIRST_COMP_MASK 0x00000001
124
125 /* MIPI CSI-2 data types */
126 #define MIPI_DT_YUV420 0x18 /* YYY.../UYVY.... */
127 #define MIPI_DT_YUV420_LEGACY 0x1a /* UYY.../VYY... */
128 #define MIPI_DT_YUV422 0x1e /* UYVY... */
129 #define MIPI_DT_RGB444 0x20
130 #define MIPI_DT_RGB555 0x21
131 #define MIPI_DT_RGB565 0x22
132 #define MIPI_DT_RGB666 0x23
133 #define MIPI_DT_RGB888 0x24
134 #define MIPI_DT_RAW6 0x28
135 #define MIPI_DT_RAW7 0x29
136 #define MIPI_DT_RAW8 0x2a
137 #define MIPI_DT_RAW10 0x2b
138 #define MIPI_DT_RAW12 0x2c
139 #define MIPI_DT_RAW14 0x2d
140
141 /*
142 * Bitfield of CSI bus signal polarities and modes.
143 */
144 struct ipu_csi_bus_config {
145 unsigned data_width:4;
146 unsigned clk_mode:3;
147 unsigned ext_vsync:1;
148 unsigned vsync_pol:1;
149 unsigned hsync_pol:1;
150 unsigned pixclk_pol:1;
151 unsigned data_pol:1;
152 unsigned sens_clksrc:1;
153 unsigned pack_tight:1;
154 unsigned force_eof:1;
155 unsigned data_en_pol:1;
156
157 unsigned data_fmt;
158 unsigned mipi_dt;
159 };
160
161 /*
162 * Enumeration of CSI data bus widths.
163 */
164 enum ipu_csi_data_width {
165 IPU_CSI_DATA_WIDTH_4 = 0,
166 IPU_CSI_DATA_WIDTH_8 = 1,
167 IPU_CSI_DATA_WIDTH_10 = 3,
168 IPU_CSI_DATA_WIDTH_12 = 5,
169 IPU_CSI_DATA_WIDTH_16 = 9,
170 };
171
172 /*
173 * Enumeration of CSI clock modes.
174 */
175 enum ipu_csi_clk_mode {
176 IPU_CSI_CLK_MODE_GATED_CLK,
177 IPU_CSI_CLK_MODE_NONGATED_CLK,
178 IPU_CSI_CLK_MODE_CCIR656_PROGRESSIVE,
179 IPU_CSI_CLK_MODE_CCIR656_INTERLACED,
180 IPU_CSI_CLK_MODE_CCIR1120_PROGRESSIVE_DDR,
181 IPU_CSI_CLK_MODE_CCIR1120_PROGRESSIVE_SDR,
182 IPU_CSI_CLK_MODE_CCIR1120_INTERLACED_DDR,
183 IPU_CSI_CLK_MODE_CCIR1120_INTERLACED_SDR,
184 };
185
ipu_csi_read(struct ipu_csi * csi,unsigned offset)186 static inline u32 ipu_csi_read(struct ipu_csi *csi, unsigned offset)
187 {
188 return readl(csi->base + offset);
189 }
190
ipu_csi_write(struct ipu_csi * csi,u32 value,unsigned offset)191 static inline void ipu_csi_write(struct ipu_csi *csi, u32 value,
192 unsigned offset)
193 {
194 writel(value, csi->base + offset);
195 }
196
197 /*
198 * Set mclk division ratio for generating test mode mclk. Only used
199 * for test generator.
200 */
ipu_csi_set_testgen_mclk(struct ipu_csi * csi,u32 pixel_clk,u32 ipu_clk)201 static int ipu_csi_set_testgen_mclk(struct ipu_csi *csi, u32 pixel_clk,
202 u32 ipu_clk)
203 {
204 u32 temp;
205 int div_ratio;
206
207 div_ratio = (ipu_clk / pixel_clk) - 1;
208
209 if (div_ratio > 0xFF || div_ratio < 0) {
210 dev_err(csi->ipu->dev,
211 "value of pixel_clk extends normal range\n");
212 return -EINVAL;
213 }
214
215 temp = ipu_csi_read(csi, CSI_SENS_CONF);
216 temp &= ~CSI_SENS_CONF_DIVRATIO_MASK;
217 ipu_csi_write(csi, temp | (div_ratio << CSI_SENS_CONF_DIVRATIO_SHIFT),
218 CSI_SENS_CONF);
219
220 return 0;
221 }
222
223 /*
224 * Find the CSI data format and data width for the given V4L2 media
225 * bus pixel format code.
226 */
mbus_code_to_bus_cfg(struct ipu_csi_bus_config * cfg,u32 mbus_code)227 static int mbus_code_to_bus_cfg(struct ipu_csi_bus_config *cfg, u32 mbus_code)
228 {
229 switch (mbus_code) {
230 case MEDIA_BUS_FMT_BGR565_2X8_BE:
231 case MEDIA_BUS_FMT_BGR565_2X8_LE:
232 case MEDIA_BUS_FMT_RGB565_2X8_BE:
233 case MEDIA_BUS_FMT_RGB565_2X8_LE:
234 cfg->data_fmt = CSI_SENS_CONF_DATA_FMT_RGB565;
235 cfg->mipi_dt = MIPI_DT_RGB565;
236 cfg->data_width = IPU_CSI_DATA_WIDTH_8;
237 break;
238 case MEDIA_BUS_FMT_RGB444_2X8_PADHI_BE:
239 case MEDIA_BUS_FMT_RGB444_2X8_PADHI_LE:
240 cfg->data_fmt = CSI_SENS_CONF_DATA_FMT_RGB444;
241 cfg->mipi_dt = MIPI_DT_RGB444;
242 cfg->data_width = IPU_CSI_DATA_WIDTH_8;
243 break;
244 case MEDIA_BUS_FMT_RGB555_2X8_PADHI_BE:
245 case MEDIA_BUS_FMT_RGB555_2X8_PADHI_LE:
246 cfg->data_fmt = CSI_SENS_CONF_DATA_FMT_RGB555;
247 cfg->mipi_dt = MIPI_DT_RGB555;
248 cfg->data_width = IPU_CSI_DATA_WIDTH_8;
249 break;
250 case MEDIA_BUS_FMT_UYVY8_2X8:
251 cfg->data_fmt = CSI_SENS_CONF_DATA_FMT_YUV422_UYVY;
252 cfg->mipi_dt = MIPI_DT_YUV422;
253 cfg->data_width = IPU_CSI_DATA_WIDTH_8;
254 break;
255 case MEDIA_BUS_FMT_YUYV8_2X8:
256 cfg->data_fmt = CSI_SENS_CONF_DATA_FMT_YUV422_YUYV;
257 cfg->mipi_dt = MIPI_DT_YUV422;
258 cfg->data_width = IPU_CSI_DATA_WIDTH_8;
259 break;
260 case MEDIA_BUS_FMT_UYVY8_1X16:
261 case MEDIA_BUS_FMT_YUYV8_1X16:
262 cfg->data_fmt = CSI_SENS_CONF_DATA_FMT_BAYER;
263 cfg->mipi_dt = MIPI_DT_YUV422;
264 cfg->data_width = IPU_CSI_DATA_WIDTH_16;
265 break;
266 case MEDIA_BUS_FMT_SBGGR8_1X8:
267 case MEDIA_BUS_FMT_SGBRG8_1X8:
268 case MEDIA_BUS_FMT_SGRBG8_1X8:
269 case MEDIA_BUS_FMT_SRGGB8_1X8:
270 case MEDIA_BUS_FMT_Y8_1X8:
271 cfg->data_fmt = CSI_SENS_CONF_DATA_FMT_BAYER;
272 cfg->mipi_dt = MIPI_DT_RAW8;
273 cfg->data_width = IPU_CSI_DATA_WIDTH_8;
274 break;
275 case MEDIA_BUS_FMT_SBGGR10_DPCM8_1X8:
276 case MEDIA_BUS_FMT_SGBRG10_DPCM8_1X8:
277 case MEDIA_BUS_FMT_SGRBG10_DPCM8_1X8:
278 case MEDIA_BUS_FMT_SRGGB10_DPCM8_1X8:
279 case MEDIA_BUS_FMT_SBGGR10_2X8_PADHI_BE:
280 case MEDIA_BUS_FMT_SBGGR10_2X8_PADHI_LE:
281 case MEDIA_BUS_FMT_SBGGR10_2X8_PADLO_BE:
282 case MEDIA_BUS_FMT_SBGGR10_2X8_PADLO_LE:
283 cfg->data_fmt = CSI_SENS_CONF_DATA_FMT_BAYER;
284 cfg->mipi_dt = MIPI_DT_RAW10;
285 cfg->data_width = IPU_CSI_DATA_WIDTH_8;
286 break;
287 case MEDIA_BUS_FMT_SBGGR10_1X10:
288 case MEDIA_BUS_FMT_SGBRG10_1X10:
289 case MEDIA_BUS_FMT_SGRBG10_1X10:
290 case MEDIA_BUS_FMT_SRGGB10_1X10:
291 cfg->data_fmt = CSI_SENS_CONF_DATA_FMT_BAYER;
292 cfg->mipi_dt = MIPI_DT_RAW10;
293 cfg->data_width = IPU_CSI_DATA_WIDTH_10;
294 break;
295 case MEDIA_BUS_FMT_SBGGR12_1X12:
296 case MEDIA_BUS_FMT_SGBRG12_1X12:
297 case MEDIA_BUS_FMT_SGRBG12_1X12:
298 case MEDIA_BUS_FMT_SRGGB12_1X12:
299 cfg->data_fmt = CSI_SENS_CONF_DATA_FMT_BAYER;
300 cfg->mipi_dt = MIPI_DT_RAW12;
301 cfg->data_width = IPU_CSI_DATA_WIDTH_12;
302 break;
303 case MEDIA_BUS_FMT_JPEG_1X8:
304 /* TODO */
305 cfg->data_fmt = CSI_SENS_CONF_DATA_FMT_JPEG;
306 cfg->mipi_dt = MIPI_DT_RAW8;
307 cfg->data_width = IPU_CSI_DATA_WIDTH_8;
308 break;
309 default:
310 return -EINVAL;
311 }
312
313 return 0;
314 }
315
316 /*
317 * Fill a CSI bus config struct from mbus_config and mbus_framefmt.
318 */
fill_csi_bus_cfg(struct ipu_csi_bus_config * csicfg,struct v4l2_mbus_config * mbus_cfg,struct v4l2_mbus_framefmt * mbus_fmt)319 static int fill_csi_bus_cfg(struct ipu_csi_bus_config *csicfg,
320 struct v4l2_mbus_config *mbus_cfg,
321 struct v4l2_mbus_framefmt *mbus_fmt)
322 {
323 int ret;
324
325 memset(csicfg, 0, sizeof(*csicfg));
326
327 ret = mbus_code_to_bus_cfg(csicfg, mbus_fmt->code);
328 if (ret < 0)
329 return ret;
330
331 switch (mbus_cfg->type) {
332 case V4L2_MBUS_PARALLEL:
333 csicfg->ext_vsync = 1;
334 csicfg->vsync_pol = (mbus_cfg->flags &
335 V4L2_MBUS_VSYNC_ACTIVE_LOW) ? 1 : 0;
336 csicfg->hsync_pol = (mbus_cfg->flags &
337 V4L2_MBUS_HSYNC_ACTIVE_LOW) ? 1 : 0;
338 csicfg->pixclk_pol = (mbus_cfg->flags &
339 V4L2_MBUS_PCLK_SAMPLE_FALLING) ? 1 : 0;
340 csicfg->clk_mode = IPU_CSI_CLK_MODE_GATED_CLK;
341 break;
342 case V4L2_MBUS_BT656:
343 csicfg->ext_vsync = 0;
344 if (V4L2_FIELD_HAS_BOTH(mbus_fmt->field))
345 csicfg->clk_mode = IPU_CSI_CLK_MODE_CCIR656_INTERLACED;
346 else
347 csicfg->clk_mode = IPU_CSI_CLK_MODE_CCIR656_PROGRESSIVE;
348 break;
349 case V4L2_MBUS_CSI2:
350 /*
351 * MIPI CSI-2 requires non gated clock mode, all other
352 * parameters are not applicable for MIPI CSI-2 bus.
353 */
354 csicfg->clk_mode = IPU_CSI_CLK_MODE_NONGATED_CLK;
355 break;
356 default:
357 /* will never get here, keep compiler quiet */
358 break;
359 }
360
361 return 0;
362 }
363
ipu_csi_init_interface(struct ipu_csi * csi,struct v4l2_mbus_config * mbus_cfg,struct v4l2_mbus_framefmt * mbus_fmt)364 int ipu_csi_init_interface(struct ipu_csi *csi,
365 struct v4l2_mbus_config *mbus_cfg,
366 struct v4l2_mbus_framefmt *mbus_fmt)
367 {
368 struct ipu_csi_bus_config cfg;
369 unsigned long flags;
370 u32 width, height, data = 0;
371 int ret;
372
373 ret = fill_csi_bus_cfg(&cfg, mbus_cfg, mbus_fmt);
374 if (ret < 0)
375 return ret;
376
377 /* set default sensor frame width and height */
378 width = mbus_fmt->width;
379 height = mbus_fmt->height;
380
381 /* Set the CSI_SENS_CONF register remaining fields */
382 data |= cfg.data_width << CSI_SENS_CONF_DATA_WIDTH_SHIFT |
383 cfg.data_fmt << CSI_SENS_CONF_DATA_FMT_SHIFT |
384 cfg.data_pol << CSI_SENS_CONF_DATA_POL_SHIFT |
385 cfg.vsync_pol << CSI_SENS_CONF_VSYNC_POL_SHIFT |
386 cfg.hsync_pol << CSI_SENS_CONF_HSYNC_POL_SHIFT |
387 cfg.pixclk_pol << CSI_SENS_CONF_PIX_CLK_POL_SHIFT |
388 cfg.ext_vsync << CSI_SENS_CONF_EXT_VSYNC_SHIFT |
389 cfg.clk_mode << CSI_SENS_CONF_SENS_PRTCL_SHIFT |
390 cfg.pack_tight << CSI_SENS_CONF_PACK_TIGHT_SHIFT |
391 cfg.force_eof << CSI_SENS_CONF_FORCE_EOF_SHIFT |
392 cfg.data_en_pol << CSI_SENS_CONF_DATA_EN_POL_SHIFT;
393
394 spin_lock_irqsave(&csi->lock, flags);
395
396 ipu_csi_write(csi, data, CSI_SENS_CONF);
397
398 /* Set CCIR registers */
399
400 switch (cfg.clk_mode) {
401 case IPU_CSI_CLK_MODE_CCIR656_PROGRESSIVE:
402 ipu_csi_write(csi, 0x40030, CSI_CCIR_CODE_1);
403 ipu_csi_write(csi, 0xFF0000, CSI_CCIR_CODE_3);
404 break;
405 case IPU_CSI_CLK_MODE_CCIR656_INTERLACED:
406 if (mbus_fmt->width == 720 && mbus_fmt->height == 576) {
407 /*
408 * PAL case
409 *
410 * Field0BlankEnd = 0x6, Field0BlankStart = 0x2,
411 * Field0ActiveEnd = 0x4, Field0ActiveStart = 0
412 * Field1BlankEnd = 0x7, Field1BlankStart = 0x3,
413 * Field1ActiveEnd = 0x5, Field1ActiveStart = 0x1
414 */
415 height = 625; /* framelines for PAL */
416
417 ipu_csi_write(csi, 0x40596 | CSI_CCIR_ERR_DET_EN,
418 CSI_CCIR_CODE_1);
419 ipu_csi_write(csi, 0xD07DF, CSI_CCIR_CODE_2);
420 ipu_csi_write(csi, 0xFF0000, CSI_CCIR_CODE_3);
421 } else if (mbus_fmt->width == 720 && mbus_fmt->height == 480) {
422 /*
423 * NTSC case
424 *
425 * Field0BlankEnd = 0x7, Field0BlankStart = 0x3,
426 * Field0ActiveEnd = 0x5, Field0ActiveStart = 0x1
427 * Field1BlankEnd = 0x6, Field1BlankStart = 0x2,
428 * Field1ActiveEnd = 0x4, Field1ActiveStart = 0
429 */
430 height = 525; /* framelines for NTSC */
431
432 ipu_csi_write(csi, 0xD07DF | CSI_CCIR_ERR_DET_EN,
433 CSI_CCIR_CODE_1);
434 ipu_csi_write(csi, 0x40596, CSI_CCIR_CODE_2);
435 ipu_csi_write(csi, 0xFF0000, CSI_CCIR_CODE_3);
436 } else {
437 dev_err(csi->ipu->dev,
438 "Unsupported CCIR656 interlaced video mode\n");
439 spin_unlock_irqrestore(&csi->lock, flags);
440 return -EINVAL;
441 }
442 break;
443 case IPU_CSI_CLK_MODE_CCIR1120_PROGRESSIVE_DDR:
444 case IPU_CSI_CLK_MODE_CCIR1120_PROGRESSIVE_SDR:
445 case IPU_CSI_CLK_MODE_CCIR1120_INTERLACED_DDR:
446 case IPU_CSI_CLK_MODE_CCIR1120_INTERLACED_SDR:
447 ipu_csi_write(csi, 0x40030 | CSI_CCIR_ERR_DET_EN,
448 CSI_CCIR_CODE_1);
449 ipu_csi_write(csi, 0xFF0000, CSI_CCIR_CODE_3);
450 break;
451 case IPU_CSI_CLK_MODE_GATED_CLK:
452 case IPU_CSI_CLK_MODE_NONGATED_CLK:
453 ipu_csi_write(csi, 0, CSI_CCIR_CODE_1);
454 break;
455 }
456
457 /* Setup sensor frame size */
458 ipu_csi_write(csi, (width - 1) | ((height - 1) << 16),
459 CSI_SENS_FRM_SIZE);
460
461 dev_dbg(csi->ipu->dev, "CSI_SENS_CONF = 0x%08X\n",
462 ipu_csi_read(csi, CSI_SENS_CONF));
463 dev_dbg(csi->ipu->dev, "CSI_ACT_FRM_SIZE = 0x%08X\n",
464 ipu_csi_read(csi, CSI_ACT_FRM_SIZE));
465
466 spin_unlock_irqrestore(&csi->lock, flags);
467
468 return 0;
469 }
470 EXPORT_SYMBOL_GPL(ipu_csi_init_interface);
471
ipu_csi_is_interlaced(struct ipu_csi * csi)472 bool ipu_csi_is_interlaced(struct ipu_csi *csi)
473 {
474 unsigned long flags;
475 u32 sensor_protocol;
476
477 spin_lock_irqsave(&csi->lock, flags);
478 sensor_protocol =
479 (ipu_csi_read(csi, CSI_SENS_CONF) &
480 CSI_SENS_CONF_SENS_PRTCL_MASK) >>
481 CSI_SENS_CONF_SENS_PRTCL_SHIFT;
482 spin_unlock_irqrestore(&csi->lock, flags);
483
484 switch (sensor_protocol) {
485 case IPU_CSI_CLK_MODE_GATED_CLK:
486 case IPU_CSI_CLK_MODE_NONGATED_CLK:
487 case IPU_CSI_CLK_MODE_CCIR656_PROGRESSIVE:
488 case IPU_CSI_CLK_MODE_CCIR1120_PROGRESSIVE_DDR:
489 case IPU_CSI_CLK_MODE_CCIR1120_PROGRESSIVE_SDR:
490 return false;
491 case IPU_CSI_CLK_MODE_CCIR656_INTERLACED:
492 case IPU_CSI_CLK_MODE_CCIR1120_INTERLACED_DDR:
493 case IPU_CSI_CLK_MODE_CCIR1120_INTERLACED_SDR:
494 return true;
495 default:
496 dev_err(csi->ipu->dev,
497 "CSI %d sensor protocol unsupported\n", csi->id);
498 return false;
499 }
500 }
501 EXPORT_SYMBOL_GPL(ipu_csi_is_interlaced);
502
ipu_csi_get_window(struct ipu_csi * csi,struct v4l2_rect * w)503 void ipu_csi_get_window(struct ipu_csi *csi, struct v4l2_rect *w)
504 {
505 unsigned long flags;
506 u32 reg;
507
508 spin_lock_irqsave(&csi->lock, flags);
509
510 reg = ipu_csi_read(csi, CSI_ACT_FRM_SIZE);
511 w->width = (reg & 0xFFFF) + 1;
512 w->height = (reg >> 16 & 0xFFFF) + 1;
513
514 reg = ipu_csi_read(csi, CSI_OUT_FRM_CTRL);
515 w->left = (reg & CSI_HSC_MASK) >> CSI_HSC_SHIFT;
516 w->top = (reg & CSI_VSC_MASK) >> CSI_VSC_SHIFT;
517
518 spin_unlock_irqrestore(&csi->lock, flags);
519 }
520 EXPORT_SYMBOL_GPL(ipu_csi_get_window);
521
ipu_csi_set_window(struct ipu_csi * csi,struct v4l2_rect * w)522 void ipu_csi_set_window(struct ipu_csi *csi, struct v4l2_rect *w)
523 {
524 unsigned long flags;
525 u32 reg;
526
527 spin_lock_irqsave(&csi->lock, flags);
528
529 ipu_csi_write(csi, (w->width - 1) | ((w->height - 1) << 16),
530 CSI_ACT_FRM_SIZE);
531
532 reg = ipu_csi_read(csi, CSI_OUT_FRM_CTRL);
533 reg &= ~(CSI_HSC_MASK | CSI_VSC_MASK);
534 reg |= ((w->top << CSI_VSC_SHIFT) | (w->left << CSI_HSC_SHIFT));
535 ipu_csi_write(csi, reg, CSI_OUT_FRM_CTRL);
536
537 spin_unlock_irqrestore(&csi->lock, flags);
538 }
539 EXPORT_SYMBOL_GPL(ipu_csi_set_window);
540
ipu_csi_set_downsize(struct ipu_csi * csi,bool horiz,bool vert)541 void ipu_csi_set_downsize(struct ipu_csi *csi, bool horiz, bool vert)
542 {
543 unsigned long flags;
544 u32 reg;
545
546 spin_lock_irqsave(&csi->lock, flags);
547
548 reg = ipu_csi_read(csi, CSI_OUT_FRM_CTRL);
549 reg &= ~(CSI_HORI_DOWNSIZE_EN | CSI_VERT_DOWNSIZE_EN);
550 reg |= (horiz ? CSI_HORI_DOWNSIZE_EN : 0) |
551 (vert ? CSI_VERT_DOWNSIZE_EN : 0);
552 ipu_csi_write(csi, reg, CSI_OUT_FRM_CTRL);
553
554 spin_unlock_irqrestore(&csi->lock, flags);
555 }
556 EXPORT_SYMBOL_GPL(ipu_csi_set_downsize);
557
ipu_csi_set_test_generator(struct ipu_csi * csi,bool active,u32 r_value,u32 g_value,u32 b_value,u32 pix_clk)558 void ipu_csi_set_test_generator(struct ipu_csi *csi, bool active,
559 u32 r_value, u32 g_value, u32 b_value,
560 u32 pix_clk)
561 {
562 unsigned long flags;
563 u32 ipu_clk = clk_get_rate(csi->clk_ipu);
564 u32 temp;
565
566 spin_lock_irqsave(&csi->lock, flags);
567
568 temp = ipu_csi_read(csi, CSI_TST_CTRL);
569
570 if (!active) {
571 temp &= ~CSI_TEST_GEN_MODE_EN;
572 ipu_csi_write(csi, temp, CSI_TST_CTRL);
573 } else {
574 /* Set sensb_mclk div_ratio */
575 ipu_csi_set_testgen_mclk(csi, pix_clk, ipu_clk);
576
577 temp &= ~(CSI_TEST_GEN_R_MASK | CSI_TEST_GEN_G_MASK |
578 CSI_TEST_GEN_B_MASK);
579 temp |= CSI_TEST_GEN_MODE_EN;
580 temp |= (r_value << CSI_TEST_GEN_R_SHIFT) |
581 (g_value << CSI_TEST_GEN_G_SHIFT) |
582 (b_value << CSI_TEST_GEN_B_SHIFT);
583 ipu_csi_write(csi, temp, CSI_TST_CTRL);
584 }
585
586 spin_unlock_irqrestore(&csi->lock, flags);
587 }
588 EXPORT_SYMBOL_GPL(ipu_csi_set_test_generator);
589
ipu_csi_set_mipi_datatype(struct ipu_csi * csi,u32 vc,struct v4l2_mbus_framefmt * mbus_fmt)590 int ipu_csi_set_mipi_datatype(struct ipu_csi *csi, u32 vc,
591 struct v4l2_mbus_framefmt *mbus_fmt)
592 {
593 struct ipu_csi_bus_config cfg;
594 unsigned long flags;
595 u32 temp;
596 int ret;
597
598 if (vc > 3)
599 return -EINVAL;
600
601 ret = mbus_code_to_bus_cfg(&cfg, mbus_fmt->code);
602 if (ret < 0)
603 return ret;
604
605 spin_lock_irqsave(&csi->lock, flags);
606
607 temp = ipu_csi_read(csi, CSI_MIPI_DI);
608 temp &= ~(0xff << (vc * 8));
609 temp |= (cfg.mipi_dt << (vc * 8));
610 ipu_csi_write(csi, temp, CSI_MIPI_DI);
611
612 spin_unlock_irqrestore(&csi->lock, flags);
613
614 return 0;
615 }
616 EXPORT_SYMBOL_GPL(ipu_csi_set_mipi_datatype);
617
ipu_csi_set_skip_smfc(struct ipu_csi * csi,u32 skip,u32 max_ratio,u32 id)618 int ipu_csi_set_skip_smfc(struct ipu_csi *csi, u32 skip,
619 u32 max_ratio, u32 id)
620 {
621 unsigned long flags;
622 u32 temp;
623
624 if (max_ratio > 5 || id > 3)
625 return -EINVAL;
626
627 spin_lock_irqsave(&csi->lock, flags);
628
629 temp = ipu_csi_read(csi, CSI_SKIP);
630 temp &= ~(CSI_MAX_RATIO_SKIP_SMFC_MASK | CSI_ID_2_SKIP_MASK |
631 CSI_SKIP_SMFC_MASK);
632 temp |= (max_ratio << CSI_MAX_RATIO_SKIP_SMFC_SHIFT) |
633 (id << CSI_ID_2_SKIP_SHIFT) |
634 (skip << CSI_SKIP_SMFC_SHIFT);
635 ipu_csi_write(csi, temp, CSI_SKIP);
636
637 spin_unlock_irqrestore(&csi->lock, flags);
638
639 return 0;
640 }
641 EXPORT_SYMBOL_GPL(ipu_csi_set_skip_smfc);
642
ipu_csi_set_dest(struct ipu_csi * csi,enum ipu_csi_dest csi_dest)643 int ipu_csi_set_dest(struct ipu_csi *csi, enum ipu_csi_dest csi_dest)
644 {
645 unsigned long flags;
646 u32 csi_sens_conf, dest;
647
648 if (csi_dest == IPU_CSI_DEST_IDMAC)
649 dest = CSI_DATA_DEST_IDMAC;
650 else
651 dest = CSI_DATA_DEST_IC; /* IC or VDIC */
652
653 spin_lock_irqsave(&csi->lock, flags);
654
655 csi_sens_conf = ipu_csi_read(csi, CSI_SENS_CONF);
656 csi_sens_conf &= ~CSI_SENS_CONF_DATA_DEST_MASK;
657 csi_sens_conf |= (dest << CSI_SENS_CONF_DATA_DEST_SHIFT);
658 ipu_csi_write(csi, csi_sens_conf, CSI_SENS_CONF);
659
660 spin_unlock_irqrestore(&csi->lock, flags);
661
662 return 0;
663 }
664 EXPORT_SYMBOL_GPL(ipu_csi_set_dest);
665
ipu_csi_enable(struct ipu_csi * csi)666 int ipu_csi_enable(struct ipu_csi *csi)
667 {
668 ipu_module_enable(csi->ipu, csi->module);
669
670 return 0;
671 }
672 EXPORT_SYMBOL_GPL(ipu_csi_enable);
673
ipu_csi_disable(struct ipu_csi * csi)674 int ipu_csi_disable(struct ipu_csi *csi)
675 {
676 ipu_module_disable(csi->ipu, csi->module);
677
678 return 0;
679 }
680 EXPORT_SYMBOL_GPL(ipu_csi_disable);
681
ipu_csi_get(struct ipu_soc * ipu,int id)682 struct ipu_csi *ipu_csi_get(struct ipu_soc *ipu, int id)
683 {
684 unsigned long flags;
685 struct ipu_csi *csi, *ret;
686
687 if (id > 1)
688 return ERR_PTR(-EINVAL);
689
690 csi = ipu->csi_priv[id];
691 ret = csi;
692
693 spin_lock_irqsave(&csi->lock, flags);
694
695 if (csi->inuse) {
696 ret = ERR_PTR(-EBUSY);
697 goto unlock;
698 }
699
700 csi->inuse = true;
701 unlock:
702 spin_unlock_irqrestore(&csi->lock, flags);
703 return ret;
704 }
705 EXPORT_SYMBOL_GPL(ipu_csi_get);
706
ipu_csi_put(struct ipu_csi * csi)707 void ipu_csi_put(struct ipu_csi *csi)
708 {
709 unsigned long flags;
710
711 spin_lock_irqsave(&csi->lock, flags);
712 csi->inuse = false;
713 spin_unlock_irqrestore(&csi->lock, flags);
714 }
715 EXPORT_SYMBOL_GPL(ipu_csi_put);
716
ipu_csi_init(struct ipu_soc * ipu,struct device * dev,int id,unsigned long base,u32 module,struct clk * clk_ipu)717 int ipu_csi_init(struct ipu_soc *ipu, struct device *dev, int id,
718 unsigned long base, u32 module, struct clk *clk_ipu)
719 {
720 struct ipu_csi *csi;
721
722 if (id > 1)
723 return -ENODEV;
724
725 csi = devm_kzalloc(dev, sizeof(*csi), GFP_KERNEL);
726 if (!csi)
727 return -ENOMEM;
728
729 ipu->csi_priv[id] = csi;
730
731 spin_lock_init(&csi->lock);
732 csi->module = module;
733 csi->id = id;
734 csi->clk_ipu = clk_ipu;
735 csi->base = devm_ioremap(dev, base, PAGE_SIZE);
736 if (!csi->base)
737 return -ENOMEM;
738
739 dev_dbg(dev, "CSI%d base: 0x%08lx remapped to %p\n",
740 id, base, csi->base);
741 csi->ipu = ipu;
742
743 return 0;
744 }
745
ipu_csi_exit(struct ipu_soc * ipu,int id)746 void ipu_csi_exit(struct ipu_soc *ipu, int id)
747 {
748 }
749
ipu_csi_dump(struct ipu_csi * csi)750 void ipu_csi_dump(struct ipu_csi *csi)
751 {
752 dev_dbg(csi->ipu->dev, "CSI_SENS_CONF: %08x\n",
753 ipu_csi_read(csi, CSI_SENS_CONF));
754 dev_dbg(csi->ipu->dev, "CSI_SENS_FRM_SIZE: %08x\n",
755 ipu_csi_read(csi, CSI_SENS_FRM_SIZE));
756 dev_dbg(csi->ipu->dev, "CSI_ACT_FRM_SIZE: %08x\n",
757 ipu_csi_read(csi, CSI_ACT_FRM_SIZE));
758 dev_dbg(csi->ipu->dev, "CSI_OUT_FRM_CTRL: %08x\n",
759 ipu_csi_read(csi, CSI_OUT_FRM_CTRL));
760 dev_dbg(csi->ipu->dev, "CSI_TST_CTRL: %08x\n",
761 ipu_csi_read(csi, CSI_TST_CTRL));
762 dev_dbg(csi->ipu->dev, "CSI_CCIR_CODE_1: %08x\n",
763 ipu_csi_read(csi, CSI_CCIR_CODE_1));
764 dev_dbg(csi->ipu->dev, "CSI_CCIR_CODE_2: %08x\n",
765 ipu_csi_read(csi, CSI_CCIR_CODE_2));
766 dev_dbg(csi->ipu->dev, "CSI_CCIR_CODE_3: %08x\n",
767 ipu_csi_read(csi, CSI_CCIR_CODE_3));
768 dev_dbg(csi->ipu->dev, "CSI_MIPI_DI: %08x\n",
769 ipu_csi_read(csi, CSI_MIPI_DI));
770 dev_dbg(csi->ipu->dev, "CSI_SKIP: %08x\n",
771 ipu_csi_read(csi, CSI_SKIP));
772 }
773 EXPORT_SYMBOL_GPL(ipu_csi_dump);
774