1 /* Copyright (c) 2011-2012, The Linux Foundation. All rights reserved.
2 *
3 * Description: CoreSight Embedded Trace Buffer driver
4 *
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License version 2 and
7 * only version 2 as published by the Free Software Foundation.
8 *
9 * This program is distributed in the hope that it will be useful,
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 * GNU General Public License for more details.
13 */
14
15 #include <asm/local.h>
16 #include <linux/kernel.h>
17 #include <linux/init.h>
18 #include <linux/types.h>
19 #include <linux/device.h>
20 #include <linux/io.h>
21 #include <linux/err.h>
22 #include <linux/fs.h>
23 #include <linux/miscdevice.h>
24 #include <linux/uaccess.h>
25 #include <linux/slab.h>
26 #include <linux/spinlock.h>
27 #include <linux/pm_runtime.h>
28 #include <linux/seq_file.h>
29 #include <linux/coresight.h>
30 #include <linux/amba/bus.h>
31 #include <linux/clk.h>
32 #include <linux/circ_buf.h>
33 #include <linux/mm.h>
34 #include <linux/perf_event.h>
35
36 #include <asm/local.h>
37
38 #include "coresight-priv.h"
39
40 #define ETB_RAM_DEPTH_REG 0x004
41 #define ETB_STATUS_REG 0x00c
42 #define ETB_RAM_READ_DATA_REG 0x010
43 #define ETB_RAM_READ_POINTER 0x014
44 #define ETB_RAM_WRITE_POINTER 0x018
45 #define ETB_TRG 0x01c
46 #define ETB_CTL_REG 0x020
47 #define ETB_RWD_REG 0x024
48 #define ETB_FFSR 0x300
49 #define ETB_FFCR 0x304
50 #define ETB_ITMISCOP0 0xee0
51 #define ETB_ITTRFLINACK 0xee4
52 #define ETB_ITTRFLIN 0xee8
53 #define ETB_ITATBDATA0 0xeeC
54 #define ETB_ITATBCTR2 0xef0
55 #define ETB_ITATBCTR1 0xef4
56 #define ETB_ITATBCTR0 0xef8
57
58 /* register description */
59 /* STS - 0x00C */
60 #define ETB_STATUS_RAM_FULL BIT(0)
61 /* CTL - 0x020 */
62 #define ETB_CTL_CAPT_EN BIT(0)
63 /* FFCR - 0x304 */
64 #define ETB_FFCR_EN_FTC BIT(0)
65 #define ETB_FFCR_FON_MAN BIT(6)
66 #define ETB_FFCR_STOP_FI BIT(12)
67 #define ETB_FFCR_STOP_TRIGGER BIT(13)
68
69 #define ETB_FFCR_BIT 6
70 #define ETB_FFSR_BIT 1
71 #define ETB_FRAME_SIZE_WORDS 4
72
73 /**
74 * struct etb_drvdata - specifics associated to an ETB component
75 * @base: memory mapped base address for this component.
76 * @dev: the device entity associated to this component.
77 * @atclk: optional clock for the core parts of the ETB.
78 * @csdev: component vitals needed by the framework.
79 * @miscdev: specifics to handle "/dev/xyz.etb" entry.
80 * @spinlock: only one at a time pls.
81 * @reading: synchronise user space access to etb buffer.
82 * @mode: this ETB is being used.
83 * @buf: area of memory where ETB buffer content gets sent.
84 * @buffer_depth: size of @buf.
85 * @trigger_cntr: amount of words to store after a trigger.
86 */
87 struct etb_drvdata {
88 void __iomem *base;
89 struct device *dev;
90 struct clk *atclk;
91 struct coresight_device *csdev;
92 struct miscdevice miscdev;
93 spinlock_t spinlock;
94 local_t reading;
95 local_t mode;
96 u8 *buf;
97 u32 buffer_depth;
98 u32 trigger_cntr;
99 };
100
etb_get_buffer_depth(struct etb_drvdata * drvdata)101 static unsigned int etb_get_buffer_depth(struct etb_drvdata *drvdata)
102 {
103 u32 depth = 0;
104
105 pm_runtime_get_sync(drvdata->dev);
106
107 /* RO registers don't need locking */
108 depth = readl_relaxed(drvdata->base + ETB_RAM_DEPTH_REG);
109
110 pm_runtime_put(drvdata->dev);
111 return depth;
112 }
113
etb_enable_hw(struct etb_drvdata * drvdata)114 static void etb_enable_hw(struct etb_drvdata *drvdata)
115 {
116 int i;
117 u32 depth;
118
119 CS_UNLOCK(drvdata->base);
120
121 depth = drvdata->buffer_depth;
122 /* reset write RAM pointer address */
123 writel_relaxed(0x0, drvdata->base + ETB_RAM_WRITE_POINTER);
124 /* clear entire RAM buffer */
125 for (i = 0; i < depth; i++)
126 writel_relaxed(0x0, drvdata->base + ETB_RWD_REG);
127
128 /* reset write RAM pointer address */
129 writel_relaxed(0x0, drvdata->base + ETB_RAM_WRITE_POINTER);
130 /* reset read RAM pointer address */
131 writel_relaxed(0x0, drvdata->base + ETB_RAM_READ_POINTER);
132
133 writel_relaxed(drvdata->trigger_cntr, drvdata->base + ETB_TRG);
134 writel_relaxed(ETB_FFCR_EN_FTC | ETB_FFCR_STOP_TRIGGER,
135 drvdata->base + ETB_FFCR);
136 /* ETB trace capture enable */
137 writel_relaxed(ETB_CTL_CAPT_EN, drvdata->base + ETB_CTL_REG);
138
139 CS_LOCK(drvdata->base);
140 }
141
etb_enable(struct coresight_device * csdev,u32 mode)142 static int etb_enable(struct coresight_device *csdev, u32 mode)
143 {
144 u32 val;
145 unsigned long flags;
146 struct etb_drvdata *drvdata = dev_get_drvdata(csdev->dev.parent);
147
148 val = local_cmpxchg(&drvdata->mode,
149 CS_MODE_DISABLED, mode);
150 /*
151 * When accessing from Perf, a HW buffer can be handled
152 * by a single trace entity. In sysFS mode many tracers
153 * can be logging to the same HW buffer.
154 */
155 if (val == CS_MODE_PERF)
156 return -EBUSY;
157
158 /* Don't let perf disturb sysFS sessions */
159 if (val == CS_MODE_SYSFS && mode == CS_MODE_PERF)
160 return -EBUSY;
161
162 /* Nothing to do, the tracer is already enabled. */
163 if (val == CS_MODE_SYSFS)
164 goto out;
165
166 spin_lock_irqsave(&drvdata->spinlock, flags);
167 etb_enable_hw(drvdata);
168 spin_unlock_irqrestore(&drvdata->spinlock, flags);
169
170 out:
171 dev_info(drvdata->dev, "ETB enabled\n");
172 return 0;
173 }
174
etb_disable_hw(struct etb_drvdata * drvdata)175 static void etb_disable_hw(struct etb_drvdata *drvdata)
176 {
177 u32 ffcr;
178
179 CS_UNLOCK(drvdata->base);
180
181 ffcr = readl_relaxed(drvdata->base + ETB_FFCR);
182 /* stop formatter when a stop has completed */
183 ffcr |= ETB_FFCR_STOP_FI;
184 writel_relaxed(ffcr, drvdata->base + ETB_FFCR);
185 /* manually generate a flush of the system */
186 ffcr |= ETB_FFCR_FON_MAN;
187 writel_relaxed(ffcr, drvdata->base + ETB_FFCR);
188
189 if (coresight_timeout(drvdata->base, ETB_FFCR, ETB_FFCR_BIT, 0)) {
190 dev_err(drvdata->dev,
191 "timeout while waiting for completion of Manual Flush\n");
192 }
193
194 /* disable trace capture */
195 writel_relaxed(0x0, drvdata->base + ETB_CTL_REG);
196
197 if (coresight_timeout(drvdata->base, ETB_FFSR, ETB_FFSR_BIT, 1)) {
198 dev_err(drvdata->dev,
199 "timeout while waiting for Formatter to Stop\n");
200 }
201
202 CS_LOCK(drvdata->base);
203 }
204
etb_dump_hw(struct etb_drvdata * drvdata)205 static void etb_dump_hw(struct etb_drvdata *drvdata)
206 {
207 bool lost = false;
208 int i;
209 u8 *buf_ptr;
210 const u32 *barrier;
211 u32 read_data, depth;
212 u32 read_ptr, write_ptr;
213 u32 frame_off, frame_endoff;
214
215 CS_UNLOCK(drvdata->base);
216
217 read_ptr = readl_relaxed(drvdata->base + ETB_RAM_READ_POINTER);
218 write_ptr = readl_relaxed(drvdata->base + ETB_RAM_WRITE_POINTER);
219
220 frame_off = write_ptr % ETB_FRAME_SIZE_WORDS;
221 frame_endoff = ETB_FRAME_SIZE_WORDS - frame_off;
222 if (frame_off) {
223 dev_err(drvdata->dev,
224 "write_ptr: %lu not aligned to formatter frame size\n",
225 (unsigned long)write_ptr);
226 dev_err(drvdata->dev, "frameoff: %lu, frame_endoff: %lu\n",
227 (unsigned long)frame_off, (unsigned long)frame_endoff);
228 write_ptr += frame_endoff;
229 }
230
231 if ((readl_relaxed(drvdata->base + ETB_STATUS_REG)
232 & ETB_STATUS_RAM_FULL) == 0) {
233 writel_relaxed(0x0, drvdata->base + ETB_RAM_READ_POINTER);
234 } else {
235 writel_relaxed(write_ptr, drvdata->base + ETB_RAM_READ_POINTER);
236 lost = true;
237 }
238
239 depth = drvdata->buffer_depth;
240 buf_ptr = drvdata->buf;
241 barrier = barrier_pkt;
242 for (i = 0; i < depth; i++) {
243 read_data = readl_relaxed(drvdata->base +
244 ETB_RAM_READ_DATA_REG);
245 if (lost && *barrier) {
246 read_data = *barrier;
247 barrier++;
248 }
249
250 *(u32 *)buf_ptr = read_data;
251 buf_ptr += 4;
252 }
253
254 if (frame_off) {
255 buf_ptr -= (frame_endoff * 4);
256 for (i = 0; i < frame_endoff; i++) {
257 *buf_ptr++ = 0x0;
258 *buf_ptr++ = 0x0;
259 *buf_ptr++ = 0x0;
260 *buf_ptr++ = 0x0;
261 }
262 }
263
264 writel_relaxed(read_ptr, drvdata->base + ETB_RAM_READ_POINTER);
265
266 CS_LOCK(drvdata->base);
267 }
268
etb_disable(struct coresight_device * csdev)269 static void etb_disable(struct coresight_device *csdev)
270 {
271 struct etb_drvdata *drvdata = dev_get_drvdata(csdev->dev.parent);
272 unsigned long flags;
273
274 spin_lock_irqsave(&drvdata->spinlock, flags);
275 etb_disable_hw(drvdata);
276 etb_dump_hw(drvdata);
277 spin_unlock_irqrestore(&drvdata->spinlock, flags);
278
279 local_set(&drvdata->mode, CS_MODE_DISABLED);
280
281 dev_info(drvdata->dev, "ETB disabled\n");
282 }
283
etb_alloc_buffer(struct coresight_device * csdev,int cpu,void ** pages,int nr_pages,bool overwrite)284 static void *etb_alloc_buffer(struct coresight_device *csdev, int cpu,
285 void **pages, int nr_pages, bool overwrite)
286 {
287 int node;
288 struct cs_buffers *buf;
289
290 node = (cpu == -1) ? NUMA_NO_NODE : cpu_to_node(cpu);
291
292 buf = kzalloc_node(sizeof(struct cs_buffers), GFP_KERNEL, node);
293 if (!buf)
294 return NULL;
295
296 buf->snapshot = overwrite;
297 buf->nr_pages = nr_pages;
298 buf->data_pages = pages;
299
300 return buf;
301 }
302
etb_free_buffer(void * config)303 static void etb_free_buffer(void *config)
304 {
305 struct cs_buffers *buf = config;
306
307 kfree(buf);
308 }
309
etb_set_buffer(struct coresight_device * csdev,struct perf_output_handle * handle,void * sink_config)310 static int etb_set_buffer(struct coresight_device *csdev,
311 struct perf_output_handle *handle,
312 void *sink_config)
313 {
314 int ret = 0;
315 unsigned long head;
316 struct cs_buffers *buf = sink_config;
317
318 /* wrap head around to the amount of space we have */
319 head = handle->head & ((buf->nr_pages << PAGE_SHIFT) - 1);
320
321 /* find the page to write to */
322 buf->cur = head / PAGE_SIZE;
323
324 /* and offset within that page */
325 buf->offset = head % PAGE_SIZE;
326
327 local_set(&buf->data_size, 0);
328
329 return ret;
330 }
331
etb_reset_buffer(struct coresight_device * csdev,struct perf_output_handle * handle,void * sink_config)332 static unsigned long etb_reset_buffer(struct coresight_device *csdev,
333 struct perf_output_handle *handle,
334 void *sink_config)
335 {
336 unsigned long size = 0;
337 struct cs_buffers *buf = sink_config;
338
339 if (buf) {
340 /*
341 * In snapshot mode ->data_size holds the new address of the
342 * ring buffer's head. The size itself is the whole address
343 * range since we want the latest information.
344 */
345 if (buf->snapshot)
346 handle->head = local_xchg(&buf->data_size,
347 buf->nr_pages << PAGE_SHIFT);
348
349 /*
350 * Tell the tracer PMU how much we got in this run and if
351 * something went wrong along the way. Nobody else can use
352 * this cs_buffers instance until we are done. As such
353 * resetting parameters here and squaring off with the ring
354 * buffer API in the tracer PMU is fine.
355 */
356 size = local_xchg(&buf->data_size, 0);
357 }
358
359 return size;
360 }
361
etb_update_buffer(struct coresight_device * csdev,struct perf_output_handle * handle,void * sink_config)362 static void etb_update_buffer(struct coresight_device *csdev,
363 struct perf_output_handle *handle,
364 void *sink_config)
365 {
366 bool lost = false;
367 int i, cur;
368 u8 *buf_ptr;
369 const u32 *barrier;
370 u32 read_ptr, write_ptr, capacity;
371 u32 status, read_data, to_read;
372 unsigned long offset;
373 struct cs_buffers *buf = sink_config;
374 struct etb_drvdata *drvdata = dev_get_drvdata(csdev->dev.parent);
375
376 if (!buf)
377 return;
378
379 capacity = drvdata->buffer_depth * ETB_FRAME_SIZE_WORDS;
380
381 etb_disable_hw(drvdata);
382 CS_UNLOCK(drvdata->base);
383
384 /* unit is in words, not bytes */
385 read_ptr = readl_relaxed(drvdata->base + ETB_RAM_READ_POINTER);
386 write_ptr = readl_relaxed(drvdata->base + ETB_RAM_WRITE_POINTER);
387
388 /*
389 * Entries should be aligned to the frame size. If they are not
390 * go back to the last alignment point to give decoding tools a
391 * chance to fix things.
392 */
393 if (write_ptr % ETB_FRAME_SIZE_WORDS) {
394 dev_err(drvdata->dev,
395 "write_ptr: %lu not aligned to formatter frame size\n",
396 (unsigned long)write_ptr);
397
398 write_ptr &= ~(ETB_FRAME_SIZE_WORDS - 1);
399 lost = true;
400 }
401
402 /*
403 * Get a hold of the status register and see if a wrap around
404 * has occurred. If so adjust things accordingly. Otherwise
405 * start at the beginning and go until the write pointer has
406 * been reached.
407 */
408 status = readl_relaxed(drvdata->base + ETB_STATUS_REG);
409 if (status & ETB_STATUS_RAM_FULL) {
410 lost = true;
411 to_read = capacity;
412 read_ptr = write_ptr;
413 } else {
414 to_read = CIRC_CNT(write_ptr, read_ptr, drvdata->buffer_depth);
415 to_read *= ETB_FRAME_SIZE_WORDS;
416 }
417
418 /*
419 * Make sure we don't overwrite data that hasn't been consumed yet.
420 * It is entirely possible that the HW buffer has more data than the
421 * ring buffer can currently handle. If so adjust the start address
422 * to take only the last traces.
423 *
424 * In snapshot mode we are looking to get the latest traces only and as
425 * such, we don't care about not overwriting data that hasn't been
426 * processed by user space.
427 */
428 if (!buf->snapshot && to_read > handle->size) {
429 u32 mask = ~(ETB_FRAME_SIZE_WORDS - 1);
430
431 /* The new read pointer must be frame size aligned */
432 to_read = handle->size & mask;
433 /*
434 * Move the RAM read pointer up, keeping in mind that
435 * everything is in frame size units.
436 */
437 read_ptr = (write_ptr + drvdata->buffer_depth) -
438 to_read / ETB_FRAME_SIZE_WORDS;
439 /* Wrap around if need be*/
440 if (read_ptr > (drvdata->buffer_depth - 1))
441 read_ptr -= drvdata->buffer_depth;
442 /* let the decoder know we've skipped ahead */
443 lost = true;
444 }
445
446 if (lost)
447 perf_aux_output_flag(handle, PERF_AUX_FLAG_TRUNCATED);
448
449 /* finally tell HW where we want to start reading from */
450 writel_relaxed(read_ptr, drvdata->base + ETB_RAM_READ_POINTER);
451
452 cur = buf->cur;
453 offset = buf->offset;
454 barrier = barrier_pkt;
455
456 for (i = 0; i < to_read; i += 4) {
457 buf_ptr = buf->data_pages[cur] + offset;
458 read_data = readl_relaxed(drvdata->base +
459 ETB_RAM_READ_DATA_REG);
460 if (lost && *barrier) {
461 read_data = *barrier;
462 barrier++;
463 }
464
465 *(u32 *)buf_ptr = read_data;
466 buf_ptr += 4;
467
468 offset += 4;
469 if (offset >= PAGE_SIZE) {
470 offset = 0;
471 cur++;
472 /* wrap around at the end of the buffer */
473 cur &= buf->nr_pages - 1;
474 }
475 }
476
477 /* reset ETB buffer for next run */
478 writel_relaxed(0x0, drvdata->base + ETB_RAM_READ_POINTER);
479 writel_relaxed(0x0, drvdata->base + ETB_RAM_WRITE_POINTER);
480
481 /*
482 * In snapshot mode all we have to do is communicate to
483 * perf_aux_output_end() the address of the current head. In full
484 * trace mode the same function expects a size to move rb->aux_head
485 * forward.
486 */
487 if (buf->snapshot)
488 local_set(&buf->data_size, (cur * PAGE_SIZE) + offset);
489 else
490 local_add(to_read, &buf->data_size);
491
492 etb_enable_hw(drvdata);
493 CS_LOCK(drvdata->base);
494 }
495
496 static const struct coresight_ops_sink etb_sink_ops = {
497 .enable = etb_enable,
498 .disable = etb_disable,
499 .alloc_buffer = etb_alloc_buffer,
500 .free_buffer = etb_free_buffer,
501 .set_buffer = etb_set_buffer,
502 .reset_buffer = etb_reset_buffer,
503 .update_buffer = etb_update_buffer,
504 };
505
506 static const struct coresight_ops etb_cs_ops = {
507 .sink_ops = &etb_sink_ops,
508 };
509
etb_dump(struct etb_drvdata * drvdata)510 static void etb_dump(struct etb_drvdata *drvdata)
511 {
512 unsigned long flags;
513
514 spin_lock_irqsave(&drvdata->spinlock, flags);
515 if (local_read(&drvdata->mode) == CS_MODE_SYSFS) {
516 etb_disable_hw(drvdata);
517 etb_dump_hw(drvdata);
518 etb_enable_hw(drvdata);
519 }
520 spin_unlock_irqrestore(&drvdata->spinlock, flags);
521
522 dev_info(drvdata->dev, "ETB dumped\n");
523 }
524
etb_open(struct inode * inode,struct file * file)525 static int etb_open(struct inode *inode, struct file *file)
526 {
527 struct etb_drvdata *drvdata = container_of(file->private_data,
528 struct etb_drvdata, miscdev);
529
530 if (local_cmpxchg(&drvdata->reading, 0, 1))
531 return -EBUSY;
532
533 dev_dbg(drvdata->dev, "%s: successfully opened\n", __func__);
534 return 0;
535 }
536
etb_read(struct file * file,char __user * data,size_t len,loff_t * ppos)537 static ssize_t etb_read(struct file *file, char __user *data,
538 size_t len, loff_t *ppos)
539 {
540 u32 depth;
541 struct etb_drvdata *drvdata = container_of(file->private_data,
542 struct etb_drvdata, miscdev);
543
544 etb_dump(drvdata);
545
546 depth = drvdata->buffer_depth;
547 if (*ppos + len > depth * 4)
548 len = depth * 4 - *ppos;
549
550 if (copy_to_user(data, drvdata->buf + *ppos, len)) {
551 dev_dbg(drvdata->dev, "%s: copy_to_user failed\n", __func__);
552 return -EFAULT;
553 }
554
555 *ppos += len;
556
557 dev_dbg(drvdata->dev, "%s: %zu bytes copied, %d bytes left\n",
558 __func__, len, (int)(depth * 4 - *ppos));
559 return len;
560 }
561
etb_release(struct inode * inode,struct file * file)562 static int etb_release(struct inode *inode, struct file *file)
563 {
564 struct etb_drvdata *drvdata = container_of(file->private_data,
565 struct etb_drvdata, miscdev);
566 local_set(&drvdata->reading, 0);
567
568 dev_dbg(drvdata->dev, "%s: released\n", __func__);
569 return 0;
570 }
571
572 static const struct file_operations etb_fops = {
573 .owner = THIS_MODULE,
574 .open = etb_open,
575 .read = etb_read,
576 .release = etb_release,
577 .llseek = no_llseek,
578 };
579
580 #define coresight_etb10_reg(name, offset) \
581 coresight_simple_reg32(struct etb_drvdata, name, offset)
582
583 coresight_etb10_reg(rdp, ETB_RAM_DEPTH_REG);
584 coresight_etb10_reg(sts, ETB_STATUS_REG);
585 coresight_etb10_reg(rrp, ETB_RAM_READ_POINTER);
586 coresight_etb10_reg(rwp, ETB_RAM_WRITE_POINTER);
587 coresight_etb10_reg(trg, ETB_TRG);
588 coresight_etb10_reg(ctl, ETB_CTL_REG);
589 coresight_etb10_reg(ffsr, ETB_FFSR);
590 coresight_etb10_reg(ffcr, ETB_FFCR);
591
592 static struct attribute *coresight_etb_mgmt_attrs[] = {
593 &dev_attr_rdp.attr,
594 &dev_attr_sts.attr,
595 &dev_attr_rrp.attr,
596 &dev_attr_rwp.attr,
597 &dev_attr_trg.attr,
598 &dev_attr_ctl.attr,
599 &dev_attr_ffsr.attr,
600 &dev_attr_ffcr.attr,
601 NULL,
602 };
603
trigger_cntr_show(struct device * dev,struct device_attribute * attr,char * buf)604 static ssize_t trigger_cntr_show(struct device *dev,
605 struct device_attribute *attr, char *buf)
606 {
607 struct etb_drvdata *drvdata = dev_get_drvdata(dev->parent);
608 unsigned long val = drvdata->trigger_cntr;
609
610 return sprintf(buf, "%#lx\n", val);
611 }
612
trigger_cntr_store(struct device * dev,struct device_attribute * attr,const char * buf,size_t size)613 static ssize_t trigger_cntr_store(struct device *dev,
614 struct device_attribute *attr,
615 const char *buf, size_t size)
616 {
617 int ret;
618 unsigned long val;
619 struct etb_drvdata *drvdata = dev_get_drvdata(dev->parent);
620
621 ret = kstrtoul(buf, 16, &val);
622 if (ret)
623 return ret;
624
625 drvdata->trigger_cntr = val;
626 return size;
627 }
628 static DEVICE_ATTR_RW(trigger_cntr);
629
630 static struct attribute *coresight_etb_attrs[] = {
631 &dev_attr_trigger_cntr.attr,
632 NULL,
633 };
634
635 static const struct attribute_group coresight_etb_group = {
636 .attrs = coresight_etb_attrs,
637 };
638
639 static const struct attribute_group coresight_etb_mgmt_group = {
640 .attrs = coresight_etb_mgmt_attrs,
641 .name = "mgmt",
642 };
643
644 const struct attribute_group *coresight_etb_groups[] = {
645 &coresight_etb_group,
646 &coresight_etb_mgmt_group,
647 NULL,
648 };
649
etb_probe(struct amba_device * adev,const struct amba_id * id)650 static int etb_probe(struct amba_device *adev, const struct amba_id *id)
651 {
652 int ret;
653 void __iomem *base;
654 struct device *dev = &adev->dev;
655 struct coresight_platform_data *pdata = NULL;
656 struct etb_drvdata *drvdata;
657 struct resource *res = &adev->res;
658 struct coresight_desc desc = { 0 };
659 struct device_node *np = adev->dev.of_node;
660
661 if (np) {
662 pdata = of_get_coresight_platform_data(dev, np);
663 if (IS_ERR(pdata))
664 return PTR_ERR(pdata);
665 adev->dev.platform_data = pdata;
666 }
667
668 drvdata = devm_kzalloc(dev, sizeof(*drvdata), GFP_KERNEL);
669 if (!drvdata)
670 return -ENOMEM;
671
672 drvdata->dev = &adev->dev;
673 drvdata->atclk = devm_clk_get(&adev->dev, "atclk"); /* optional */
674 if (!IS_ERR(drvdata->atclk)) {
675 ret = clk_prepare_enable(drvdata->atclk);
676 if (ret)
677 return ret;
678 }
679 dev_set_drvdata(dev, drvdata);
680
681 /* validity for the resource is already checked by the AMBA core */
682 base = devm_ioremap_resource(dev, res);
683 if (IS_ERR(base))
684 return PTR_ERR(base);
685
686 drvdata->base = base;
687
688 spin_lock_init(&drvdata->spinlock);
689
690 drvdata->buffer_depth = etb_get_buffer_depth(drvdata);
691 pm_runtime_put(&adev->dev);
692
693 if (drvdata->buffer_depth & 0x80000000)
694 return -EINVAL;
695
696 drvdata->buf = devm_kzalloc(dev,
697 drvdata->buffer_depth * 4, GFP_KERNEL);
698 if (!drvdata->buf)
699 return -ENOMEM;
700
701 desc.type = CORESIGHT_DEV_TYPE_SINK;
702 desc.subtype.sink_subtype = CORESIGHT_DEV_SUBTYPE_SINK_BUFFER;
703 desc.ops = &etb_cs_ops;
704 desc.pdata = pdata;
705 desc.dev = dev;
706 desc.groups = coresight_etb_groups;
707 drvdata->csdev = coresight_register(&desc);
708 if (IS_ERR(drvdata->csdev))
709 return PTR_ERR(drvdata->csdev);
710
711 drvdata->miscdev.name = pdata->name;
712 drvdata->miscdev.minor = MISC_DYNAMIC_MINOR;
713 drvdata->miscdev.fops = &etb_fops;
714 ret = misc_register(&drvdata->miscdev);
715 if (ret)
716 goto err_misc_register;
717
718 return 0;
719
720 err_misc_register:
721 coresight_unregister(drvdata->csdev);
722 return ret;
723 }
724
725 #ifdef CONFIG_PM
etb_runtime_suspend(struct device * dev)726 static int etb_runtime_suspend(struct device *dev)
727 {
728 struct etb_drvdata *drvdata = dev_get_drvdata(dev);
729
730 if (drvdata && !IS_ERR(drvdata->atclk))
731 clk_disable_unprepare(drvdata->atclk);
732
733 return 0;
734 }
735
etb_runtime_resume(struct device * dev)736 static int etb_runtime_resume(struct device *dev)
737 {
738 struct etb_drvdata *drvdata = dev_get_drvdata(dev);
739
740 if (drvdata && !IS_ERR(drvdata->atclk))
741 clk_prepare_enable(drvdata->atclk);
742
743 return 0;
744 }
745 #endif
746
747 static const struct dev_pm_ops etb_dev_pm_ops = {
748 SET_RUNTIME_PM_OPS(etb_runtime_suspend, etb_runtime_resume, NULL)
749 };
750
751 static const struct amba_id etb_ids[] = {
752 {
753 .id = 0x0003b907,
754 .mask = 0x0003ffff,
755 },
756 { 0, 0},
757 };
758
759 static struct amba_driver etb_driver = {
760 .drv = {
761 .name = "coresight-etb10",
762 .owner = THIS_MODULE,
763 .pm = &etb_dev_pm_ops,
764 .suppress_bind_attrs = true,
765
766 },
767 .probe = etb_probe,
768 .id_table = etb_ids,
769 };
770 builtin_amba_driver(etb_driver);
771