1 /* Copyright (c) 2011-2012, The Linux Foundation. All rights reserved.
2 *
3 * This program is free software; you can redistribute it and/or modify
4 * it under the terms of the GNU General Public License version 2 and
5 * only version 2 as published by the Free Software Foundation.
6 *
7 * This program is distributed in the hope that it will be useful,
8 * but WITHOUT ANY WARRANTY; without even the implied warranty of
9 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
10 * GNU General Public License for more details.
11 */
12
13 #ifndef _CORESIGHT_PRIV_H
14 #define _CORESIGHT_PRIV_H
15
16 #include <linux/bitops.h>
17 #include <linux/io.h>
18 #include <linux/coresight.h>
19 #include <linux/pm_runtime.h>
20
21 /*
22 * Coresight management registers (0xf00-0xfcc)
23 * 0xfa0 - 0xfa4: Management registers in PFTv1.0
24 * Trace registers in PFTv1.1
25 */
26 #define CORESIGHT_ITCTRL 0xf00
27 #define CORESIGHT_CLAIMSET 0xfa0
28 #define CORESIGHT_CLAIMCLR 0xfa4
29 #define CORESIGHT_LAR 0xfb0
30 #define CORESIGHT_LSR 0xfb4
31 #define CORESIGHT_AUTHSTATUS 0xfb8
32 #define CORESIGHT_DEVID 0xfc8
33 #define CORESIGHT_DEVTYPE 0xfcc
34
35 #define TIMEOUT_US 100
36 #define BMVAL(val, lsb, msb) ((val & GENMASK(msb, lsb)) >> lsb)
37
38 #define ETM_MODE_EXCL_KERN BIT(30)
39 #define ETM_MODE_EXCL_USER BIT(31)
40
41 typedef u32 (*coresight_read_fn)(const struct device *, u32 offset);
42 #define __coresight_simple_func(type, func, name, lo_off, hi_off) \
43 static ssize_t name##_show(struct device *_dev, \
44 struct device_attribute *attr, char *buf) \
45 { \
46 type *drvdata = dev_get_drvdata(_dev->parent); \
47 coresight_read_fn fn = func; \
48 u64 val; \
49 pm_runtime_get_sync(_dev->parent); \
50 if (fn) \
51 val = (u64)fn(_dev->parent, lo_off); \
52 else \
53 val = coresight_read_reg_pair(drvdata->base, \
54 lo_off, hi_off); \
55 pm_runtime_put_sync(_dev->parent); \
56 return scnprintf(buf, PAGE_SIZE, "0x%llx\n", val); \
57 } \
58 static DEVICE_ATTR_RO(name)
59
60 #define coresight_simple_func(type, func, name, offset) \
61 __coresight_simple_func(type, func, name, offset, -1)
62 #define coresight_simple_reg32(type, name, offset) \
63 __coresight_simple_func(type, NULL, name, offset, -1)
64 #define coresight_simple_reg64(type, name, lo_off, hi_off) \
65 __coresight_simple_func(type, NULL, name, lo_off, hi_off)
66
67 extern const u32 barrier_pkt[5];
68
69 enum etm_addr_type {
70 ETM_ADDR_TYPE_NONE,
71 ETM_ADDR_TYPE_SINGLE,
72 ETM_ADDR_TYPE_RANGE,
73 ETM_ADDR_TYPE_START,
74 ETM_ADDR_TYPE_STOP,
75 };
76
77 enum cs_mode {
78 CS_MODE_DISABLED,
79 CS_MODE_SYSFS,
80 CS_MODE_PERF,
81 };
82
83 /**
84 * struct cs_buffer - keep track of a recording session' specifics
85 * @cur: index of the current buffer
86 * @nr_pages: max number of pages granted to us
87 * @offset: offset within the current buffer
88 * @data_size: how much we collected in this run
89 * @snapshot: is this run in snapshot mode
90 * @data_pages: a handle the ring buffer
91 */
92 struct cs_buffers {
93 unsigned int cur;
94 unsigned int nr_pages;
95 unsigned long offset;
96 local_t data_size;
97 bool snapshot;
98 void **data_pages;
99 };
100
CS_LOCK(void __iomem * addr)101 static inline void CS_LOCK(void __iomem *addr)
102 {
103 do {
104 /* Wait for things to settle */
105 mb();
106 writel_relaxed(0x0, addr + CORESIGHT_LAR);
107 } while (0);
108 }
109
CS_UNLOCK(void __iomem * addr)110 static inline void CS_UNLOCK(void __iomem *addr)
111 {
112 do {
113 writel_relaxed(CORESIGHT_UNLOCK, addr + CORESIGHT_LAR);
114 /* Make sure everyone has seen this */
115 mb();
116 } while (0);
117 }
118
119 static inline u64
coresight_read_reg_pair(void __iomem * addr,s32 lo_offset,s32 hi_offset)120 coresight_read_reg_pair(void __iomem *addr, s32 lo_offset, s32 hi_offset)
121 {
122 u64 val;
123
124 val = readl_relaxed(addr + lo_offset);
125 val |= (hi_offset < 0) ? 0 :
126 (u64)readl_relaxed(addr + hi_offset) << 32;
127 return val;
128 }
129
coresight_write_reg_pair(void __iomem * addr,u64 val,s32 lo_offset,s32 hi_offset)130 static inline void coresight_write_reg_pair(void __iomem *addr, u64 val,
131 s32 lo_offset, s32 hi_offset)
132 {
133 writel_relaxed((u32)val, addr + lo_offset);
134 if (hi_offset >= 0)
135 writel_relaxed((u32)(val >> 32), addr + hi_offset);
136 }
137
138 void coresight_disable_path(struct list_head *path);
139 int coresight_enable_path(struct list_head *path, u32 mode);
140 struct coresight_device *coresight_get_sink(struct list_head *path);
141 struct coresight_device *coresight_get_enabled_sink(bool reset);
142 struct list_head *coresight_build_path(struct coresight_device *csdev,
143 struct coresight_device *sink);
144 void coresight_release_path(struct list_head *path);
145
146 #ifdef CONFIG_CORESIGHT_SOURCE_ETM3X
147 extern int etm_readl_cp14(u32 off, unsigned int *val);
148 extern int etm_writel_cp14(u32 off, u32 val);
149 #else
etm_readl_cp14(u32 off,unsigned int * val)150 static inline int etm_readl_cp14(u32 off, unsigned int *val) { return 0; }
etm_writel_cp14(u32 off,u32 val)151 static inline int etm_writel_cp14(u32 off, u32 val) { return 0; }
152 #endif
153
154 #endif
155