1 /*
2 * Intel CHT Whiskey Cove PMIC I2C Master driver
3 * Copyright (C) 2017 Hans de Goede <hdegoede@redhat.com>
4 *
5 * Based on various non upstream patches to support the CHT Whiskey Cove PMIC:
6 * Copyright (C) 2011 - 2014 Intel Corporation. All rights reserved.
7 *
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License version
10 * 2 as published by the Free Software Foundation, or (at your option)
11 * any later version.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 */
18
19 #include <linux/completion.h>
20 #include <linux/delay.h>
21 #include <linux/i2c.h>
22 #include <linux/interrupt.h>
23 #include <linux/irq.h>
24 #include <linux/irqdomain.h>
25 #include <linux/mfd/intel_soc_pmic.h>
26 #include <linux/module.h>
27 #include <linux/platform_device.h>
28 #include <linux/slab.h>
29
30 #define CHT_WC_I2C_CTRL 0x5e24
31 #define CHT_WC_I2C_CTRL_WR BIT(0)
32 #define CHT_WC_I2C_CTRL_RD BIT(1)
33 #define CHT_WC_I2C_CLIENT_ADDR 0x5e25
34 #define CHT_WC_I2C_REG_OFFSET 0x5e26
35 #define CHT_WC_I2C_WRDATA 0x5e27
36 #define CHT_WC_I2C_RDDATA 0x5e28
37
38 #define CHT_WC_EXTCHGRIRQ 0x6e0a
39 #define CHT_WC_EXTCHGRIRQ_CLIENT_IRQ BIT(0)
40 #define CHT_WC_EXTCHGRIRQ_WRITE_IRQ BIT(1)
41 #define CHT_WC_EXTCHGRIRQ_READ_IRQ BIT(2)
42 #define CHT_WC_EXTCHGRIRQ_NACK_IRQ BIT(3)
43 #define CHT_WC_EXTCHGRIRQ_ADAP_IRQMASK ((u8)GENMASK(3, 1))
44 #define CHT_WC_EXTCHGRIRQ_MSK 0x6e17
45
46 struct cht_wc_i2c_adap {
47 struct i2c_adapter adapter;
48 wait_queue_head_t wait;
49 struct irq_chip irqchip;
50 struct mutex adap_lock;
51 struct mutex irqchip_lock;
52 struct regmap *regmap;
53 struct irq_domain *irq_domain;
54 struct i2c_client *client;
55 int client_irq;
56 u8 irq_mask;
57 u8 old_irq_mask;
58 int read_data;
59 bool io_error;
60 bool done;
61 };
62
cht_wc_i2c_adap_thread_handler(int id,void * data)63 static irqreturn_t cht_wc_i2c_adap_thread_handler(int id, void *data)
64 {
65 struct cht_wc_i2c_adap *adap = data;
66 int ret, reg;
67
68 mutex_lock(&adap->adap_lock);
69
70 /* Read IRQs */
71 ret = regmap_read(adap->regmap, CHT_WC_EXTCHGRIRQ, ®);
72 if (ret) {
73 dev_err(&adap->adapter.dev, "Error reading extchgrirq reg\n");
74 mutex_unlock(&adap->adap_lock);
75 return IRQ_NONE;
76 }
77
78 reg &= ~adap->irq_mask;
79
80 /* Reads must be acked after reading the received data. */
81 ret = regmap_read(adap->regmap, CHT_WC_I2C_RDDATA, &adap->read_data);
82 if (ret)
83 adap->io_error = true;
84
85 /*
86 * Immediately ack IRQs, so that if new IRQs arrives while we're
87 * handling the previous ones our irq will re-trigger when we're done.
88 */
89 ret = regmap_write(adap->regmap, CHT_WC_EXTCHGRIRQ, reg);
90 if (ret)
91 dev_err(&adap->adapter.dev, "Error writing extchgrirq reg\n");
92
93 if (reg & CHT_WC_EXTCHGRIRQ_ADAP_IRQMASK) {
94 adap->io_error |= !!(reg & CHT_WC_EXTCHGRIRQ_NACK_IRQ);
95 adap->done = true;
96 }
97
98 mutex_unlock(&adap->adap_lock);
99
100 if (reg & CHT_WC_EXTCHGRIRQ_ADAP_IRQMASK)
101 wake_up(&adap->wait);
102
103 /*
104 * Do NOT use handle_nested_irq here, the client irq handler will
105 * likely want to do i2c transfers and the i2c controller uses this
106 * interrupt handler as well, so running the client irq handler from
107 * this thread will cause things to lock up.
108 */
109 if (reg & CHT_WC_EXTCHGRIRQ_CLIENT_IRQ) {
110 /*
111 * generic_handle_irq expects local IRQs to be disabled
112 * as normally it is called from interrupt context.
113 */
114 local_irq_disable();
115 generic_handle_irq(adap->client_irq);
116 local_irq_enable();
117 }
118
119 return IRQ_HANDLED;
120 }
121
cht_wc_i2c_adap_master_func(struct i2c_adapter * adap)122 static u32 cht_wc_i2c_adap_master_func(struct i2c_adapter *adap)
123 {
124 /* This i2c adapter only supports SMBUS byte transfers */
125 return I2C_FUNC_SMBUS_BYTE_DATA;
126 }
127
cht_wc_i2c_adap_smbus_xfer(struct i2c_adapter * _adap,u16 addr,unsigned short flags,char read_write,u8 command,int size,union i2c_smbus_data * data)128 static int cht_wc_i2c_adap_smbus_xfer(struct i2c_adapter *_adap, u16 addr,
129 unsigned short flags, char read_write,
130 u8 command, int size,
131 union i2c_smbus_data *data)
132 {
133 struct cht_wc_i2c_adap *adap = i2c_get_adapdata(_adap);
134 int ret;
135
136 mutex_lock(&adap->adap_lock);
137 adap->io_error = false;
138 adap->done = false;
139 mutex_unlock(&adap->adap_lock);
140
141 ret = regmap_write(adap->regmap, CHT_WC_I2C_CLIENT_ADDR, addr);
142 if (ret)
143 return ret;
144
145 if (read_write == I2C_SMBUS_WRITE) {
146 ret = regmap_write(adap->regmap, CHT_WC_I2C_WRDATA, data->byte);
147 if (ret)
148 return ret;
149 }
150
151 ret = regmap_write(adap->regmap, CHT_WC_I2C_REG_OFFSET, command);
152 if (ret)
153 return ret;
154
155 ret = regmap_write(adap->regmap, CHT_WC_I2C_CTRL,
156 (read_write == I2C_SMBUS_WRITE) ?
157 CHT_WC_I2C_CTRL_WR : CHT_WC_I2C_CTRL_RD);
158 if (ret)
159 return ret;
160
161 ret = wait_event_timeout(adap->wait, adap->done, msecs_to_jiffies(30));
162 if (ret == 0) {
163 /*
164 * The CHT GPIO controller serializes all IRQs, sometimes
165 * causing significant delays, check status manually.
166 */
167 cht_wc_i2c_adap_thread_handler(0, adap);
168 if (!adap->done)
169 return -ETIMEDOUT;
170 }
171
172 ret = 0;
173 mutex_lock(&adap->adap_lock);
174 if (adap->io_error)
175 ret = -EIO;
176 else if (read_write == I2C_SMBUS_READ)
177 data->byte = adap->read_data;
178 mutex_unlock(&adap->adap_lock);
179
180 return ret;
181 }
182
183 static const struct i2c_algorithm cht_wc_i2c_adap_algo = {
184 .functionality = cht_wc_i2c_adap_master_func,
185 .smbus_xfer = cht_wc_i2c_adap_smbus_xfer,
186 };
187
188 /*
189 * We are an i2c-adapter which itself is part of an i2c-client. This means that
190 * transfers done through us take adapter->bus_lock twice, once for our parent
191 * i2c-adapter and once to take our own bus_lock. Lockdep does not like this
192 * nested locking, to make lockdep happy in the case of busses with muxes, the
193 * i2c-core's i2c_adapter_lock_bus function calls:
194 * rt_mutex_lock_nested(&adapter->bus_lock, i2c_adapter_depth(adapter));
195 *
196 * But i2c_adapter_depth only works when the direct parent of the adapter is
197 * another adapter, as it is only meant for muxes. In our case there is an
198 * i2c-client and MFD instantiated platform_device in the parent->child chain
199 * between the 2 devices.
200 *
201 * So we override the default i2c_lock_operations and pass a hardcoded
202 * depth of 1 to rt_mutex_lock_nested, to make lockdep happy.
203 *
204 * Note that if there were to be a mux attached to our adapter, this would
205 * break things again since the i2c-mux code expects the root-adapter to have
206 * a locking depth of 0. But we always have only 1 client directly attached
207 * in the form of the Charger IC paired with the CHT Whiskey Cove PMIC.
208 */
cht_wc_i2c_adap_lock_bus(struct i2c_adapter * adapter,unsigned int flags)209 static void cht_wc_i2c_adap_lock_bus(struct i2c_adapter *adapter,
210 unsigned int flags)
211 {
212 rt_mutex_lock_nested(&adapter->bus_lock, 1);
213 }
214
cht_wc_i2c_adap_trylock_bus(struct i2c_adapter * adapter,unsigned int flags)215 static int cht_wc_i2c_adap_trylock_bus(struct i2c_adapter *adapter,
216 unsigned int flags)
217 {
218 return rt_mutex_trylock(&adapter->bus_lock);
219 }
220
cht_wc_i2c_adap_unlock_bus(struct i2c_adapter * adapter,unsigned int flags)221 static void cht_wc_i2c_adap_unlock_bus(struct i2c_adapter *adapter,
222 unsigned int flags)
223 {
224 rt_mutex_unlock(&adapter->bus_lock);
225 }
226
227 static const struct i2c_lock_operations cht_wc_i2c_adap_lock_ops = {
228 .lock_bus = cht_wc_i2c_adap_lock_bus,
229 .trylock_bus = cht_wc_i2c_adap_trylock_bus,
230 .unlock_bus = cht_wc_i2c_adap_unlock_bus,
231 };
232
233 /**** irqchip for the client connected to the extchgr i2c adapter ****/
cht_wc_i2c_irq_lock(struct irq_data * data)234 static void cht_wc_i2c_irq_lock(struct irq_data *data)
235 {
236 struct cht_wc_i2c_adap *adap = irq_data_get_irq_chip_data(data);
237
238 mutex_lock(&adap->irqchip_lock);
239 }
240
cht_wc_i2c_irq_sync_unlock(struct irq_data * data)241 static void cht_wc_i2c_irq_sync_unlock(struct irq_data *data)
242 {
243 struct cht_wc_i2c_adap *adap = irq_data_get_irq_chip_data(data);
244 int ret;
245
246 if (adap->irq_mask != adap->old_irq_mask) {
247 ret = regmap_write(adap->regmap, CHT_WC_EXTCHGRIRQ_MSK,
248 adap->irq_mask);
249 if (ret == 0)
250 adap->old_irq_mask = adap->irq_mask;
251 else
252 dev_err(&adap->adapter.dev, "Error writing EXTCHGRIRQ_MSK\n");
253 }
254
255 mutex_unlock(&adap->irqchip_lock);
256 }
257
cht_wc_i2c_irq_enable(struct irq_data * data)258 static void cht_wc_i2c_irq_enable(struct irq_data *data)
259 {
260 struct cht_wc_i2c_adap *adap = irq_data_get_irq_chip_data(data);
261
262 adap->irq_mask &= ~CHT_WC_EXTCHGRIRQ_CLIENT_IRQ;
263 }
264
cht_wc_i2c_irq_disable(struct irq_data * data)265 static void cht_wc_i2c_irq_disable(struct irq_data *data)
266 {
267 struct cht_wc_i2c_adap *adap = irq_data_get_irq_chip_data(data);
268
269 adap->irq_mask |= CHT_WC_EXTCHGRIRQ_CLIENT_IRQ;
270 }
271
272 static const struct irq_chip cht_wc_i2c_irq_chip = {
273 .irq_bus_lock = cht_wc_i2c_irq_lock,
274 .irq_bus_sync_unlock = cht_wc_i2c_irq_sync_unlock,
275 .irq_disable = cht_wc_i2c_irq_disable,
276 .irq_enable = cht_wc_i2c_irq_enable,
277 .name = "cht_wc_ext_chrg_irq_chip",
278 };
279
280 static const struct property_entry bq24190_props[] = {
281 PROPERTY_ENTRY_STRING("extcon-name", "cht_wcove_pwrsrc"),
282 PROPERTY_ENTRY_BOOL("omit-battery-class"),
283 PROPERTY_ENTRY_BOOL("disable-reset"),
284 { }
285 };
286
cht_wc_i2c_adap_i2c_probe(struct platform_device * pdev)287 static int cht_wc_i2c_adap_i2c_probe(struct platform_device *pdev)
288 {
289 struct intel_soc_pmic *pmic = dev_get_drvdata(pdev->dev.parent);
290 struct cht_wc_i2c_adap *adap;
291 struct i2c_board_info board_info = {
292 .type = "bq24190",
293 .addr = 0x6b,
294 .properties = bq24190_props,
295 };
296 int ret, reg, irq;
297
298 irq = platform_get_irq(pdev, 0);
299 if (irq < 0) {
300 dev_err(&pdev->dev, "Error missing irq resource\n");
301 return -EINVAL;
302 }
303
304 adap = devm_kzalloc(&pdev->dev, sizeof(*adap), GFP_KERNEL);
305 if (!adap)
306 return -ENOMEM;
307
308 init_waitqueue_head(&adap->wait);
309 mutex_init(&adap->adap_lock);
310 mutex_init(&adap->irqchip_lock);
311 adap->irqchip = cht_wc_i2c_irq_chip;
312 adap->regmap = pmic->regmap;
313 adap->adapter.owner = THIS_MODULE;
314 adap->adapter.class = I2C_CLASS_HWMON;
315 adap->adapter.algo = &cht_wc_i2c_adap_algo;
316 adap->adapter.lock_ops = &cht_wc_i2c_adap_lock_ops;
317 strlcpy(adap->adapter.name, "PMIC I2C Adapter",
318 sizeof(adap->adapter.name));
319 adap->adapter.dev.parent = &pdev->dev;
320
321 /* Clear and activate i2c-adapter interrupts, disable client IRQ */
322 adap->old_irq_mask = adap->irq_mask = ~CHT_WC_EXTCHGRIRQ_ADAP_IRQMASK;
323
324 ret = regmap_read(adap->regmap, CHT_WC_I2C_RDDATA, ®);
325 if (ret)
326 return ret;
327
328 ret = regmap_write(adap->regmap, CHT_WC_EXTCHGRIRQ, ~adap->irq_mask);
329 if (ret)
330 return ret;
331
332 ret = regmap_write(adap->regmap, CHT_WC_EXTCHGRIRQ_MSK, adap->irq_mask);
333 if (ret)
334 return ret;
335
336 /* Alloc and register client IRQ */
337 adap->irq_domain = irq_domain_add_linear(pdev->dev.of_node, 1,
338 &irq_domain_simple_ops, NULL);
339 if (!adap->irq_domain)
340 return -ENOMEM;
341
342 adap->client_irq = irq_create_mapping(adap->irq_domain, 0);
343 if (!adap->client_irq) {
344 ret = -ENOMEM;
345 goto remove_irq_domain;
346 }
347
348 irq_set_chip_data(adap->client_irq, adap);
349 irq_set_chip_and_handler(adap->client_irq, &adap->irqchip,
350 handle_simple_irq);
351
352 ret = devm_request_threaded_irq(&pdev->dev, irq, NULL,
353 cht_wc_i2c_adap_thread_handler,
354 IRQF_ONESHOT, "PMIC I2C Adapter", adap);
355 if (ret)
356 goto remove_irq_domain;
357
358 i2c_set_adapdata(&adap->adapter, adap);
359 ret = i2c_add_adapter(&adap->adapter);
360 if (ret)
361 goto remove_irq_domain;
362
363 board_info.irq = adap->client_irq;
364 adap->client = i2c_new_device(&adap->adapter, &board_info);
365 if (!adap->client) {
366 ret = -ENOMEM;
367 goto del_adapter;
368 }
369
370 platform_set_drvdata(pdev, adap);
371 return 0;
372
373 del_adapter:
374 i2c_del_adapter(&adap->adapter);
375 remove_irq_domain:
376 irq_domain_remove(adap->irq_domain);
377 return ret;
378 }
379
cht_wc_i2c_adap_i2c_remove(struct platform_device * pdev)380 static int cht_wc_i2c_adap_i2c_remove(struct platform_device *pdev)
381 {
382 struct cht_wc_i2c_adap *adap = platform_get_drvdata(pdev);
383
384 i2c_unregister_device(adap->client);
385 i2c_del_adapter(&adap->adapter);
386 irq_domain_remove(adap->irq_domain);
387
388 return 0;
389 }
390
391 static struct platform_device_id cht_wc_i2c_adap_id_table[] = {
392 { .name = "cht_wcove_ext_chgr" },
393 {},
394 };
395 MODULE_DEVICE_TABLE(platform, cht_wc_i2c_adap_id_table);
396
397 static struct platform_driver cht_wc_i2c_adap_driver = {
398 .probe = cht_wc_i2c_adap_i2c_probe,
399 .remove = cht_wc_i2c_adap_i2c_remove,
400 .driver = {
401 .name = "cht_wcove_ext_chgr",
402 },
403 .id_table = cht_wc_i2c_adap_id_table,
404 };
405 module_platform_driver(cht_wc_i2c_adap_driver);
406
407 MODULE_DESCRIPTION("Intel CHT Whiskey Cove PMIC I2C Master driver");
408 MODULE_AUTHOR("Hans de Goede <hdegoede@redhat.com>");
409 MODULE_LICENSE("GPL");
410