1 /*
2 * Synopsys DesignWare I2C adapter driver (slave only).
3 *
4 * Based on the Synopsys DesignWare I2C adapter driver (master).
5 *
6 * Copyright (C) 2016 Synopsys Inc.
7 *
8 * ----------------------------------------------------------------------------
9 *
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License as published by
12 * the Free Software Foundation; either version 2 of the License, or
13 * (at your option) any later version.
14 *
15 * This program is distributed in the hope that it will be useful,
16 * but WITHOUT ANY WARRANTY; without even the implied warranty of
17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 * GNU General Public License for more details.
19 * ----------------------------------------------------------------------------
20 *
21 */
22 #include <linux/delay.h>
23 #include <linux/err.h>
24 #include <linux/errno.h>
25 #include <linux/i2c.h>
26 #include <linux/interrupt.h>
27 #include <linux/io.h>
28 #include <linux/module.h>
29 #include <linux/pm_runtime.h>
30
31 #include "i2c-designware-core.h"
32
i2c_dw_configure_fifo_slave(struct dw_i2c_dev * dev)33 static void i2c_dw_configure_fifo_slave(struct dw_i2c_dev *dev)
34 {
35 /* Configure Tx/Rx FIFO threshold levels. */
36 dw_writel(dev, 0, DW_IC_TX_TL);
37 dw_writel(dev, 0, DW_IC_RX_TL);
38
39 /* Configure the I2C slave. */
40 dw_writel(dev, dev->slave_cfg, DW_IC_CON);
41 dw_writel(dev, DW_IC_INTR_SLAVE_MASK, DW_IC_INTR_MASK);
42 }
43
44 /**
45 * i2c_dw_init_slave() - Initialize the designware i2c slave hardware
46 * @dev: device private data
47 *
48 * This function configures and enables the I2C in slave mode.
49 * This function is called during I2C init function, and in case of timeout at
50 * run time.
51 */
i2c_dw_init_slave(struct dw_i2c_dev * dev)52 static int i2c_dw_init_slave(struct dw_i2c_dev *dev)
53 {
54 u32 sda_falling_time, scl_falling_time;
55 u32 reg, comp_param1;
56 u32 hcnt, lcnt;
57 int ret;
58
59 ret = i2c_dw_acquire_lock(dev);
60 if (ret)
61 return ret;
62
63 reg = dw_readl(dev, DW_IC_COMP_TYPE);
64 if (reg == ___constant_swab32(DW_IC_COMP_TYPE_VALUE)) {
65 /* Configure register endianness access. */
66 dev->flags |= ACCESS_SWAP;
67 } else if (reg == (DW_IC_COMP_TYPE_VALUE & 0x0000ffff)) {
68 /* Configure register access mode 16bit. */
69 dev->flags |= ACCESS_16BIT;
70 } else if (reg != DW_IC_COMP_TYPE_VALUE) {
71 dev_err(dev->dev,
72 "Unknown Synopsys component type: 0x%08x\n", reg);
73 i2c_dw_release_lock(dev);
74 return -ENODEV;
75 }
76
77 comp_param1 = dw_readl(dev, DW_IC_COMP_PARAM_1);
78
79 /* Disable the adapter. */
80 __i2c_dw_enable_and_wait(dev, false);
81
82 /* Set standard and fast speed deviders for high/low periods. */
83 sda_falling_time = dev->sda_falling_time ?: 300; /* ns */
84 scl_falling_time = dev->scl_falling_time ?: 300; /* ns */
85
86 /* Set SCL timing parameters for standard-mode. */
87 if (dev->ss_hcnt && dev->ss_lcnt) {
88 hcnt = dev->ss_hcnt;
89 lcnt = dev->ss_lcnt;
90 } else {
91 hcnt = i2c_dw_scl_hcnt(i2c_dw_clk_rate(dev),
92 4000, /* tHD;STA = tHIGH = 4.0 us */
93 sda_falling_time,
94 0, /* 0: DW default, 1: Ideal */
95 0); /* No offset */
96 lcnt = i2c_dw_scl_lcnt(i2c_dw_clk_rate(dev),
97 4700, /* tLOW = 4.7 us */
98 scl_falling_time,
99 0); /* No offset */
100 }
101 dw_writel(dev, hcnt, DW_IC_SS_SCL_HCNT);
102 dw_writel(dev, lcnt, DW_IC_SS_SCL_LCNT);
103 dev_dbg(dev->dev, "Standard-mode HCNT:LCNT = %d:%d\n", hcnt, lcnt);
104
105 /* Set SCL timing parameters for fast-mode or fast-mode plus. */
106 if ((dev->clk_freq == 1000000) && dev->fp_hcnt && dev->fp_lcnt) {
107 hcnt = dev->fp_hcnt;
108 lcnt = dev->fp_lcnt;
109 } else if (dev->fs_hcnt && dev->fs_lcnt) {
110 hcnt = dev->fs_hcnt;
111 lcnt = dev->fs_lcnt;
112 } else {
113 hcnt = i2c_dw_scl_hcnt(i2c_dw_clk_rate(dev),
114 600, /* tHD;STA = tHIGH = 0.6 us */
115 sda_falling_time,
116 0, /* 0: DW default, 1: Ideal */
117 0); /* No offset */
118 lcnt = i2c_dw_scl_lcnt(i2c_dw_clk_rate(dev),
119 1300, /* tLOW = 1.3 us */
120 scl_falling_time,
121 0); /* No offset */
122 }
123 dw_writel(dev, hcnt, DW_IC_FS_SCL_HCNT);
124 dw_writel(dev, lcnt, DW_IC_FS_SCL_LCNT);
125 dev_dbg(dev->dev, "Fast-mode HCNT:LCNT = %d:%d\n", hcnt, lcnt);
126
127 if ((dev->slave_cfg & DW_IC_CON_SPEED_MASK) ==
128 DW_IC_CON_SPEED_HIGH) {
129 if ((comp_param1 & DW_IC_COMP_PARAM_1_SPEED_MODE_MASK)
130 != DW_IC_COMP_PARAM_1_SPEED_MODE_HIGH) {
131 dev_err(dev->dev, "High Speed not supported!\n");
132 dev->slave_cfg &= ~DW_IC_CON_SPEED_MASK;
133 dev->slave_cfg |= DW_IC_CON_SPEED_FAST;
134 } else if (dev->hs_hcnt && dev->hs_lcnt) {
135 hcnt = dev->hs_hcnt;
136 lcnt = dev->hs_lcnt;
137 dw_writel(dev, hcnt, DW_IC_HS_SCL_HCNT);
138 dw_writel(dev, lcnt, DW_IC_HS_SCL_LCNT);
139 dev_dbg(dev->dev, "HighSpeed-mode HCNT:LCNT = %d:%d\n",
140 hcnt, lcnt);
141 }
142 }
143
144 /* Configure SDA Hold Time if required. */
145 reg = dw_readl(dev, DW_IC_COMP_VERSION);
146 if (reg >= DW_IC_SDA_HOLD_MIN_VERS) {
147 if (!dev->sda_hold_time) {
148 /* Keep previous hold time setting if no one set it. */
149 dev->sda_hold_time = dw_readl(dev, DW_IC_SDA_HOLD);
150 }
151 /*
152 * Workaround for avoiding TX arbitration lost in case I2C
153 * slave pulls SDA down "too quickly" after falling egde of
154 * SCL by enabling non-zero SDA RX hold. Specification says it
155 * extends incoming SDA low to high transition while SCL is
156 * high but it apprears to help also above issue.
157 */
158 if (!(dev->sda_hold_time & DW_IC_SDA_HOLD_RX_MASK))
159 dev->sda_hold_time |= 1 << DW_IC_SDA_HOLD_RX_SHIFT;
160 dw_writel(dev, dev->sda_hold_time, DW_IC_SDA_HOLD);
161 } else {
162 dev_warn(dev->dev,
163 "Hardware too old to adjust SDA hold time.\n");
164 }
165
166 i2c_dw_configure_fifo_slave(dev);
167 i2c_dw_release_lock(dev);
168
169 return 0;
170 }
171
i2c_dw_reg_slave(struct i2c_client * slave)172 static int i2c_dw_reg_slave(struct i2c_client *slave)
173 {
174 struct dw_i2c_dev *dev = i2c_get_adapdata(slave->adapter);
175
176 if (dev->slave)
177 return -EBUSY;
178 if (slave->flags & I2C_CLIENT_TEN)
179 return -EAFNOSUPPORT;
180 pm_runtime_get_sync(dev->dev);
181
182 /*
183 * Set slave address in the IC_SAR register,
184 * the address to which the DW_apb_i2c responds.
185 */
186 __i2c_dw_enable(dev, false);
187 dw_writel(dev, slave->addr, DW_IC_SAR);
188 dev->slave = slave;
189
190 __i2c_dw_enable(dev, true);
191
192 dev->cmd_err = 0;
193 dev->msg_write_idx = 0;
194 dev->msg_read_idx = 0;
195 dev->msg_err = 0;
196 dev->status = STATUS_IDLE;
197 dev->abort_source = 0;
198 dev->rx_outstanding = 0;
199
200 return 0;
201 }
202
i2c_dw_unreg_slave(struct i2c_client * slave)203 static int i2c_dw_unreg_slave(struct i2c_client *slave)
204 {
205 struct dw_i2c_dev *dev = i2c_get_adapdata(slave->adapter);
206
207 dev->disable_int(dev);
208 dev->disable(dev);
209 synchronize_irq(dev->irq);
210 dev->slave = NULL;
211 pm_runtime_put(dev->dev);
212
213 return 0;
214 }
215
i2c_dw_read_clear_intrbits_slave(struct dw_i2c_dev * dev)216 static u32 i2c_dw_read_clear_intrbits_slave(struct dw_i2c_dev *dev)
217 {
218 u32 stat;
219
220 /*
221 * The IC_INTR_STAT register just indicates "enabled" interrupts.
222 * Ths unmasked raw version of interrupt status bits are available
223 * in the IC_RAW_INTR_STAT register.
224 *
225 * That is,
226 * stat = dw_readl(IC_INTR_STAT);
227 * equals to,
228 * stat = dw_readl(IC_RAW_INTR_STAT) & dw_readl(IC_INTR_MASK);
229 *
230 * The raw version might be useful for debugging purposes.
231 */
232 stat = dw_readl(dev, DW_IC_INTR_STAT);
233
234 /*
235 * Do not use the IC_CLR_INTR register to clear interrupts, or
236 * you'll miss some interrupts, triggered during the period from
237 * dw_readl(IC_INTR_STAT) to dw_readl(IC_CLR_INTR).
238 *
239 * Instead, use the separately-prepared IC_CLR_* registers.
240 */
241 if (stat & DW_IC_INTR_TX_ABRT)
242 dw_readl(dev, DW_IC_CLR_TX_ABRT);
243 if (stat & DW_IC_INTR_RX_UNDER)
244 dw_readl(dev, DW_IC_CLR_RX_UNDER);
245 if (stat & DW_IC_INTR_RX_OVER)
246 dw_readl(dev, DW_IC_CLR_RX_OVER);
247 if (stat & DW_IC_INTR_TX_OVER)
248 dw_readl(dev, DW_IC_CLR_TX_OVER);
249 if (stat & DW_IC_INTR_RX_DONE)
250 dw_readl(dev, DW_IC_CLR_RX_DONE);
251 if (stat & DW_IC_INTR_ACTIVITY)
252 dw_readl(dev, DW_IC_CLR_ACTIVITY);
253 if (stat & DW_IC_INTR_STOP_DET)
254 dw_readl(dev, DW_IC_CLR_STOP_DET);
255 if (stat & DW_IC_INTR_START_DET)
256 dw_readl(dev, DW_IC_CLR_START_DET);
257 if (stat & DW_IC_INTR_GEN_CALL)
258 dw_readl(dev, DW_IC_CLR_GEN_CALL);
259
260 return stat;
261 }
262
263 /*
264 * Interrupt service routine. This gets called whenever an I2C slave interrupt
265 * occurs.
266 */
267
i2c_dw_irq_handler_slave(struct dw_i2c_dev * dev)268 static int i2c_dw_irq_handler_slave(struct dw_i2c_dev *dev)
269 {
270 u32 raw_stat, stat, enabled;
271 u8 val, slave_activity;
272
273 stat = dw_readl(dev, DW_IC_INTR_STAT);
274 enabled = dw_readl(dev, DW_IC_ENABLE);
275 raw_stat = dw_readl(dev, DW_IC_RAW_INTR_STAT);
276 slave_activity = ((dw_readl(dev, DW_IC_STATUS) &
277 DW_IC_STATUS_SLAVE_ACTIVITY) >> 6);
278
279 if (!enabled || !(raw_stat & ~DW_IC_INTR_ACTIVITY) || !dev->slave)
280 return 0;
281
282 dev_dbg(dev->dev,
283 "%#x STATUS SLAVE_ACTIVITY=%#x : RAW_INTR_STAT=%#x : INTR_STAT=%#x\n",
284 enabled, slave_activity, raw_stat, stat);
285
286 if ((stat & DW_IC_INTR_RX_FULL) && (stat & DW_IC_INTR_STOP_DET))
287 i2c_slave_event(dev->slave, I2C_SLAVE_WRITE_REQUESTED, &val);
288
289 if (stat & DW_IC_INTR_RD_REQ) {
290 if (slave_activity) {
291 if (stat & DW_IC_INTR_RX_FULL) {
292 val = dw_readl(dev, DW_IC_DATA_CMD);
293
294 if (!i2c_slave_event(dev->slave,
295 I2C_SLAVE_WRITE_RECEIVED,
296 &val)) {
297 dev_vdbg(dev->dev, "Byte %X acked!",
298 val);
299 }
300 dw_readl(dev, DW_IC_CLR_RD_REQ);
301 stat = i2c_dw_read_clear_intrbits_slave(dev);
302 } else {
303 dw_readl(dev, DW_IC_CLR_RD_REQ);
304 dw_readl(dev, DW_IC_CLR_RX_UNDER);
305 stat = i2c_dw_read_clear_intrbits_slave(dev);
306 }
307 if (!i2c_slave_event(dev->slave,
308 I2C_SLAVE_READ_REQUESTED,
309 &val))
310 dw_writel(dev, val, DW_IC_DATA_CMD);
311 }
312 }
313
314 if (stat & DW_IC_INTR_RX_DONE) {
315 if (!i2c_slave_event(dev->slave, I2C_SLAVE_READ_PROCESSED,
316 &val))
317 dw_readl(dev, DW_IC_CLR_RX_DONE);
318
319 i2c_slave_event(dev->slave, I2C_SLAVE_STOP, &val);
320 stat = i2c_dw_read_clear_intrbits_slave(dev);
321 return 1;
322 }
323
324 if (stat & DW_IC_INTR_RX_FULL) {
325 val = dw_readl(dev, DW_IC_DATA_CMD);
326 if (!i2c_slave_event(dev->slave, I2C_SLAVE_WRITE_RECEIVED,
327 &val))
328 dev_vdbg(dev->dev, "Byte %X acked!", val);
329 } else {
330 i2c_slave_event(dev->slave, I2C_SLAVE_STOP, &val);
331 stat = i2c_dw_read_clear_intrbits_slave(dev);
332 }
333
334 return 1;
335 }
336
i2c_dw_isr_slave(int this_irq,void * dev_id)337 static irqreturn_t i2c_dw_isr_slave(int this_irq, void *dev_id)
338 {
339 struct dw_i2c_dev *dev = dev_id;
340 int ret;
341
342 i2c_dw_read_clear_intrbits_slave(dev);
343 ret = i2c_dw_irq_handler_slave(dev);
344 if (ret > 0)
345 complete(&dev->cmd_complete);
346
347 return IRQ_RETVAL(ret);
348 }
349
350 static const struct i2c_algorithm i2c_dw_algo = {
351 .functionality = i2c_dw_func,
352 .reg_slave = i2c_dw_reg_slave,
353 .unreg_slave = i2c_dw_unreg_slave,
354 };
355
i2c_dw_probe_slave(struct dw_i2c_dev * dev)356 int i2c_dw_probe_slave(struct dw_i2c_dev *dev)
357 {
358 struct i2c_adapter *adap = &dev->adapter;
359 int ret;
360
361 init_completion(&dev->cmd_complete);
362
363 dev->init = i2c_dw_init_slave;
364 dev->disable = i2c_dw_disable;
365 dev->disable_int = i2c_dw_disable_int;
366
367 ret = dev->init(dev);
368 if (ret)
369 return ret;
370
371 snprintf(adap->name, sizeof(adap->name),
372 "Synopsys DesignWare I2C Slave adapter");
373 adap->retries = 3;
374 adap->algo = &i2c_dw_algo;
375 adap->dev.parent = dev->dev;
376 i2c_set_adapdata(adap, dev);
377
378 ret = devm_request_irq(dev->dev, dev->irq, i2c_dw_isr_slave,
379 IRQF_SHARED, dev_name(dev->dev), dev);
380 if (ret) {
381 dev_err(dev->dev, "failure requesting irq %i: %d\n",
382 dev->irq, ret);
383 return ret;
384 }
385
386 ret = i2c_add_numbered_adapter(adap);
387 if (ret)
388 dev_err(dev->dev, "failure adding adapter: %d\n", ret);
389
390 return ret;
391 }
392 EXPORT_SYMBOL_GPL(i2c_dw_probe_slave);
393
394 MODULE_AUTHOR("Luis Oliveira <lolivei@synopsys.com>");
395 MODULE_DESCRIPTION("Synopsys DesignWare I2C bus slave adapter");
396 MODULE_LICENSE("GPL v2");
397