1 /*
2 * drivers/i2c/busses/i2c-tegra.c
3 *
4 * Copyright (C) 2010 Google, Inc.
5 * Author: Colin Cross <ccross@android.com>
6 *
7 * This software is licensed under the terms of the GNU General Public
8 * License version 2, as published by the Free Software Foundation, and
9 * may be copied, distributed, and modified under those terms.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 *
16 */
17
18 #include <linux/kernel.h>
19 #include <linux/init.h>
20 #include <linux/platform_device.h>
21 #include <linux/clk.h>
22 #include <linux/err.h>
23 #include <linux/i2c.h>
24 #include <linux/io.h>
25 #include <linux/interrupt.h>
26 #include <linux/delay.h>
27 #include <linux/slab.h>
28 #include <linux/of_device.h>
29 #include <linux/module.h>
30 #include <linux/reset.h>
31 #include <linux/pinctrl/consumer.h>
32 #include <linux/pm_runtime.h>
33 #include <linux/iopoll.h>
34
35 #include <asm/unaligned.h>
36
37 #define TEGRA_I2C_TIMEOUT (msecs_to_jiffies(1000))
38 #define BYTES_PER_FIFO_WORD 4
39
40 #define I2C_CNFG 0x000
41 #define I2C_CNFG_DEBOUNCE_CNT_SHIFT 12
42 #define I2C_CNFG_PACKET_MODE_EN BIT(10)
43 #define I2C_CNFG_NEW_MASTER_FSM BIT(11)
44 #define I2C_CNFG_MULTI_MASTER_MODE BIT(17)
45 #define I2C_STATUS 0x01C
46 #define I2C_SL_CNFG 0x020
47 #define I2C_SL_CNFG_NACK BIT(1)
48 #define I2C_SL_CNFG_NEWSL BIT(2)
49 #define I2C_SL_ADDR1 0x02c
50 #define I2C_SL_ADDR2 0x030
51 #define I2C_TX_FIFO 0x050
52 #define I2C_RX_FIFO 0x054
53 #define I2C_PACKET_TRANSFER_STATUS 0x058
54 #define I2C_FIFO_CONTROL 0x05c
55 #define I2C_FIFO_CONTROL_TX_FLUSH BIT(1)
56 #define I2C_FIFO_CONTROL_RX_FLUSH BIT(0)
57 #define I2C_FIFO_CONTROL_TX_TRIG_SHIFT 5
58 #define I2C_FIFO_CONTROL_RX_TRIG_SHIFT 2
59 #define I2C_FIFO_STATUS 0x060
60 #define I2C_FIFO_STATUS_TX_MASK 0xF0
61 #define I2C_FIFO_STATUS_TX_SHIFT 4
62 #define I2C_FIFO_STATUS_RX_MASK 0x0F
63 #define I2C_FIFO_STATUS_RX_SHIFT 0
64 #define I2C_INT_MASK 0x064
65 #define I2C_INT_STATUS 0x068
66 #define I2C_INT_PACKET_XFER_COMPLETE BIT(7)
67 #define I2C_INT_ALL_PACKETS_XFER_COMPLETE BIT(6)
68 #define I2C_INT_TX_FIFO_OVERFLOW BIT(5)
69 #define I2C_INT_RX_FIFO_UNDERFLOW BIT(4)
70 #define I2C_INT_NO_ACK BIT(3)
71 #define I2C_INT_ARBITRATION_LOST BIT(2)
72 #define I2C_INT_TX_FIFO_DATA_REQ BIT(1)
73 #define I2C_INT_RX_FIFO_DATA_REQ BIT(0)
74 #define I2C_CLK_DIVISOR 0x06c
75 #define I2C_CLK_DIVISOR_STD_FAST_MODE_SHIFT 16
76 #define I2C_CLK_MULTIPLIER_STD_FAST_MODE 8
77
78 #define DVC_CTRL_REG1 0x000
79 #define DVC_CTRL_REG1_INTR_EN BIT(10)
80 #define DVC_CTRL_REG2 0x004
81 #define DVC_CTRL_REG3 0x008
82 #define DVC_CTRL_REG3_SW_PROG BIT(26)
83 #define DVC_CTRL_REG3_I2C_DONE_INTR_EN BIT(30)
84 #define DVC_STATUS 0x00c
85 #define DVC_STATUS_I2C_DONE_INTR BIT(30)
86
87 #define I2C_ERR_NONE 0x00
88 #define I2C_ERR_NO_ACK 0x01
89 #define I2C_ERR_ARBITRATION_LOST 0x02
90 #define I2C_ERR_UNKNOWN_INTERRUPT 0x04
91
92 #define PACKET_HEADER0_HEADER_SIZE_SHIFT 28
93 #define PACKET_HEADER0_PACKET_ID_SHIFT 16
94 #define PACKET_HEADER0_CONT_ID_SHIFT 12
95 #define PACKET_HEADER0_PROTOCOL_I2C BIT(4)
96
97 #define I2C_HEADER_HIGHSPEED_MODE BIT(22)
98 #define I2C_HEADER_CONT_ON_NAK BIT(21)
99 #define I2C_HEADER_SEND_START_BYTE BIT(20)
100 #define I2C_HEADER_READ BIT(19)
101 #define I2C_HEADER_10BIT_ADDR BIT(18)
102 #define I2C_HEADER_IE_ENABLE BIT(17)
103 #define I2C_HEADER_REPEAT_START BIT(16)
104 #define I2C_HEADER_CONTINUE_XFER BIT(15)
105 #define I2C_HEADER_MASTER_ADDR_SHIFT 12
106 #define I2C_HEADER_SLAVE_ADDR_SHIFT 1
107
108 #define I2C_CONFIG_LOAD 0x08C
109 #define I2C_MSTR_CONFIG_LOAD BIT(0)
110 #define I2C_SLV_CONFIG_LOAD BIT(1)
111 #define I2C_TIMEOUT_CONFIG_LOAD BIT(2)
112
113 #define I2C_CLKEN_OVERRIDE 0x090
114 #define I2C_MST_CORE_CLKEN_OVR BIT(0)
115
116 #define I2C_CONFIG_LOAD_TIMEOUT 1000000
117
118 /*
119 * msg_end_type: The bus control which need to be send at end of transfer.
120 * @MSG_END_STOP: Send stop pulse at end of transfer.
121 * @MSG_END_REPEAT_START: Send repeat start at end of transfer.
122 * @MSG_END_CONTINUE: The following on message is coming and so do not send
123 * stop or repeat start.
124 */
125 enum msg_end_type {
126 MSG_END_STOP,
127 MSG_END_REPEAT_START,
128 MSG_END_CONTINUE,
129 };
130
131 /**
132 * struct tegra_i2c_hw_feature : Different HW support on Tegra
133 * @has_continue_xfer_support: Continue transfer supports.
134 * @has_per_pkt_xfer_complete_irq: Has enable/disable capability for transfer
135 * complete interrupt per packet basis.
136 * @has_single_clk_source: The i2c controller has single clock source. Tegra30
137 * and earlier Socs has two clock sources i.e. div-clk and
138 * fast-clk.
139 * @has_config_load_reg: Has the config load register to load the new
140 * configuration.
141 * @clk_divisor_hs_mode: Clock divisor in HS mode.
142 * @clk_divisor_std_fast_mode: Clock divisor in standard/fast mode. It is
143 * applicable if there is no fast clock source i.e. single clock
144 * source.
145 */
146
147 struct tegra_i2c_hw_feature {
148 bool has_continue_xfer_support;
149 bool has_per_pkt_xfer_complete_irq;
150 bool has_single_clk_source;
151 bool has_config_load_reg;
152 int clk_divisor_hs_mode;
153 int clk_divisor_std_fast_mode;
154 u16 clk_divisor_fast_plus_mode;
155 bool has_multi_master_mode;
156 bool has_slcg_override_reg;
157 };
158
159 /**
160 * struct tegra_i2c_dev - per device i2c context
161 * @dev: device reference for power management
162 * @hw: Tegra i2c hw feature.
163 * @adapter: core i2c layer adapter information
164 * @div_clk: clock reference for div clock of i2c controller.
165 * @fast_clk: clock reference for fast clock of i2c controller.
166 * @base: ioremapped registers cookie
167 * @cont_id: i2c controller id, used for for packet header
168 * @irq: irq number of transfer complete interrupt
169 * @is_dvc: identifies the DVC i2c controller, has a different register layout
170 * @msg_complete: transfer completion notifier
171 * @msg_err: error code for completed message
172 * @msg_buf: pointer to current message data
173 * @msg_buf_remaining: size of unsent data in the message buffer
174 * @msg_read: identifies read transfers
175 * @bus_clk_rate: current i2c bus clock rate
176 * @is_suspended: prevents i2c controller accesses after suspend is called
177 */
178 struct tegra_i2c_dev {
179 struct device *dev;
180 const struct tegra_i2c_hw_feature *hw;
181 struct i2c_adapter adapter;
182 struct clk *div_clk;
183 struct clk *fast_clk;
184 struct reset_control *rst;
185 void __iomem *base;
186 int cont_id;
187 int irq;
188 bool irq_disabled;
189 int is_dvc;
190 struct completion msg_complete;
191 int msg_err;
192 u8 *msg_buf;
193 size_t msg_buf_remaining;
194 int msg_read;
195 u32 bus_clk_rate;
196 u16 clk_divisor_non_hs_mode;
197 bool is_suspended;
198 bool is_multimaster_mode;
199 spinlock_t xfer_lock;
200 };
201
dvc_writel(struct tegra_i2c_dev * i2c_dev,u32 val,unsigned long reg)202 static void dvc_writel(struct tegra_i2c_dev *i2c_dev, u32 val,
203 unsigned long reg)
204 {
205 writel(val, i2c_dev->base + reg);
206 }
207
dvc_readl(struct tegra_i2c_dev * i2c_dev,unsigned long reg)208 static u32 dvc_readl(struct tegra_i2c_dev *i2c_dev, unsigned long reg)
209 {
210 return readl(i2c_dev->base + reg);
211 }
212
213 /*
214 * i2c_writel and i2c_readl will offset the register if necessary to talk
215 * to the I2C block inside the DVC block
216 */
tegra_i2c_reg_addr(struct tegra_i2c_dev * i2c_dev,unsigned long reg)217 static unsigned long tegra_i2c_reg_addr(struct tegra_i2c_dev *i2c_dev,
218 unsigned long reg)
219 {
220 if (i2c_dev->is_dvc)
221 reg += (reg >= I2C_TX_FIFO) ? 0x10 : 0x40;
222 return reg;
223 }
224
i2c_writel(struct tegra_i2c_dev * i2c_dev,u32 val,unsigned long reg)225 static void i2c_writel(struct tegra_i2c_dev *i2c_dev, u32 val,
226 unsigned long reg)
227 {
228 writel(val, i2c_dev->base + tegra_i2c_reg_addr(i2c_dev, reg));
229
230 /* Read back register to make sure that register writes completed */
231 if (reg != I2C_TX_FIFO)
232 readl(i2c_dev->base + tegra_i2c_reg_addr(i2c_dev, reg));
233 }
234
i2c_readl(struct tegra_i2c_dev * i2c_dev,unsigned long reg)235 static u32 i2c_readl(struct tegra_i2c_dev *i2c_dev, unsigned long reg)
236 {
237 return readl(i2c_dev->base + tegra_i2c_reg_addr(i2c_dev, reg));
238 }
239
i2c_writesl(struct tegra_i2c_dev * i2c_dev,void * data,unsigned long reg,int len)240 static void i2c_writesl(struct tegra_i2c_dev *i2c_dev, void *data,
241 unsigned long reg, int len)
242 {
243 writesl(i2c_dev->base + tegra_i2c_reg_addr(i2c_dev, reg), data, len);
244 }
245
i2c_readsl(struct tegra_i2c_dev * i2c_dev,void * data,unsigned long reg,int len)246 static void i2c_readsl(struct tegra_i2c_dev *i2c_dev, void *data,
247 unsigned long reg, int len)
248 {
249 readsl(i2c_dev->base + tegra_i2c_reg_addr(i2c_dev, reg), data, len);
250 }
251
tegra_i2c_mask_irq(struct tegra_i2c_dev * i2c_dev,u32 mask)252 static void tegra_i2c_mask_irq(struct tegra_i2c_dev *i2c_dev, u32 mask)
253 {
254 u32 int_mask;
255
256 int_mask = i2c_readl(i2c_dev, I2C_INT_MASK) & ~mask;
257 i2c_writel(i2c_dev, int_mask, I2C_INT_MASK);
258 }
259
tegra_i2c_unmask_irq(struct tegra_i2c_dev * i2c_dev,u32 mask)260 static void tegra_i2c_unmask_irq(struct tegra_i2c_dev *i2c_dev, u32 mask)
261 {
262 u32 int_mask;
263
264 int_mask = i2c_readl(i2c_dev, I2C_INT_MASK) | mask;
265 i2c_writel(i2c_dev, int_mask, I2C_INT_MASK);
266 }
267
tegra_i2c_flush_fifos(struct tegra_i2c_dev * i2c_dev)268 static int tegra_i2c_flush_fifos(struct tegra_i2c_dev *i2c_dev)
269 {
270 unsigned long timeout = jiffies + HZ;
271 u32 val = i2c_readl(i2c_dev, I2C_FIFO_CONTROL);
272
273 val |= I2C_FIFO_CONTROL_TX_FLUSH | I2C_FIFO_CONTROL_RX_FLUSH;
274 i2c_writel(i2c_dev, val, I2C_FIFO_CONTROL);
275
276 while (i2c_readl(i2c_dev, I2C_FIFO_CONTROL) &
277 (I2C_FIFO_CONTROL_TX_FLUSH | I2C_FIFO_CONTROL_RX_FLUSH)) {
278 if (time_after(jiffies, timeout)) {
279 dev_warn(i2c_dev->dev, "timeout waiting for fifo flush\n");
280 return -ETIMEDOUT;
281 }
282 msleep(1);
283 }
284 return 0;
285 }
286
tegra_i2c_empty_rx_fifo(struct tegra_i2c_dev * i2c_dev)287 static int tegra_i2c_empty_rx_fifo(struct tegra_i2c_dev *i2c_dev)
288 {
289 u32 val;
290 int rx_fifo_avail;
291 u8 *buf = i2c_dev->msg_buf;
292 size_t buf_remaining = i2c_dev->msg_buf_remaining;
293 int words_to_transfer;
294
295 val = i2c_readl(i2c_dev, I2C_FIFO_STATUS);
296 rx_fifo_avail = (val & I2C_FIFO_STATUS_RX_MASK) >>
297 I2C_FIFO_STATUS_RX_SHIFT;
298
299 /* Rounds down to not include partial word at the end of buf */
300 words_to_transfer = buf_remaining / BYTES_PER_FIFO_WORD;
301 if (words_to_transfer > rx_fifo_avail)
302 words_to_transfer = rx_fifo_avail;
303
304 i2c_readsl(i2c_dev, buf, I2C_RX_FIFO, words_to_transfer);
305
306 buf += words_to_transfer * BYTES_PER_FIFO_WORD;
307 buf_remaining -= words_to_transfer * BYTES_PER_FIFO_WORD;
308 rx_fifo_avail -= words_to_transfer;
309
310 /*
311 * If there is a partial word at the end of buf, handle it manually to
312 * prevent overwriting past the end of buf
313 */
314 if (rx_fifo_avail > 0 && buf_remaining > 0) {
315 BUG_ON(buf_remaining > 3);
316 val = i2c_readl(i2c_dev, I2C_RX_FIFO);
317 val = cpu_to_le32(val);
318 memcpy(buf, &val, buf_remaining);
319 buf_remaining = 0;
320 rx_fifo_avail--;
321 }
322
323 BUG_ON(rx_fifo_avail > 0 && buf_remaining > 0);
324 i2c_dev->msg_buf_remaining = buf_remaining;
325 i2c_dev->msg_buf = buf;
326 return 0;
327 }
328
tegra_i2c_fill_tx_fifo(struct tegra_i2c_dev * i2c_dev)329 static int tegra_i2c_fill_tx_fifo(struct tegra_i2c_dev *i2c_dev)
330 {
331 u32 val;
332 int tx_fifo_avail;
333 u8 *buf = i2c_dev->msg_buf;
334 size_t buf_remaining = i2c_dev->msg_buf_remaining;
335 int words_to_transfer;
336
337 val = i2c_readl(i2c_dev, I2C_FIFO_STATUS);
338 tx_fifo_avail = (val & I2C_FIFO_STATUS_TX_MASK) >>
339 I2C_FIFO_STATUS_TX_SHIFT;
340
341 /* Rounds down to not include partial word at the end of buf */
342 words_to_transfer = buf_remaining / BYTES_PER_FIFO_WORD;
343
344 /* It's very common to have < 4 bytes, so optimize that case. */
345 if (words_to_transfer) {
346 if (words_to_transfer > tx_fifo_avail)
347 words_to_transfer = tx_fifo_avail;
348
349 /*
350 * Update state before writing to FIFO. If this casues us
351 * to finish writing all bytes (AKA buf_remaining goes to 0) we
352 * have a potential for an interrupt (PACKET_XFER_COMPLETE is
353 * not maskable). We need to make sure that the isr sees
354 * buf_remaining as 0 and doesn't call us back re-entrantly.
355 */
356 buf_remaining -= words_to_transfer * BYTES_PER_FIFO_WORD;
357 tx_fifo_avail -= words_to_transfer;
358 i2c_dev->msg_buf_remaining = buf_remaining;
359 i2c_dev->msg_buf = buf +
360 words_to_transfer * BYTES_PER_FIFO_WORD;
361 barrier();
362
363 i2c_writesl(i2c_dev, buf, I2C_TX_FIFO, words_to_transfer);
364
365 buf += words_to_transfer * BYTES_PER_FIFO_WORD;
366 }
367
368 /*
369 * If there is a partial word at the end of buf, handle it manually to
370 * prevent reading past the end of buf, which could cross a page
371 * boundary and fault.
372 */
373 if (tx_fifo_avail > 0 && buf_remaining > 0) {
374 BUG_ON(buf_remaining > 3);
375 memcpy(&val, buf, buf_remaining);
376 val = le32_to_cpu(val);
377
378 /* Again update before writing to FIFO to make sure isr sees. */
379 i2c_dev->msg_buf_remaining = 0;
380 i2c_dev->msg_buf = NULL;
381 barrier();
382
383 i2c_writel(i2c_dev, val, I2C_TX_FIFO);
384 }
385
386 return 0;
387 }
388
389 /*
390 * One of the Tegra I2C blocks is inside the DVC (Digital Voltage Controller)
391 * block. This block is identical to the rest of the I2C blocks, except that
392 * it only supports master mode, it has registers moved around, and it needs
393 * some extra init to get it into I2C mode. The register moves are handled
394 * by i2c_readl and i2c_writel
395 */
tegra_dvc_init(struct tegra_i2c_dev * i2c_dev)396 static void tegra_dvc_init(struct tegra_i2c_dev *i2c_dev)
397 {
398 u32 val;
399
400 val = dvc_readl(i2c_dev, DVC_CTRL_REG3);
401 val |= DVC_CTRL_REG3_SW_PROG;
402 val |= DVC_CTRL_REG3_I2C_DONE_INTR_EN;
403 dvc_writel(i2c_dev, val, DVC_CTRL_REG3);
404
405 val = dvc_readl(i2c_dev, DVC_CTRL_REG1);
406 val |= DVC_CTRL_REG1_INTR_EN;
407 dvc_writel(i2c_dev, val, DVC_CTRL_REG1);
408 }
409
tegra_i2c_runtime_resume(struct device * dev)410 static int tegra_i2c_runtime_resume(struct device *dev)
411 {
412 struct tegra_i2c_dev *i2c_dev = dev_get_drvdata(dev);
413 int ret;
414
415 ret = pinctrl_pm_select_default_state(i2c_dev->dev);
416 if (ret)
417 return ret;
418
419 if (!i2c_dev->hw->has_single_clk_source) {
420 ret = clk_enable(i2c_dev->fast_clk);
421 if (ret < 0) {
422 dev_err(i2c_dev->dev,
423 "Enabling fast clk failed, err %d\n", ret);
424 return ret;
425 }
426 }
427
428 ret = clk_enable(i2c_dev->div_clk);
429 if (ret < 0) {
430 dev_err(i2c_dev->dev,
431 "Enabling div clk failed, err %d\n", ret);
432 clk_disable(i2c_dev->fast_clk);
433 return ret;
434 }
435
436 return 0;
437 }
438
tegra_i2c_runtime_suspend(struct device * dev)439 static int tegra_i2c_runtime_suspend(struct device *dev)
440 {
441 struct tegra_i2c_dev *i2c_dev = dev_get_drvdata(dev);
442
443 clk_disable(i2c_dev->div_clk);
444 if (!i2c_dev->hw->has_single_clk_source)
445 clk_disable(i2c_dev->fast_clk);
446
447 return pinctrl_pm_select_idle_state(i2c_dev->dev);
448 }
449
tegra_i2c_wait_for_config_load(struct tegra_i2c_dev * i2c_dev)450 static int tegra_i2c_wait_for_config_load(struct tegra_i2c_dev *i2c_dev)
451 {
452 unsigned long reg_offset;
453 void __iomem *addr;
454 u32 val;
455 int err;
456
457 if (i2c_dev->hw->has_config_load_reg) {
458 reg_offset = tegra_i2c_reg_addr(i2c_dev, I2C_CONFIG_LOAD);
459 addr = i2c_dev->base + reg_offset;
460 i2c_writel(i2c_dev, I2C_MSTR_CONFIG_LOAD, I2C_CONFIG_LOAD);
461 if (in_interrupt())
462 err = readl_poll_timeout_atomic(addr, val, val == 0,
463 1000, I2C_CONFIG_LOAD_TIMEOUT);
464 else
465 err = readl_poll_timeout(addr, val, val == 0,
466 1000, I2C_CONFIG_LOAD_TIMEOUT);
467
468 if (err) {
469 dev_warn(i2c_dev->dev,
470 "timeout waiting for config load\n");
471 return err;
472 }
473 }
474
475 return 0;
476 }
477
tegra_i2c_init(struct tegra_i2c_dev * i2c_dev)478 static int tegra_i2c_init(struct tegra_i2c_dev *i2c_dev)
479 {
480 u32 val;
481 int err;
482 u32 clk_divisor;
483
484 err = pm_runtime_get_sync(i2c_dev->dev);
485 if (err < 0) {
486 dev_err(i2c_dev->dev, "runtime resume failed %d\n", err);
487 return err;
488 }
489
490 reset_control_assert(i2c_dev->rst);
491 udelay(2);
492 reset_control_deassert(i2c_dev->rst);
493
494 if (i2c_dev->is_dvc)
495 tegra_dvc_init(i2c_dev);
496
497 val = I2C_CNFG_NEW_MASTER_FSM | I2C_CNFG_PACKET_MODE_EN |
498 (0x2 << I2C_CNFG_DEBOUNCE_CNT_SHIFT);
499
500 if (i2c_dev->hw->has_multi_master_mode)
501 val |= I2C_CNFG_MULTI_MASTER_MODE;
502
503 i2c_writel(i2c_dev, val, I2C_CNFG);
504 i2c_writel(i2c_dev, 0, I2C_INT_MASK);
505
506 /* Make sure clock divisor programmed correctly */
507 clk_divisor = i2c_dev->hw->clk_divisor_hs_mode;
508 clk_divisor |= i2c_dev->clk_divisor_non_hs_mode <<
509 I2C_CLK_DIVISOR_STD_FAST_MODE_SHIFT;
510 i2c_writel(i2c_dev, clk_divisor, I2C_CLK_DIVISOR);
511
512 if (!i2c_dev->is_dvc) {
513 u32 sl_cfg = i2c_readl(i2c_dev, I2C_SL_CNFG);
514
515 sl_cfg |= I2C_SL_CNFG_NACK | I2C_SL_CNFG_NEWSL;
516 i2c_writel(i2c_dev, sl_cfg, I2C_SL_CNFG);
517 i2c_writel(i2c_dev, 0xfc, I2C_SL_ADDR1);
518 i2c_writel(i2c_dev, 0x00, I2C_SL_ADDR2);
519 }
520
521 val = 7 << I2C_FIFO_CONTROL_TX_TRIG_SHIFT |
522 0 << I2C_FIFO_CONTROL_RX_TRIG_SHIFT;
523 i2c_writel(i2c_dev, val, I2C_FIFO_CONTROL);
524
525 err = tegra_i2c_flush_fifos(i2c_dev);
526 if (err)
527 goto err;
528
529 if (i2c_dev->is_multimaster_mode && i2c_dev->hw->has_slcg_override_reg)
530 i2c_writel(i2c_dev, I2C_MST_CORE_CLKEN_OVR, I2C_CLKEN_OVERRIDE);
531
532 err = tegra_i2c_wait_for_config_load(i2c_dev);
533 if (err)
534 goto err;
535
536 if (i2c_dev->irq_disabled) {
537 i2c_dev->irq_disabled = false;
538 enable_irq(i2c_dev->irq);
539 }
540
541 err:
542 pm_runtime_put(i2c_dev->dev);
543 return err;
544 }
545
tegra_i2c_disable_packet_mode(struct tegra_i2c_dev * i2c_dev)546 static int tegra_i2c_disable_packet_mode(struct tegra_i2c_dev *i2c_dev)
547 {
548 u32 cnfg;
549
550 /*
551 * NACK interrupt is generated before the I2C controller generates
552 * the STOP condition on the bus. So wait for 2 clock periods
553 * before disabling the controller so that the STOP condition has
554 * been delivered properly.
555 */
556 udelay(DIV_ROUND_UP(2 * 1000000, i2c_dev->bus_clk_rate));
557
558 cnfg = i2c_readl(i2c_dev, I2C_CNFG);
559 if (cnfg & I2C_CNFG_PACKET_MODE_EN)
560 i2c_writel(i2c_dev, cnfg & ~I2C_CNFG_PACKET_MODE_EN, I2C_CNFG);
561
562 return tegra_i2c_wait_for_config_load(i2c_dev);
563 }
564
tegra_i2c_isr(int irq,void * dev_id)565 static irqreturn_t tegra_i2c_isr(int irq, void *dev_id)
566 {
567 u32 status;
568 const u32 status_err = I2C_INT_NO_ACK | I2C_INT_ARBITRATION_LOST;
569 struct tegra_i2c_dev *i2c_dev = dev_id;
570 unsigned long flags;
571
572 status = i2c_readl(i2c_dev, I2C_INT_STATUS);
573
574 spin_lock_irqsave(&i2c_dev->xfer_lock, flags);
575 if (status == 0) {
576 dev_warn(i2c_dev->dev, "irq status 0 %08x %08x %08x\n",
577 i2c_readl(i2c_dev, I2C_PACKET_TRANSFER_STATUS),
578 i2c_readl(i2c_dev, I2C_STATUS),
579 i2c_readl(i2c_dev, I2C_CNFG));
580 i2c_dev->msg_err |= I2C_ERR_UNKNOWN_INTERRUPT;
581
582 if (!i2c_dev->irq_disabled) {
583 disable_irq_nosync(i2c_dev->irq);
584 i2c_dev->irq_disabled = true;
585 }
586 goto err;
587 }
588
589 if (unlikely(status & status_err)) {
590 tegra_i2c_disable_packet_mode(i2c_dev);
591 if (status & I2C_INT_NO_ACK)
592 i2c_dev->msg_err |= I2C_ERR_NO_ACK;
593 if (status & I2C_INT_ARBITRATION_LOST)
594 i2c_dev->msg_err |= I2C_ERR_ARBITRATION_LOST;
595 goto err;
596 }
597
598 if (i2c_dev->msg_read && (status & I2C_INT_RX_FIFO_DATA_REQ)) {
599 if (i2c_dev->msg_buf_remaining)
600 tegra_i2c_empty_rx_fifo(i2c_dev);
601 else
602 BUG();
603 }
604
605 if (!i2c_dev->msg_read && (status & I2C_INT_TX_FIFO_DATA_REQ)) {
606 if (i2c_dev->msg_buf_remaining)
607 tegra_i2c_fill_tx_fifo(i2c_dev);
608 else
609 tegra_i2c_mask_irq(i2c_dev, I2C_INT_TX_FIFO_DATA_REQ);
610 }
611
612 i2c_writel(i2c_dev, status, I2C_INT_STATUS);
613 if (i2c_dev->is_dvc)
614 dvc_writel(i2c_dev, DVC_STATUS_I2C_DONE_INTR, DVC_STATUS);
615
616 if (status & I2C_INT_PACKET_XFER_COMPLETE) {
617 BUG_ON(i2c_dev->msg_buf_remaining);
618 complete(&i2c_dev->msg_complete);
619 }
620 goto done;
621 err:
622 /* An error occurred, mask all interrupts */
623 tegra_i2c_mask_irq(i2c_dev, I2C_INT_NO_ACK | I2C_INT_ARBITRATION_LOST |
624 I2C_INT_PACKET_XFER_COMPLETE | I2C_INT_TX_FIFO_DATA_REQ |
625 I2C_INT_RX_FIFO_DATA_REQ);
626 i2c_writel(i2c_dev, status, I2C_INT_STATUS);
627 if (i2c_dev->is_dvc)
628 dvc_writel(i2c_dev, DVC_STATUS_I2C_DONE_INTR, DVC_STATUS);
629
630 complete(&i2c_dev->msg_complete);
631 done:
632 spin_unlock_irqrestore(&i2c_dev->xfer_lock, flags);
633 return IRQ_HANDLED;
634 }
635
tegra_i2c_xfer_msg(struct tegra_i2c_dev * i2c_dev,struct i2c_msg * msg,enum msg_end_type end_state)636 static int tegra_i2c_xfer_msg(struct tegra_i2c_dev *i2c_dev,
637 struct i2c_msg *msg, enum msg_end_type end_state)
638 {
639 u32 packet_header;
640 u32 int_mask;
641 unsigned long time_left;
642 unsigned long flags;
643
644 tegra_i2c_flush_fifos(i2c_dev);
645
646 if (msg->len == 0)
647 return -EINVAL;
648
649 i2c_dev->msg_buf = msg->buf;
650 i2c_dev->msg_buf_remaining = msg->len;
651 i2c_dev->msg_err = I2C_ERR_NONE;
652 i2c_dev->msg_read = (msg->flags & I2C_M_RD);
653 reinit_completion(&i2c_dev->msg_complete);
654
655 spin_lock_irqsave(&i2c_dev->xfer_lock, flags);
656
657 int_mask = I2C_INT_NO_ACK | I2C_INT_ARBITRATION_LOST;
658 tegra_i2c_unmask_irq(i2c_dev, int_mask);
659
660 packet_header = (0 << PACKET_HEADER0_HEADER_SIZE_SHIFT) |
661 PACKET_HEADER0_PROTOCOL_I2C |
662 (i2c_dev->cont_id << PACKET_HEADER0_CONT_ID_SHIFT) |
663 (1 << PACKET_HEADER0_PACKET_ID_SHIFT);
664 i2c_writel(i2c_dev, packet_header, I2C_TX_FIFO);
665
666 packet_header = msg->len - 1;
667 i2c_writel(i2c_dev, packet_header, I2C_TX_FIFO);
668
669 packet_header = I2C_HEADER_IE_ENABLE;
670 if (end_state == MSG_END_CONTINUE)
671 packet_header |= I2C_HEADER_CONTINUE_XFER;
672 else if (end_state == MSG_END_REPEAT_START)
673 packet_header |= I2C_HEADER_REPEAT_START;
674 if (msg->flags & I2C_M_TEN) {
675 packet_header |= msg->addr;
676 packet_header |= I2C_HEADER_10BIT_ADDR;
677 } else {
678 packet_header |= msg->addr << I2C_HEADER_SLAVE_ADDR_SHIFT;
679 }
680 if (msg->flags & I2C_M_IGNORE_NAK)
681 packet_header |= I2C_HEADER_CONT_ON_NAK;
682 if (msg->flags & I2C_M_RD)
683 packet_header |= I2C_HEADER_READ;
684 i2c_writel(i2c_dev, packet_header, I2C_TX_FIFO);
685
686 if (!(msg->flags & I2C_M_RD))
687 tegra_i2c_fill_tx_fifo(i2c_dev);
688
689 if (i2c_dev->hw->has_per_pkt_xfer_complete_irq)
690 int_mask |= I2C_INT_PACKET_XFER_COMPLETE;
691 if (msg->flags & I2C_M_RD)
692 int_mask |= I2C_INT_RX_FIFO_DATA_REQ;
693 else if (i2c_dev->msg_buf_remaining)
694 int_mask |= I2C_INT_TX_FIFO_DATA_REQ;
695
696 tegra_i2c_unmask_irq(i2c_dev, int_mask);
697 spin_unlock_irqrestore(&i2c_dev->xfer_lock, flags);
698 dev_dbg(i2c_dev->dev, "unmasked irq: %02x\n",
699 i2c_readl(i2c_dev, I2C_INT_MASK));
700
701 time_left = wait_for_completion_timeout(&i2c_dev->msg_complete,
702 TEGRA_I2C_TIMEOUT);
703 tegra_i2c_mask_irq(i2c_dev, int_mask);
704
705 if (time_left == 0) {
706 dev_err(i2c_dev->dev, "i2c transfer timed out\n");
707
708 tegra_i2c_init(i2c_dev);
709 return -ETIMEDOUT;
710 }
711
712 dev_dbg(i2c_dev->dev, "transfer complete: %lu %d %d\n",
713 time_left, completion_done(&i2c_dev->msg_complete),
714 i2c_dev->msg_err);
715
716 if (likely(i2c_dev->msg_err == I2C_ERR_NONE))
717 return 0;
718
719 tegra_i2c_init(i2c_dev);
720 if (i2c_dev->msg_err == I2C_ERR_NO_ACK) {
721 if (msg->flags & I2C_M_IGNORE_NAK)
722 return 0;
723 return -EREMOTEIO;
724 }
725
726 return -EIO;
727 }
728
tegra_i2c_xfer(struct i2c_adapter * adap,struct i2c_msg msgs[],int num)729 static int tegra_i2c_xfer(struct i2c_adapter *adap, struct i2c_msg msgs[],
730 int num)
731 {
732 struct tegra_i2c_dev *i2c_dev = i2c_get_adapdata(adap);
733 int i;
734 int ret = 0;
735
736 if (i2c_dev->is_suspended)
737 return -EBUSY;
738
739 ret = pm_runtime_get_sync(i2c_dev->dev);
740 if (ret < 0) {
741 dev_err(i2c_dev->dev, "runtime resume failed %d\n", ret);
742 return ret;
743 }
744
745 for (i = 0; i < num; i++) {
746 enum msg_end_type end_type = MSG_END_STOP;
747
748 if (i < (num - 1)) {
749 if (msgs[i + 1].flags & I2C_M_NOSTART)
750 end_type = MSG_END_CONTINUE;
751 else
752 end_type = MSG_END_REPEAT_START;
753 }
754 ret = tegra_i2c_xfer_msg(i2c_dev, &msgs[i], end_type);
755 if (ret)
756 break;
757 }
758
759 pm_runtime_put(i2c_dev->dev);
760
761 return ret ?: i;
762 }
763
tegra_i2c_func(struct i2c_adapter * adap)764 static u32 tegra_i2c_func(struct i2c_adapter *adap)
765 {
766 struct tegra_i2c_dev *i2c_dev = i2c_get_adapdata(adap);
767 u32 ret = I2C_FUNC_I2C | (I2C_FUNC_SMBUS_EMUL & ~I2C_FUNC_SMBUS_QUICK) |
768 I2C_FUNC_10BIT_ADDR | I2C_FUNC_PROTOCOL_MANGLING;
769
770 if (i2c_dev->hw->has_continue_xfer_support)
771 ret |= I2C_FUNC_NOSTART;
772 return ret;
773 }
774
tegra_i2c_parse_dt(struct tegra_i2c_dev * i2c_dev)775 static void tegra_i2c_parse_dt(struct tegra_i2c_dev *i2c_dev)
776 {
777 struct device_node *np = i2c_dev->dev->of_node;
778 int ret;
779
780 ret = of_property_read_u32(np, "clock-frequency",
781 &i2c_dev->bus_clk_rate);
782 if (ret)
783 i2c_dev->bus_clk_rate = 100000; /* default clock rate */
784
785 i2c_dev->is_multimaster_mode = of_property_read_bool(np,
786 "multi-master");
787 }
788
789 static const struct i2c_algorithm tegra_i2c_algo = {
790 .master_xfer = tegra_i2c_xfer,
791 .functionality = tegra_i2c_func,
792 };
793
794 /* payload size is only 12 bit */
795 static const struct i2c_adapter_quirks tegra_i2c_quirks = {
796 .max_read_len = 4096,
797 .max_write_len = 4096 - 12,
798 };
799
800 static const struct tegra_i2c_hw_feature tegra20_i2c_hw = {
801 .has_continue_xfer_support = false,
802 .has_per_pkt_xfer_complete_irq = false,
803 .has_single_clk_source = false,
804 .clk_divisor_hs_mode = 3,
805 .clk_divisor_std_fast_mode = 0,
806 .clk_divisor_fast_plus_mode = 0,
807 .has_config_load_reg = false,
808 .has_multi_master_mode = false,
809 .has_slcg_override_reg = false,
810 };
811
812 static const struct tegra_i2c_hw_feature tegra30_i2c_hw = {
813 .has_continue_xfer_support = true,
814 .has_per_pkt_xfer_complete_irq = false,
815 .has_single_clk_source = false,
816 .clk_divisor_hs_mode = 3,
817 .clk_divisor_std_fast_mode = 0,
818 .clk_divisor_fast_plus_mode = 0,
819 .has_config_load_reg = false,
820 .has_multi_master_mode = false,
821 .has_slcg_override_reg = false,
822 };
823
824 static const struct tegra_i2c_hw_feature tegra114_i2c_hw = {
825 .has_continue_xfer_support = true,
826 .has_per_pkt_xfer_complete_irq = true,
827 .has_single_clk_source = true,
828 .clk_divisor_hs_mode = 1,
829 .clk_divisor_std_fast_mode = 0x19,
830 .clk_divisor_fast_plus_mode = 0x10,
831 .has_config_load_reg = false,
832 .has_multi_master_mode = false,
833 .has_slcg_override_reg = false,
834 };
835
836 static const struct tegra_i2c_hw_feature tegra124_i2c_hw = {
837 .has_continue_xfer_support = true,
838 .has_per_pkt_xfer_complete_irq = true,
839 .has_single_clk_source = true,
840 .clk_divisor_hs_mode = 1,
841 .clk_divisor_std_fast_mode = 0x19,
842 .clk_divisor_fast_plus_mode = 0x10,
843 .has_config_load_reg = true,
844 .has_multi_master_mode = false,
845 .has_slcg_override_reg = true,
846 };
847
848 static const struct tegra_i2c_hw_feature tegra210_i2c_hw = {
849 .has_continue_xfer_support = true,
850 .has_per_pkt_xfer_complete_irq = true,
851 .has_single_clk_source = true,
852 .clk_divisor_hs_mode = 1,
853 .clk_divisor_std_fast_mode = 0x19,
854 .clk_divisor_fast_plus_mode = 0x10,
855 .has_config_load_reg = true,
856 .has_multi_master_mode = true,
857 .has_slcg_override_reg = true,
858 };
859
860 /* Match table for of_platform binding */
861 static const struct of_device_id tegra_i2c_of_match[] = {
862 { .compatible = "nvidia,tegra210-i2c", .data = &tegra210_i2c_hw, },
863 { .compatible = "nvidia,tegra124-i2c", .data = &tegra124_i2c_hw, },
864 { .compatible = "nvidia,tegra114-i2c", .data = &tegra114_i2c_hw, },
865 { .compatible = "nvidia,tegra30-i2c", .data = &tegra30_i2c_hw, },
866 { .compatible = "nvidia,tegra20-i2c", .data = &tegra20_i2c_hw, },
867 { .compatible = "nvidia,tegra20-i2c-dvc", .data = &tegra20_i2c_hw, },
868 {},
869 };
870 MODULE_DEVICE_TABLE(of, tegra_i2c_of_match);
871
tegra_i2c_probe(struct platform_device * pdev)872 static int tegra_i2c_probe(struct platform_device *pdev)
873 {
874 struct tegra_i2c_dev *i2c_dev;
875 struct resource *res;
876 struct clk *div_clk;
877 struct clk *fast_clk;
878 void __iomem *base;
879 int irq;
880 int ret = 0;
881 int clk_multiplier = I2C_CLK_MULTIPLIER_STD_FAST_MODE;
882
883 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
884 base = devm_ioremap_resource(&pdev->dev, res);
885 if (IS_ERR(base))
886 return PTR_ERR(base);
887
888 res = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
889 if (!res) {
890 dev_err(&pdev->dev, "no irq resource\n");
891 return -EINVAL;
892 }
893 irq = res->start;
894
895 div_clk = devm_clk_get(&pdev->dev, "div-clk");
896 if (IS_ERR(div_clk)) {
897 dev_err(&pdev->dev, "missing controller clock\n");
898 return PTR_ERR(div_clk);
899 }
900
901 i2c_dev = devm_kzalloc(&pdev->dev, sizeof(*i2c_dev), GFP_KERNEL);
902 if (!i2c_dev)
903 return -ENOMEM;
904
905 i2c_dev->base = base;
906 i2c_dev->div_clk = div_clk;
907 i2c_dev->adapter.algo = &tegra_i2c_algo;
908 i2c_dev->adapter.quirks = &tegra_i2c_quirks;
909 i2c_dev->irq = irq;
910 i2c_dev->cont_id = pdev->id;
911 i2c_dev->dev = &pdev->dev;
912
913 i2c_dev->rst = devm_reset_control_get_exclusive(&pdev->dev, "i2c");
914 if (IS_ERR(i2c_dev->rst)) {
915 dev_err(&pdev->dev, "missing controller reset\n");
916 return PTR_ERR(i2c_dev->rst);
917 }
918
919 tegra_i2c_parse_dt(i2c_dev);
920
921 i2c_dev->hw = of_device_get_match_data(&pdev->dev);
922 i2c_dev->is_dvc = of_device_is_compatible(pdev->dev.of_node,
923 "nvidia,tegra20-i2c-dvc");
924 init_completion(&i2c_dev->msg_complete);
925 spin_lock_init(&i2c_dev->xfer_lock);
926
927 if (!i2c_dev->hw->has_single_clk_source) {
928 fast_clk = devm_clk_get(&pdev->dev, "fast-clk");
929 if (IS_ERR(fast_clk)) {
930 dev_err(&pdev->dev, "missing fast clock\n");
931 return PTR_ERR(fast_clk);
932 }
933 i2c_dev->fast_clk = fast_clk;
934 }
935
936 platform_set_drvdata(pdev, i2c_dev);
937
938 if (!i2c_dev->hw->has_single_clk_source) {
939 ret = clk_prepare(i2c_dev->fast_clk);
940 if (ret < 0) {
941 dev_err(i2c_dev->dev, "Clock prepare failed %d\n", ret);
942 return ret;
943 }
944 }
945
946 i2c_dev->clk_divisor_non_hs_mode =
947 i2c_dev->hw->clk_divisor_std_fast_mode;
948 if (i2c_dev->hw->clk_divisor_fast_plus_mode &&
949 (i2c_dev->bus_clk_rate == 1000000))
950 i2c_dev->clk_divisor_non_hs_mode =
951 i2c_dev->hw->clk_divisor_fast_plus_mode;
952
953 clk_multiplier *= (i2c_dev->clk_divisor_non_hs_mode + 1);
954 ret = clk_set_rate(i2c_dev->div_clk,
955 i2c_dev->bus_clk_rate * clk_multiplier);
956 if (ret) {
957 dev_err(i2c_dev->dev, "Clock rate change failed %d\n", ret);
958 goto unprepare_fast_clk;
959 }
960
961 ret = clk_prepare(i2c_dev->div_clk);
962 if (ret < 0) {
963 dev_err(i2c_dev->dev, "Clock prepare failed %d\n", ret);
964 goto unprepare_fast_clk;
965 }
966
967 pm_runtime_enable(&pdev->dev);
968 if (!pm_runtime_enabled(&pdev->dev)) {
969 ret = tegra_i2c_runtime_resume(&pdev->dev);
970 if (ret < 0) {
971 dev_err(&pdev->dev, "runtime resume failed\n");
972 goto unprepare_div_clk;
973 }
974 }
975
976 if (i2c_dev->is_multimaster_mode) {
977 ret = clk_enable(i2c_dev->div_clk);
978 if (ret < 0) {
979 dev_err(i2c_dev->dev, "div_clk enable failed %d\n",
980 ret);
981 goto disable_rpm;
982 }
983 }
984
985 ret = tegra_i2c_init(i2c_dev);
986 if (ret) {
987 dev_err(&pdev->dev, "Failed to initialize i2c controller\n");
988 goto disable_div_clk;
989 }
990
991 ret = devm_request_irq(&pdev->dev, i2c_dev->irq,
992 tegra_i2c_isr, 0, dev_name(&pdev->dev), i2c_dev);
993 if (ret) {
994 dev_err(&pdev->dev, "Failed to request irq %i\n", i2c_dev->irq);
995 goto disable_div_clk;
996 }
997
998 i2c_set_adapdata(&i2c_dev->adapter, i2c_dev);
999 i2c_dev->adapter.owner = THIS_MODULE;
1000 i2c_dev->adapter.class = I2C_CLASS_DEPRECATED;
1001 strlcpy(i2c_dev->adapter.name, dev_name(&pdev->dev),
1002 sizeof(i2c_dev->adapter.name));
1003 i2c_dev->adapter.dev.parent = &pdev->dev;
1004 i2c_dev->adapter.nr = pdev->id;
1005 i2c_dev->adapter.dev.of_node = pdev->dev.of_node;
1006
1007 ret = i2c_add_numbered_adapter(&i2c_dev->adapter);
1008 if (ret)
1009 goto disable_div_clk;
1010
1011 return 0;
1012
1013 disable_div_clk:
1014 if (i2c_dev->is_multimaster_mode)
1015 clk_disable(i2c_dev->div_clk);
1016
1017 disable_rpm:
1018 pm_runtime_disable(&pdev->dev);
1019 if (!pm_runtime_status_suspended(&pdev->dev))
1020 tegra_i2c_runtime_suspend(&pdev->dev);
1021
1022 unprepare_div_clk:
1023 clk_unprepare(i2c_dev->div_clk);
1024
1025 unprepare_fast_clk:
1026 if (!i2c_dev->hw->has_single_clk_source)
1027 clk_unprepare(i2c_dev->fast_clk);
1028
1029 return ret;
1030 }
1031
tegra_i2c_remove(struct platform_device * pdev)1032 static int tegra_i2c_remove(struct platform_device *pdev)
1033 {
1034 struct tegra_i2c_dev *i2c_dev = platform_get_drvdata(pdev);
1035
1036 i2c_del_adapter(&i2c_dev->adapter);
1037
1038 if (i2c_dev->is_multimaster_mode)
1039 clk_disable(i2c_dev->div_clk);
1040
1041 pm_runtime_disable(&pdev->dev);
1042 if (!pm_runtime_status_suspended(&pdev->dev))
1043 tegra_i2c_runtime_suspend(&pdev->dev);
1044
1045 clk_unprepare(i2c_dev->div_clk);
1046 if (!i2c_dev->hw->has_single_clk_source)
1047 clk_unprepare(i2c_dev->fast_clk);
1048
1049 return 0;
1050 }
1051
1052 #ifdef CONFIG_PM_SLEEP
tegra_i2c_suspend(struct device * dev)1053 static int tegra_i2c_suspend(struct device *dev)
1054 {
1055 struct tegra_i2c_dev *i2c_dev = dev_get_drvdata(dev);
1056
1057 i2c_lock_adapter(&i2c_dev->adapter);
1058 i2c_dev->is_suspended = true;
1059 i2c_unlock_adapter(&i2c_dev->adapter);
1060
1061 return 0;
1062 }
1063
tegra_i2c_resume(struct device * dev)1064 static int tegra_i2c_resume(struct device *dev)
1065 {
1066 struct tegra_i2c_dev *i2c_dev = dev_get_drvdata(dev);
1067 int ret;
1068
1069 i2c_lock_adapter(&i2c_dev->adapter);
1070
1071 ret = tegra_i2c_init(i2c_dev);
1072 if (!ret)
1073 i2c_dev->is_suspended = false;
1074
1075 i2c_unlock_adapter(&i2c_dev->adapter);
1076
1077 return ret;
1078 }
1079
1080 static const struct dev_pm_ops tegra_i2c_pm = {
1081 SET_RUNTIME_PM_OPS(tegra_i2c_runtime_suspend, tegra_i2c_runtime_resume,
1082 NULL)
1083 SET_SYSTEM_SLEEP_PM_OPS(tegra_i2c_suspend, tegra_i2c_resume)
1084 };
1085 #define TEGRA_I2C_PM (&tegra_i2c_pm)
1086 #else
1087 #define TEGRA_I2C_PM NULL
1088 #endif
1089
1090 static struct platform_driver tegra_i2c_driver = {
1091 .probe = tegra_i2c_probe,
1092 .remove = tegra_i2c_remove,
1093 .driver = {
1094 .name = "tegra-i2c",
1095 .of_match_table = tegra_i2c_of_match,
1096 .pm = TEGRA_I2C_PM,
1097 },
1098 };
1099
tegra_i2c_init_driver(void)1100 static int __init tegra_i2c_init_driver(void)
1101 {
1102 return platform_driver_register(&tegra_i2c_driver);
1103 }
1104
tegra_i2c_exit_driver(void)1105 static void __exit tegra_i2c_exit_driver(void)
1106 {
1107 platform_driver_unregister(&tegra_i2c_driver);
1108 }
1109
1110 subsys_initcall(tegra_i2c_init_driver);
1111 module_exit(tegra_i2c_exit_driver);
1112
1113 MODULE_DESCRIPTION("nVidia Tegra2 I2C Bus Controller driver");
1114 MODULE_AUTHOR("Colin Cross");
1115 MODULE_LICENSE("GPL v2");
1116