1 /*
2 * Driver for the ADC present in the Atmel AT91 evaluation boards.
3 *
4 * Copyright 2011 Free Electrons
5 *
6 * Licensed under the GPLv2 or later.
7 */
8
9 #include <linux/bitmap.h>
10 #include <linux/bitops.h>
11 #include <linux/clk.h>
12 #include <linux/err.h>
13 #include <linux/io.h>
14 #include <linux/input.h>
15 #include <linux/interrupt.h>
16 #include <linux/jiffies.h>
17 #include <linux/kernel.h>
18 #include <linux/module.h>
19 #include <linux/of.h>
20 #include <linux/of_device.h>
21 #include <linux/platform_device.h>
22 #include <linux/sched.h>
23 #include <linux/slab.h>
24 #include <linux/wait.h>
25
26 #include <linux/platform_data/at91_adc.h>
27
28 #include <linux/iio/iio.h>
29 #include <linux/iio/buffer.h>
30 #include <linux/iio/trigger.h>
31 #include <linux/iio/trigger_consumer.h>
32 #include <linux/iio/triggered_buffer.h>
33 #include <linux/pinctrl/consumer.h>
34
35 /* Registers */
36 #define AT91_ADC_CR 0x00 /* Control Register */
37 #define AT91_ADC_SWRST (1 << 0) /* Software Reset */
38 #define AT91_ADC_START (1 << 1) /* Start Conversion */
39
40 #define AT91_ADC_MR 0x04 /* Mode Register */
41 #define AT91_ADC_TSAMOD (3 << 0) /* ADC mode */
42 #define AT91_ADC_TSAMOD_ADC_ONLY_MODE (0 << 0) /* ADC Mode */
43 #define AT91_ADC_TSAMOD_TS_ONLY_MODE (1 << 0) /* Touch Screen Only Mode */
44 #define AT91_ADC_TRGEN (1 << 0) /* Trigger Enable */
45 #define AT91_ADC_TRGSEL (7 << 1) /* Trigger Selection */
46 #define AT91_ADC_TRGSEL_TC0 (0 << 1)
47 #define AT91_ADC_TRGSEL_TC1 (1 << 1)
48 #define AT91_ADC_TRGSEL_TC2 (2 << 1)
49 #define AT91_ADC_TRGSEL_EXTERNAL (6 << 1)
50 #define AT91_ADC_LOWRES (1 << 4) /* Low Resolution */
51 #define AT91_ADC_SLEEP (1 << 5) /* Sleep Mode */
52 #define AT91_ADC_PENDET (1 << 6) /* Pen contact detection enable */
53 #define AT91_ADC_PRESCAL_9260 (0x3f << 8) /* Prescalar Rate Selection */
54 #define AT91_ADC_PRESCAL_9G45 (0xff << 8)
55 #define AT91_ADC_PRESCAL_(x) ((x) << 8)
56 #define AT91_ADC_STARTUP_9260 (0x1f << 16) /* Startup Up Time */
57 #define AT91_ADC_STARTUP_9G45 (0x7f << 16)
58 #define AT91_ADC_STARTUP_9X5 (0xf << 16)
59 #define AT91_ADC_STARTUP_(x) ((x) << 16)
60 #define AT91_ADC_SHTIM (0xf << 24) /* Sample & Hold Time */
61 #define AT91_ADC_SHTIM_(x) ((x) << 24)
62 #define AT91_ADC_PENDBC (0x0f << 28) /* Pen Debounce time */
63 #define AT91_ADC_PENDBC_(x) ((x) << 28)
64
65 #define AT91_ADC_TSR 0x0C
66 #define AT91_ADC_TSR_SHTIM (0xf << 24) /* Sample & Hold Time */
67 #define AT91_ADC_TSR_SHTIM_(x) ((x) << 24)
68
69 #define AT91_ADC_CHER 0x10 /* Channel Enable Register */
70 #define AT91_ADC_CHDR 0x14 /* Channel Disable Register */
71 #define AT91_ADC_CHSR 0x18 /* Channel Status Register */
72 #define AT91_ADC_CH(n) (1 << (n)) /* Channel Number */
73
74 #define AT91_ADC_SR 0x1C /* Status Register */
75 #define AT91_ADC_EOC(n) (1 << (n)) /* End of Conversion on Channel N */
76 #define AT91_ADC_OVRE(n) (1 << ((n) + 8))/* Overrun Error on Channel N */
77 #define AT91_ADC_DRDY (1 << 16) /* Data Ready */
78 #define AT91_ADC_GOVRE (1 << 17) /* General Overrun Error */
79 #define AT91_ADC_ENDRX (1 << 18) /* End of RX Buffer */
80 #define AT91_ADC_RXFUFF (1 << 19) /* RX Buffer Full */
81
82 #define AT91_ADC_SR_9X5 0x30 /* Status Register for 9x5 */
83 #define AT91_ADC_SR_DRDY_9X5 (1 << 24) /* Data Ready */
84
85 #define AT91_ADC_LCDR 0x20 /* Last Converted Data Register */
86 #define AT91_ADC_LDATA (0x3ff)
87
88 #define AT91_ADC_IER 0x24 /* Interrupt Enable Register */
89 #define AT91_ADC_IDR 0x28 /* Interrupt Disable Register */
90 #define AT91_ADC_IMR 0x2C /* Interrupt Mask Register */
91 #define AT91RL_ADC_IER_PEN (1 << 20)
92 #define AT91RL_ADC_IER_NOPEN (1 << 21)
93 #define AT91_ADC_IER_PEN (1 << 29)
94 #define AT91_ADC_IER_NOPEN (1 << 30)
95 #define AT91_ADC_IER_XRDY (1 << 20)
96 #define AT91_ADC_IER_YRDY (1 << 21)
97 #define AT91_ADC_IER_PRDY (1 << 22)
98 #define AT91_ADC_ISR_PENS (1 << 31)
99
100 #define AT91_ADC_CHR(n) (0x30 + ((n) * 4)) /* Channel Data Register N */
101 #define AT91_ADC_DATA (0x3ff)
102
103 #define AT91_ADC_CDR0_9X5 (0x50) /* Channel Data Register 0 for 9X5 */
104
105 #define AT91_ADC_ACR 0x94 /* Analog Control Register */
106 #define AT91_ADC_ACR_PENDETSENS (0x3 << 0) /* pull-up resistor */
107
108 #define AT91_ADC_TSMR 0xB0
109 #define AT91_ADC_TSMR_TSMODE (3 << 0) /* Touch Screen Mode */
110 #define AT91_ADC_TSMR_TSMODE_NONE (0 << 0)
111 #define AT91_ADC_TSMR_TSMODE_4WIRE_NO_PRESS (1 << 0)
112 #define AT91_ADC_TSMR_TSMODE_4WIRE_PRESS (2 << 0)
113 #define AT91_ADC_TSMR_TSMODE_5WIRE (3 << 0)
114 #define AT91_ADC_TSMR_TSAV (3 << 4) /* Averages samples */
115 #define AT91_ADC_TSMR_TSAV_(x) ((x) << 4)
116 #define AT91_ADC_TSMR_SCTIM (0x0f << 16) /* Switch closure time */
117 #define AT91_ADC_TSMR_SCTIM_(x) ((x) << 16)
118 #define AT91_ADC_TSMR_PENDBC (0x0f << 28) /* Pen Debounce time */
119 #define AT91_ADC_TSMR_PENDBC_(x) ((x) << 28)
120 #define AT91_ADC_TSMR_NOTSDMA (1 << 22) /* No Touchscreen DMA */
121 #define AT91_ADC_TSMR_PENDET_DIS (0 << 24) /* Pen contact detection disable */
122 #define AT91_ADC_TSMR_PENDET_ENA (1 << 24) /* Pen contact detection enable */
123
124 #define AT91_ADC_TSXPOSR 0xB4
125 #define AT91_ADC_TSYPOSR 0xB8
126 #define AT91_ADC_TSPRESSR 0xBC
127
128 #define AT91_ADC_TRGR_9260 AT91_ADC_MR
129 #define AT91_ADC_TRGR_9G45 0x08
130 #define AT91_ADC_TRGR_9X5 0xC0
131
132 /* Trigger Register bit field */
133 #define AT91_ADC_TRGR_TRGPER (0xffff << 16)
134 #define AT91_ADC_TRGR_TRGPER_(x) ((x) << 16)
135 #define AT91_ADC_TRGR_TRGMOD (0x7 << 0)
136 #define AT91_ADC_TRGR_NONE (0 << 0)
137 #define AT91_ADC_TRGR_MOD_PERIOD_TRIG (5 << 0)
138
139 #define AT91_ADC_CHAN(st, ch) \
140 (st->registers->channel_base + (ch * 4))
141 #define at91_adc_readl(st, reg) \
142 (readl_relaxed(st->reg_base + reg))
143 #define at91_adc_writel(st, reg, val) \
144 (writel_relaxed(val, st->reg_base + reg))
145
146 #define DRIVER_NAME "at91_adc"
147 #define MAX_POS_BITS 12
148
149 #define TOUCH_SAMPLE_PERIOD_US 2000 /* 2ms */
150 #define TOUCH_PEN_DETECT_DEBOUNCE_US 200
151
152 #define MAX_RLPOS_BITS 10
153 #define TOUCH_SAMPLE_PERIOD_US_RL 10000 /* 10ms, the SoC can't keep up with 2ms */
154 #define TOUCH_SHTIM 0xa
155 #define TOUCH_SCTIM_US 10 /* 10us for the Touchscreen Switches Closure Time */
156
157 /**
158 * struct at91_adc_reg_desc - Various informations relative to registers
159 * @channel_base: Base offset for the channel data registers
160 * @drdy_mask: Mask of the DRDY field in the relevant registers
161 (Interruptions registers mostly)
162 * @status_register: Offset of the Interrupt Status Register
163 * @trigger_register: Offset of the Trigger setup register
164 * @mr_prescal_mask: Mask of the PRESCAL field in the adc MR register
165 * @mr_startup_mask: Mask of the STARTUP field in the adc MR register
166 */
167 struct at91_adc_reg_desc {
168 u8 channel_base;
169 u32 drdy_mask;
170 u8 status_register;
171 u8 trigger_register;
172 u32 mr_prescal_mask;
173 u32 mr_startup_mask;
174 };
175
176 struct at91_adc_caps {
177 bool has_ts; /* Support touch screen */
178 bool has_tsmr; /* only at91sam9x5, sama5d3 have TSMR reg */
179 /*
180 * Numbers of sampling data will be averaged. Can be 0~3.
181 * Hardware can average (2 ^ ts_filter_average) sample data.
182 */
183 u8 ts_filter_average;
184 /* Pen Detection input pull-up resistor, can be 0~3 */
185 u8 ts_pen_detect_sensitivity;
186
187 /* startup time calculate function */
188 u32 (*calc_startup_ticks)(u32 startup_time, u32 adc_clk_khz);
189
190 u8 num_channels;
191 struct at91_adc_reg_desc registers;
192 };
193
194 struct at91_adc_state {
195 struct clk *adc_clk;
196 u16 *buffer;
197 unsigned long channels_mask;
198 struct clk *clk;
199 bool done;
200 int irq;
201 u16 last_value;
202 int chnb;
203 struct mutex lock;
204 u8 num_channels;
205 void __iomem *reg_base;
206 struct at91_adc_reg_desc *registers;
207 u32 startup_time;
208 u8 sample_hold_time;
209 bool sleep_mode;
210 struct iio_trigger **trig;
211 struct at91_adc_trigger *trigger_list;
212 u32 trigger_number;
213 bool use_external;
214 u32 vref_mv;
215 u32 res; /* resolution used for convertions */
216 bool low_res; /* the resolution corresponds to the lowest one */
217 wait_queue_head_t wq_data_avail;
218 struct at91_adc_caps *caps;
219
220 /*
221 * Following ADC channels are shared by touchscreen:
222 *
223 * CH0 -- Touch screen XP/UL
224 * CH1 -- Touch screen XM/UR
225 * CH2 -- Touch screen YP/LL
226 * CH3 -- Touch screen YM/Sense
227 * CH4 -- Touch screen LR(5-wire only)
228 *
229 * The bitfields below represents the reserved channel in the
230 * touchscreen mode.
231 */
232 #define CHAN_MASK_TOUCHSCREEN_4WIRE (0xf << 0)
233 #define CHAN_MASK_TOUCHSCREEN_5WIRE (0x1f << 0)
234 enum atmel_adc_ts_type touchscreen_type;
235 struct input_dev *ts_input;
236
237 u16 ts_sample_period_val;
238 u32 ts_pressure_threshold;
239 u16 ts_pendbc;
240
241 bool ts_bufferedmeasure;
242 u32 ts_prev_absx;
243 u32 ts_prev_absy;
244 };
245
at91_adc_trigger_handler(int irq,void * p)246 static irqreturn_t at91_adc_trigger_handler(int irq, void *p)
247 {
248 struct iio_poll_func *pf = p;
249 struct iio_dev *idev = pf->indio_dev;
250 struct at91_adc_state *st = iio_priv(idev);
251 struct iio_chan_spec const *chan;
252 int i, j = 0;
253
254 for (i = 0; i < idev->masklength; i++) {
255 if (!test_bit(i, idev->active_scan_mask))
256 continue;
257 chan = idev->channels + i;
258 st->buffer[j] = at91_adc_readl(st, AT91_ADC_CHAN(st, chan->channel));
259 j++;
260 }
261
262 iio_push_to_buffers_with_timestamp(idev, st->buffer, pf->timestamp);
263
264 iio_trigger_notify_done(idev->trig);
265
266 /* Needed to ACK the DRDY interruption */
267 at91_adc_readl(st, AT91_ADC_LCDR);
268
269 enable_irq(st->irq);
270
271 return IRQ_HANDLED;
272 }
273
274 /* Handler for classic adc channel eoc trigger */
handle_adc_eoc_trigger(int irq,struct iio_dev * idev)275 static void handle_adc_eoc_trigger(int irq, struct iio_dev *idev)
276 {
277 struct at91_adc_state *st = iio_priv(idev);
278
279 if (iio_buffer_enabled(idev)) {
280 disable_irq_nosync(irq);
281 iio_trigger_poll(idev->trig);
282 } else {
283 st->last_value = at91_adc_readl(st, AT91_ADC_CHAN(st, st->chnb));
284 /* Needed to ACK the DRDY interruption */
285 at91_adc_readl(st, AT91_ADC_LCDR);
286 st->done = true;
287 wake_up_interruptible(&st->wq_data_avail);
288 }
289 }
290
at91_ts_sample(struct at91_adc_state * st)291 static int at91_ts_sample(struct at91_adc_state *st)
292 {
293 unsigned int xscale, yscale, reg, z1, z2;
294 unsigned int x, y, pres, xpos, ypos;
295 unsigned int rxp = 1;
296 unsigned int factor = 1000;
297 struct iio_dev *idev = iio_priv_to_dev(st);
298
299 unsigned int xyz_mask_bits = st->res;
300 unsigned int xyz_mask = (1 << xyz_mask_bits) - 1;
301
302 /* calculate position */
303 /* x position = (x / xscale) * max, max = 2^MAX_POS_BITS - 1 */
304 reg = at91_adc_readl(st, AT91_ADC_TSXPOSR);
305 xpos = reg & xyz_mask;
306 x = (xpos << MAX_POS_BITS) - xpos;
307 xscale = (reg >> 16) & xyz_mask;
308 if (xscale == 0) {
309 dev_err(&idev->dev, "Error: xscale == 0!\n");
310 return -1;
311 }
312 x /= xscale;
313
314 /* y position = (y / yscale) * max, max = 2^MAX_POS_BITS - 1 */
315 reg = at91_adc_readl(st, AT91_ADC_TSYPOSR);
316 ypos = reg & xyz_mask;
317 y = (ypos << MAX_POS_BITS) - ypos;
318 yscale = (reg >> 16) & xyz_mask;
319 if (yscale == 0) {
320 dev_err(&idev->dev, "Error: yscale == 0!\n");
321 return -1;
322 }
323 y /= yscale;
324
325 /* calculate the pressure */
326 reg = at91_adc_readl(st, AT91_ADC_TSPRESSR);
327 z1 = reg & xyz_mask;
328 z2 = (reg >> 16) & xyz_mask;
329
330 if (z1 != 0)
331 pres = rxp * (x * factor / 1024) * (z2 * factor / z1 - factor)
332 / factor;
333 else
334 pres = st->ts_pressure_threshold; /* no pen contacted */
335
336 dev_dbg(&idev->dev, "xpos = %d, xscale = %d, ypos = %d, yscale = %d, z1 = %d, z2 = %d, press = %d\n",
337 xpos, xscale, ypos, yscale, z1, z2, pres);
338
339 if (pres < st->ts_pressure_threshold) {
340 dev_dbg(&idev->dev, "x = %d, y = %d, pressure = %d\n",
341 x, y, pres / factor);
342 input_report_abs(st->ts_input, ABS_X, x);
343 input_report_abs(st->ts_input, ABS_Y, y);
344 input_report_abs(st->ts_input, ABS_PRESSURE, pres);
345 input_report_key(st->ts_input, BTN_TOUCH, 1);
346 input_sync(st->ts_input);
347 } else {
348 dev_dbg(&idev->dev, "pressure too low: not reporting\n");
349 }
350
351 return 0;
352 }
353
at91_adc_rl_interrupt(int irq,void * private)354 static irqreturn_t at91_adc_rl_interrupt(int irq, void *private)
355 {
356 struct iio_dev *idev = private;
357 struct at91_adc_state *st = iio_priv(idev);
358 u32 status = at91_adc_readl(st, st->registers->status_register);
359 unsigned int reg;
360
361 status &= at91_adc_readl(st, AT91_ADC_IMR);
362 if (status & GENMASK(st->num_channels - 1, 0))
363 handle_adc_eoc_trigger(irq, idev);
364
365 if (status & AT91RL_ADC_IER_PEN) {
366 /* Disabling pen debounce is required to get a NOPEN irq */
367 reg = at91_adc_readl(st, AT91_ADC_MR);
368 reg &= ~AT91_ADC_PENDBC;
369 at91_adc_writel(st, AT91_ADC_MR, reg);
370
371 at91_adc_writel(st, AT91_ADC_IDR, AT91RL_ADC_IER_PEN);
372 at91_adc_writel(st, AT91_ADC_IER, AT91RL_ADC_IER_NOPEN
373 | AT91_ADC_EOC(3));
374 /* Set up period trigger for sampling */
375 at91_adc_writel(st, st->registers->trigger_register,
376 AT91_ADC_TRGR_MOD_PERIOD_TRIG |
377 AT91_ADC_TRGR_TRGPER_(st->ts_sample_period_val));
378 } else if (status & AT91RL_ADC_IER_NOPEN) {
379 reg = at91_adc_readl(st, AT91_ADC_MR);
380 reg |= AT91_ADC_PENDBC_(st->ts_pendbc) & AT91_ADC_PENDBC;
381 at91_adc_writel(st, AT91_ADC_MR, reg);
382 at91_adc_writel(st, st->registers->trigger_register,
383 AT91_ADC_TRGR_NONE);
384
385 at91_adc_writel(st, AT91_ADC_IDR, AT91RL_ADC_IER_NOPEN
386 | AT91_ADC_EOC(3));
387 at91_adc_writel(st, AT91_ADC_IER, AT91RL_ADC_IER_PEN);
388 st->ts_bufferedmeasure = false;
389 input_report_key(st->ts_input, BTN_TOUCH, 0);
390 input_sync(st->ts_input);
391 } else if (status & AT91_ADC_EOC(3) && st->ts_input) {
392 /* Conversion finished and we've a touchscreen */
393 if (st->ts_bufferedmeasure) {
394 /*
395 * Last measurement is always discarded, since it can
396 * be erroneous.
397 * Always report previous measurement
398 */
399 input_report_abs(st->ts_input, ABS_X, st->ts_prev_absx);
400 input_report_abs(st->ts_input, ABS_Y, st->ts_prev_absy);
401 input_report_key(st->ts_input, BTN_TOUCH, 1);
402 input_sync(st->ts_input);
403 } else
404 st->ts_bufferedmeasure = true;
405
406 /* Now make new measurement */
407 st->ts_prev_absx = at91_adc_readl(st, AT91_ADC_CHAN(st, 3))
408 << MAX_RLPOS_BITS;
409 st->ts_prev_absx /= at91_adc_readl(st, AT91_ADC_CHAN(st, 2));
410
411 st->ts_prev_absy = at91_adc_readl(st, AT91_ADC_CHAN(st, 1))
412 << MAX_RLPOS_BITS;
413 st->ts_prev_absy /= at91_adc_readl(st, AT91_ADC_CHAN(st, 0));
414 }
415
416 return IRQ_HANDLED;
417 }
418
at91_adc_9x5_interrupt(int irq,void * private)419 static irqreturn_t at91_adc_9x5_interrupt(int irq, void *private)
420 {
421 struct iio_dev *idev = private;
422 struct at91_adc_state *st = iio_priv(idev);
423 u32 status = at91_adc_readl(st, st->registers->status_register);
424 const uint32_t ts_data_irq_mask =
425 AT91_ADC_IER_XRDY |
426 AT91_ADC_IER_YRDY |
427 AT91_ADC_IER_PRDY;
428
429 if (status & GENMASK(st->num_channels - 1, 0))
430 handle_adc_eoc_trigger(irq, idev);
431
432 if (status & AT91_ADC_IER_PEN) {
433 at91_adc_writel(st, AT91_ADC_IDR, AT91_ADC_IER_PEN);
434 at91_adc_writel(st, AT91_ADC_IER, AT91_ADC_IER_NOPEN |
435 ts_data_irq_mask);
436 /* Set up period trigger for sampling */
437 at91_adc_writel(st, st->registers->trigger_register,
438 AT91_ADC_TRGR_MOD_PERIOD_TRIG |
439 AT91_ADC_TRGR_TRGPER_(st->ts_sample_period_val));
440 } else if (status & AT91_ADC_IER_NOPEN) {
441 at91_adc_writel(st, st->registers->trigger_register, 0);
442 at91_adc_writel(st, AT91_ADC_IDR, AT91_ADC_IER_NOPEN |
443 ts_data_irq_mask);
444 at91_adc_writel(st, AT91_ADC_IER, AT91_ADC_IER_PEN);
445
446 input_report_key(st->ts_input, BTN_TOUCH, 0);
447 input_sync(st->ts_input);
448 } else if ((status & ts_data_irq_mask) == ts_data_irq_mask) {
449 /* Now all touchscreen data is ready */
450
451 if (status & AT91_ADC_ISR_PENS) {
452 /* validate data by pen contact */
453 at91_ts_sample(st);
454 } else {
455 /* triggered by event that is no pen contact, just read
456 * them to clean the interrupt and discard all.
457 */
458 at91_adc_readl(st, AT91_ADC_TSXPOSR);
459 at91_adc_readl(st, AT91_ADC_TSYPOSR);
460 at91_adc_readl(st, AT91_ADC_TSPRESSR);
461 }
462 }
463
464 return IRQ_HANDLED;
465 }
466
at91_adc_channel_init(struct iio_dev * idev)467 static int at91_adc_channel_init(struct iio_dev *idev)
468 {
469 struct at91_adc_state *st = iio_priv(idev);
470 struct iio_chan_spec *chan_array, *timestamp;
471 int bit, idx = 0;
472 unsigned long rsvd_mask = 0;
473
474 /* If touchscreen is enable, then reserve the adc channels */
475 if (st->touchscreen_type == ATMEL_ADC_TOUCHSCREEN_4WIRE)
476 rsvd_mask = CHAN_MASK_TOUCHSCREEN_4WIRE;
477 else if (st->touchscreen_type == ATMEL_ADC_TOUCHSCREEN_5WIRE)
478 rsvd_mask = CHAN_MASK_TOUCHSCREEN_5WIRE;
479
480 /* set up the channel mask to reserve touchscreen channels */
481 st->channels_mask &= ~rsvd_mask;
482
483 idev->num_channels = bitmap_weight(&st->channels_mask,
484 st->num_channels) + 1;
485
486 chan_array = devm_kzalloc(&idev->dev,
487 ((idev->num_channels + 1) *
488 sizeof(struct iio_chan_spec)),
489 GFP_KERNEL);
490
491 if (!chan_array)
492 return -ENOMEM;
493
494 for_each_set_bit(bit, &st->channels_mask, st->num_channels) {
495 struct iio_chan_spec *chan = chan_array + idx;
496
497 chan->type = IIO_VOLTAGE;
498 chan->indexed = 1;
499 chan->channel = bit;
500 chan->scan_index = idx;
501 chan->scan_type.sign = 'u';
502 chan->scan_type.realbits = st->res;
503 chan->scan_type.storagebits = 16;
504 chan->info_mask_shared_by_type = BIT(IIO_CHAN_INFO_SCALE);
505 chan->info_mask_separate = BIT(IIO_CHAN_INFO_RAW);
506 idx++;
507 }
508 timestamp = chan_array + idx;
509
510 timestamp->type = IIO_TIMESTAMP;
511 timestamp->channel = -1;
512 timestamp->scan_index = idx;
513 timestamp->scan_type.sign = 's';
514 timestamp->scan_type.realbits = 64;
515 timestamp->scan_type.storagebits = 64;
516
517 idev->channels = chan_array;
518 return idev->num_channels;
519 }
520
at91_adc_get_trigger_value_by_name(struct iio_dev * idev,struct at91_adc_trigger * triggers,const char * trigger_name)521 static int at91_adc_get_trigger_value_by_name(struct iio_dev *idev,
522 struct at91_adc_trigger *triggers,
523 const char *trigger_name)
524 {
525 struct at91_adc_state *st = iio_priv(idev);
526 int i;
527
528 for (i = 0; i < st->trigger_number; i++) {
529 char *name = kasprintf(GFP_KERNEL,
530 "%s-dev%d-%s",
531 idev->name,
532 idev->id,
533 triggers[i].name);
534 if (!name)
535 return -ENOMEM;
536
537 if (strcmp(trigger_name, name) == 0) {
538 kfree(name);
539 if (triggers[i].value == 0)
540 return -EINVAL;
541 return triggers[i].value;
542 }
543
544 kfree(name);
545 }
546
547 return -EINVAL;
548 }
549
at91_adc_configure_trigger(struct iio_trigger * trig,bool state)550 static int at91_adc_configure_trigger(struct iio_trigger *trig, bool state)
551 {
552 struct iio_dev *idev = iio_trigger_get_drvdata(trig);
553 struct at91_adc_state *st = iio_priv(idev);
554 struct at91_adc_reg_desc *reg = st->registers;
555 u32 status = at91_adc_readl(st, reg->trigger_register);
556 int value;
557 u8 bit;
558
559 value = at91_adc_get_trigger_value_by_name(idev,
560 st->trigger_list,
561 idev->trig->name);
562 if (value < 0)
563 return value;
564
565 if (state) {
566 st->buffer = kmalloc(idev->scan_bytes, GFP_KERNEL);
567 if (st->buffer == NULL)
568 return -ENOMEM;
569
570 at91_adc_writel(st, reg->trigger_register,
571 status | value);
572
573 for_each_set_bit(bit, idev->active_scan_mask,
574 st->num_channels) {
575 struct iio_chan_spec const *chan = idev->channels + bit;
576 at91_adc_writel(st, AT91_ADC_CHER,
577 AT91_ADC_CH(chan->channel));
578 }
579
580 at91_adc_writel(st, AT91_ADC_IER, reg->drdy_mask);
581
582 } else {
583 at91_adc_writel(st, AT91_ADC_IDR, reg->drdy_mask);
584
585 at91_adc_writel(st, reg->trigger_register,
586 status & ~value);
587
588 for_each_set_bit(bit, idev->active_scan_mask,
589 st->num_channels) {
590 struct iio_chan_spec const *chan = idev->channels + bit;
591 at91_adc_writel(st, AT91_ADC_CHDR,
592 AT91_ADC_CH(chan->channel));
593 }
594 kfree(st->buffer);
595 }
596
597 return 0;
598 }
599
600 static const struct iio_trigger_ops at91_adc_trigger_ops = {
601 .owner = THIS_MODULE,
602 .set_trigger_state = &at91_adc_configure_trigger,
603 };
604
at91_adc_allocate_trigger(struct iio_dev * idev,struct at91_adc_trigger * trigger)605 static struct iio_trigger *at91_adc_allocate_trigger(struct iio_dev *idev,
606 struct at91_adc_trigger *trigger)
607 {
608 struct iio_trigger *trig;
609 int ret;
610
611 trig = iio_trigger_alloc("%s-dev%d-%s", idev->name,
612 idev->id, trigger->name);
613 if (trig == NULL)
614 return NULL;
615
616 trig->dev.parent = idev->dev.parent;
617 iio_trigger_set_drvdata(trig, idev);
618 trig->ops = &at91_adc_trigger_ops;
619
620 ret = iio_trigger_register(trig);
621 if (ret)
622 return NULL;
623
624 return trig;
625 }
626
at91_adc_trigger_init(struct iio_dev * idev)627 static int at91_adc_trigger_init(struct iio_dev *idev)
628 {
629 struct at91_adc_state *st = iio_priv(idev);
630 int i, ret;
631
632 st->trig = devm_kzalloc(&idev->dev,
633 st->trigger_number * sizeof(*st->trig),
634 GFP_KERNEL);
635
636 if (st->trig == NULL) {
637 ret = -ENOMEM;
638 goto error_ret;
639 }
640
641 for (i = 0; i < st->trigger_number; i++) {
642 if (st->trigger_list[i].is_external && !(st->use_external))
643 continue;
644
645 st->trig[i] = at91_adc_allocate_trigger(idev,
646 st->trigger_list + i);
647 if (st->trig[i] == NULL) {
648 dev_err(&idev->dev,
649 "Could not allocate trigger %d\n", i);
650 ret = -ENOMEM;
651 goto error_trigger;
652 }
653 }
654
655 return 0;
656
657 error_trigger:
658 for (i--; i >= 0; i--) {
659 iio_trigger_unregister(st->trig[i]);
660 iio_trigger_free(st->trig[i]);
661 }
662 error_ret:
663 return ret;
664 }
665
at91_adc_trigger_remove(struct iio_dev * idev)666 static void at91_adc_trigger_remove(struct iio_dev *idev)
667 {
668 struct at91_adc_state *st = iio_priv(idev);
669 int i;
670
671 for (i = 0; i < st->trigger_number; i++) {
672 iio_trigger_unregister(st->trig[i]);
673 iio_trigger_free(st->trig[i]);
674 }
675 }
676
at91_adc_buffer_init(struct iio_dev * idev)677 static int at91_adc_buffer_init(struct iio_dev *idev)
678 {
679 return iio_triggered_buffer_setup(idev, &iio_pollfunc_store_time,
680 &at91_adc_trigger_handler, NULL);
681 }
682
at91_adc_buffer_remove(struct iio_dev * idev)683 static void at91_adc_buffer_remove(struct iio_dev *idev)
684 {
685 iio_triggered_buffer_cleanup(idev);
686 }
687
at91_adc_read_raw(struct iio_dev * idev,struct iio_chan_spec const * chan,int * val,int * val2,long mask)688 static int at91_adc_read_raw(struct iio_dev *idev,
689 struct iio_chan_spec const *chan,
690 int *val, int *val2, long mask)
691 {
692 struct at91_adc_state *st = iio_priv(idev);
693 int ret;
694
695 switch (mask) {
696 case IIO_CHAN_INFO_RAW:
697 mutex_lock(&st->lock);
698
699 st->chnb = chan->channel;
700 at91_adc_writel(st, AT91_ADC_CHER,
701 AT91_ADC_CH(chan->channel));
702 at91_adc_writel(st, AT91_ADC_IER, BIT(chan->channel));
703 at91_adc_writel(st, AT91_ADC_CR, AT91_ADC_START);
704
705 ret = wait_event_interruptible_timeout(st->wq_data_avail,
706 st->done,
707 msecs_to_jiffies(1000));
708
709 /* Disable interrupts, regardless if adc conversion was
710 * successful or not
711 */
712 at91_adc_writel(st, AT91_ADC_CHDR,
713 AT91_ADC_CH(chan->channel));
714 at91_adc_writel(st, AT91_ADC_IDR, BIT(chan->channel));
715
716 if (ret > 0) {
717 /* a valid conversion took place */
718 *val = st->last_value;
719 st->last_value = 0;
720 st->done = false;
721 ret = IIO_VAL_INT;
722 } else if (ret == 0) {
723 /* conversion timeout */
724 dev_err(&idev->dev, "ADC Channel %d timeout.\n",
725 chan->channel);
726 ret = -ETIMEDOUT;
727 }
728
729 mutex_unlock(&st->lock);
730 return ret;
731
732 case IIO_CHAN_INFO_SCALE:
733 *val = st->vref_mv;
734 *val2 = chan->scan_type.realbits;
735 return IIO_VAL_FRACTIONAL_LOG2;
736 default:
737 break;
738 }
739 return -EINVAL;
740 }
741
at91_adc_of_get_resolution(struct at91_adc_state * st,struct platform_device * pdev)742 static int at91_adc_of_get_resolution(struct at91_adc_state *st,
743 struct platform_device *pdev)
744 {
745 struct iio_dev *idev = iio_priv_to_dev(st);
746 struct device_node *np = pdev->dev.of_node;
747 int count, i, ret = 0;
748 char *res_name, *s;
749 u32 *resolutions;
750
751 count = of_property_count_strings(np, "atmel,adc-res-names");
752 if (count < 2) {
753 dev_err(&idev->dev, "You must specified at least two resolution names for "
754 "adc-res-names property in the DT\n");
755 return count;
756 }
757
758 resolutions = kmalloc_array(count, sizeof(*resolutions), GFP_KERNEL);
759 if (!resolutions)
760 return -ENOMEM;
761
762 if (of_property_read_u32_array(np, "atmel,adc-res", resolutions, count)) {
763 dev_err(&idev->dev, "Missing adc-res property in the DT.\n");
764 ret = -ENODEV;
765 goto ret;
766 }
767
768 if (of_property_read_string(np, "atmel,adc-use-res", (const char **)&res_name))
769 res_name = "highres";
770
771 for (i = 0; i < count; i++) {
772 if (of_property_read_string_index(np, "atmel,adc-res-names", i, (const char **)&s))
773 continue;
774
775 if (strcmp(res_name, s))
776 continue;
777
778 st->res = resolutions[i];
779 if (!strcmp(res_name, "lowres"))
780 st->low_res = true;
781 else
782 st->low_res = false;
783
784 dev_info(&idev->dev, "Resolution used: %u bits\n", st->res);
785 goto ret;
786 }
787
788 dev_err(&idev->dev, "There is no resolution for %s\n", res_name);
789
790 ret:
791 kfree(resolutions);
792 return ret;
793 }
794
calc_startup_ticks_9260(u32 startup_time,u32 adc_clk_khz)795 static u32 calc_startup_ticks_9260(u32 startup_time, u32 adc_clk_khz)
796 {
797 /*
798 * Number of ticks needed to cover the startup time of the ADC
799 * as defined in the electrical characteristics of the board,
800 * divided by 8. The formula thus is :
801 * Startup Time = (ticks + 1) * 8 / ADC Clock
802 */
803 return round_up((startup_time * adc_clk_khz / 1000) - 1, 8) / 8;
804 }
805
calc_startup_ticks_9x5(u32 startup_time,u32 adc_clk_khz)806 static u32 calc_startup_ticks_9x5(u32 startup_time, u32 adc_clk_khz)
807 {
808 /*
809 * For sama5d3x and at91sam9x5, the formula changes to:
810 * Startup Time = <lookup_table_value> / ADC Clock
811 */
812 static const int startup_lookup[] = {
813 0, 8, 16, 24,
814 64, 80, 96, 112,
815 512, 576, 640, 704,
816 768, 832, 896, 960
817 };
818 int i, size = ARRAY_SIZE(startup_lookup);
819 unsigned int ticks;
820
821 ticks = startup_time * adc_clk_khz / 1000;
822 for (i = 0; i < size; i++)
823 if (ticks < startup_lookup[i])
824 break;
825
826 ticks = i;
827 if (ticks == size)
828 /* Reach the end of lookup table */
829 ticks = size - 1;
830
831 return ticks;
832 }
833
834 static const struct of_device_id at91_adc_dt_ids[];
835
at91_adc_probe_dt_ts(struct device_node * node,struct at91_adc_state * st,struct device * dev)836 static int at91_adc_probe_dt_ts(struct device_node *node,
837 struct at91_adc_state *st, struct device *dev)
838 {
839 int ret;
840 u32 prop;
841
842 ret = of_property_read_u32(node, "atmel,adc-ts-wires", &prop);
843 if (ret) {
844 dev_info(dev, "ADC Touch screen is disabled.\n");
845 return 0;
846 }
847
848 switch (prop) {
849 case 4:
850 case 5:
851 st->touchscreen_type = prop;
852 break;
853 default:
854 dev_err(dev, "Unsupported number of touchscreen wires (%d). Should be 4 or 5.\n", prop);
855 return -EINVAL;
856 }
857
858 if (!st->caps->has_tsmr)
859 return 0;
860 prop = 0;
861 of_property_read_u32(node, "atmel,adc-ts-pressure-threshold", &prop);
862 st->ts_pressure_threshold = prop;
863 if (st->ts_pressure_threshold) {
864 return 0;
865 } else {
866 dev_err(dev, "Invalid pressure threshold for the touchscreen\n");
867 return -EINVAL;
868 }
869 }
870
at91_adc_probe_dt(struct at91_adc_state * st,struct platform_device * pdev)871 static int at91_adc_probe_dt(struct at91_adc_state *st,
872 struct platform_device *pdev)
873 {
874 struct iio_dev *idev = iio_priv_to_dev(st);
875 struct device_node *node = pdev->dev.of_node;
876 struct device_node *trig_node;
877 int i = 0, ret;
878 u32 prop;
879
880 if (!node)
881 return -EINVAL;
882
883 st->caps = (struct at91_adc_caps *)
884 of_match_device(at91_adc_dt_ids, &pdev->dev)->data;
885
886 st->use_external = of_property_read_bool(node, "atmel,adc-use-external-triggers");
887
888 if (of_property_read_u32(node, "atmel,adc-channels-used", &prop)) {
889 dev_err(&idev->dev, "Missing adc-channels-used property in the DT.\n");
890 ret = -EINVAL;
891 goto error_ret;
892 }
893 st->channels_mask = prop;
894
895 st->sleep_mode = of_property_read_bool(node, "atmel,adc-sleep-mode");
896
897 if (of_property_read_u32(node, "atmel,adc-startup-time", &prop)) {
898 dev_err(&idev->dev, "Missing adc-startup-time property in the DT.\n");
899 ret = -EINVAL;
900 goto error_ret;
901 }
902 st->startup_time = prop;
903
904 prop = 0;
905 of_property_read_u32(node, "atmel,adc-sample-hold-time", &prop);
906 st->sample_hold_time = prop;
907
908 if (of_property_read_u32(node, "atmel,adc-vref", &prop)) {
909 dev_err(&idev->dev, "Missing adc-vref property in the DT.\n");
910 ret = -EINVAL;
911 goto error_ret;
912 }
913 st->vref_mv = prop;
914
915 ret = at91_adc_of_get_resolution(st, pdev);
916 if (ret)
917 goto error_ret;
918
919 st->registers = &st->caps->registers;
920 st->num_channels = st->caps->num_channels;
921 st->trigger_number = of_get_child_count(node);
922 st->trigger_list = devm_kzalloc(&idev->dev, st->trigger_number *
923 sizeof(struct at91_adc_trigger),
924 GFP_KERNEL);
925 if (!st->trigger_list) {
926 dev_err(&idev->dev, "Could not allocate trigger list memory.\n");
927 ret = -ENOMEM;
928 goto error_ret;
929 }
930
931 for_each_child_of_node(node, trig_node) {
932 struct at91_adc_trigger *trig = st->trigger_list + i;
933 const char *name;
934
935 if (of_property_read_string(trig_node, "trigger-name", &name)) {
936 dev_err(&idev->dev, "Missing trigger-name property in the DT.\n");
937 ret = -EINVAL;
938 goto error_ret;
939 }
940 trig->name = name;
941
942 if (of_property_read_u32(trig_node, "trigger-value", &prop)) {
943 dev_err(&idev->dev, "Missing trigger-value property in the DT.\n");
944 ret = -EINVAL;
945 goto error_ret;
946 }
947 trig->value = prop;
948 trig->is_external = of_property_read_bool(trig_node, "trigger-external");
949 i++;
950 }
951
952 /* Check if touchscreen is supported. */
953 if (st->caps->has_ts)
954 return at91_adc_probe_dt_ts(node, st, &idev->dev);
955 else
956 dev_info(&idev->dev, "not support touchscreen in the adc compatible string.\n");
957
958 return 0;
959
960 error_ret:
961 return ret;
962 }
963
at91_adc_probe_pdata(struct at91_adc_state * st,struct platform_device * pdev)964 static int at91_adc_probe_pdata(struct at91_adc_state *st,
965 struct platform_device *pdev)
966 {
967 struct at91_adc_data *pdata = pdev->dev.platform_data;
968
969 if (!pdata)
970 return -EINVAL;
971
972 st->caps = (struct at91_adc_caps *)
973 platform_get_device_id(pdev)->driver_data;
974
975 st->use_external = pdata->use_external_triggers;
976 st->vref_mv = pdata->vref;
977 st->channels_mask = pdata->channels_used;
978 st->num_channels = st->caps->num_channels;
979 st->startup_time = pdata->startup_time;
980 st->trigger_number = pdata->trigger_number;
981 st->trigger_list = pdata->trigger_list;
982 st->registers = &st->caps->registers;
983 st->touchscreen_type = pdata->touchscreen_type;
984
985 return 0;
986 }
987
988 static const struct iio_info at91_adc_info = {
989 .driver_module = THIS_MODULE,
990 .read_raw = &at91_adc_read_raw,
991 };
992
993 /* Touchscreen related functions */
atmel_ts_open(struct input_dev * dev)994 static int atmel_ts_open(struct input_dev *dev)
995 {
996 struct at91_adc_state *st = input_get_drvdata(dev);
997
998 if (st->caps->has_tsmr)
999 at91_adc_writel(st, AT91_ADC_IER, AT91_ADC_IER_PEN);
1000 else
1001 at91_adc_writel(st, AT91_ADC_IER, AT91RL_ADC_IER_PEN);
1002 return 0;
1003 }
1004
atmel_ts_close(struct input_dev * dev)1005 static void atmel_ts_close(struct input_dev *dev)
1006 {
1007 struct at91_adc_state *st = input_get_drvdata(dev);
1008
1009 if (st->caps->has_tsmr)
1010 at91_adc_writel(st, AT91_ADC_IDR, AT91_ADC_IER_PEN);
1011 else
1012 at91_adc_writel(st, AT91_ADC_IDR, AT91RL_ADC_IER_PEN);
1013 }
1014
at91_ts_hw_init(struct at91_adc_state * st,u32 adc_clk_khz)1015 static int at91_ts_hw_init(struct at91_adc_state *st, u32 adc_clk_khz)
1016 {
1017 struct iio_dev *idev = iio_priv_to_dev(st);
1018 u32 reg = 0;
1019 u32 tssctim = 0;
1020 int i = 0;
1021
1022 /* a Pen Detect Debounce Time is necessary for the ADC Touch to avoid
1023 * pen detect noise.
1024 * The formula is : Pen Detect Debounce Time = (2 ^ pendbc) / ADCClock
1025 */
1026 st->ts_pendbc = round_up(TOUCH_PEN_DETECT_DEBOUNCE_US * adc_clk_khz /
1027 1000, 1);
1028
1029 while (st->ts_pendbc >> ++i)
1030 ; /* Empty! Find the shift offset */
1031 if (abs(st->ts_pendbc - (1 << i)) < abs(st->ts_pendbc - (1 << (i - 1))))
1032 st->ts_pendbc = i;
1033 else
1034 st->ts_pendbc = i - 1;
1035
1036 if (!st->caps->has_tsmr) {
1037 reg = at91_adc_readl(st, AT91_ADC_MR);
1038 reg |= AT91_ADC_TSAMOD_TS_ONLY_MODE | AT91_ADC_PENDET;
1039
1040 reg |= AT91_ADC_PENDBC_(st->ts_pendbc) & AT91_ADC_PENDBC;
1041 at91_adc_writel(st, AT91_ADC_MR, reg);
1042
1043 reg = AT91_ADC_TSR_SHTIM_(TOUCH_SHTIM) & AT91_ADC_TSR_SHTIM;
1044 at91_adc_writel(st, AT91_ADC_TSR, reg);
1045
1046 st->ts_sample_period_val = round_up((TOUCH_SAMPLE_PERIOD_US_RL *
1047 adc_clk_khz / 1000) - 1, 1);
1048
1049 return 0;
1050 }
1051
1052 /* Touchscreen Switches Closure time needed for allowing the value to
1053 * stabilize.
1054 * Switch Closure Time = (TSSCTIM * 4) ADCClock periods
1055 */
1056 tssctim = DIV_ROUND_UP(TOUCH_SCTIM_US * adc_clk_khz / 1000, 4);
1057 dev_dbg(&idev->dev, "adc_clk at: %d KHz, tssctim at: %d\n",
1058 adc_clk_khz, tssctim);
1059
1060 if (st->touchscreen_type == ATMEL_ADC_TOUCHSCREEN_4WIRE)
1061 reg = AT91_ADC_TSMR_TSMODE_4WIRE_PRESS;
1062 else
1063 reg = AT91_ADC_TSMR_TSMODE_5WIRE;
1064
1065 reg |= AT91_ADC_TSMR_SCTIM_(tssctim) & AT91_ADC_TSMR_SCTIM;
1066 reg |= AT91_ADC_TSMR_TSAV_(st->caps->ts_filter_average)
1067 & AT91_ADC_TSMR_TSAV;
1068 reg |= AT91_ADC_TSMR_PENDBC_(st->ts_pendbc) & AT91_ADC_TSMR_PENDBC;
1069 reg |= AT91_ADC_TSMR_NOTSDMA;
1070 reg |= AT91_ADC_TSMR_PENDET_ENA;
1071 reg |= 0x03 << 8; /* TSFREQ, needs to be bigger than TSAV */
1072
1073 at91_adc_writel(st, AT91_ADC_TSMR, reg);
1074
1075 /* Change adc internal resistor value for better pen detection,
1076 * default value is 100 kOhm.
1077 * 0 = 200 kOhm, 1 = 150 kOhm, 2 = 100 kOhm, 3 = 50 kOhm
1078 * option only available on ES2 and higher
1079 */
1080 at91_adc_writel(st, AT91_ADC_ACR, st->caps->ts_pen_detect_sensitivity
1081 & AT91_ADC_ACR_PENDETSENS);
1082
1083 /* Sample Period Time = (TRGPER + 1) / ADCClock */
1084 st->ts_sample_period_val = round_up((TOUCH_SAMPLE_PERIOD_US *
1085 adc_clk_khz / 1000) - 1, 1);
1086
1087 return 0;
1088 }
1089
at91_ts_register(struct at91_adc_state * st,struct platform_device * pdev)1090 static int at91_ts_register(struct at91_adc_state *st,
1091 struct platform_device *pdev)
1092 {
1093 struct input_dev *input;
1094 struct iio_dev *idev = iio_priv_to_dev(st);
1095 int ret;
1096
1097 input = input_allocate_device();
1098 if (!input) {
1099 dev_err(&idev->dev, "Failed to allocate TS device!\n");
1100 return -ENOMEM;
1101 }
1102
1103 input->name = DRIVER_NAME;
1104 input->id.bustype = BUS_HOST;
1105 input->dev.parent = &pdev->dev;
1106 input->open = atmel_ts_open;
1107 input->close = atmel_ts_close;
1108
1109 __set_bit(EV_ABS, input->evbit);
1110 __set_bit(EV_KEY, input->evbit);
1111 __set_bit(BTN_TOUCH, input->keybit);
1112 if (st->caps->has_tsmr) {
1113 input_set_abs_params(input, ABS_X, 0, (1 << MAX_POS_BITS) - 1,
1114 0, 0);
1115 input_set_abs_params(input, ABS_Y, 0, (1 << MAX_POS_BITS) - 1,
1116 0, 0);
1117 input_set_abs_params(input, ABS_PRESSURE, 0, 0xffffff, 0, 0);
1118 } else {
1119 if (st->touchscreen_type != ATMEL_ADC_TOUCHSCREEN_4WIRE) {
1120 dev_err(&pdev->dev,
1121 "This touchscreen controller only support 4 wires\n");
1122 ret = -EINVAL;
1123 goto err;
1124 }
1125
1126 input_set_abs_params(input, ABS_X, 0, (1 << MAX_RLPOS_BITS) - 1,
1127 0, 0);
1128 input_set_abs_params(input, ABS_Y, 0, (1 << MAX_RLPOS_BITS) - 1,
1129 0, 0);
1130 }
1131
1132 st->ts_input = input;
1133 input_set_drvdata(input, st);
1134
1135 ret = input_register_device(input);
1136 if (ret)
1137 goto err;
1138
1139 return ret;
1140
1141 err:
1142 input_free_device(st->ts_input);
1143 return ret;
1144 }
1145
at91_ts_unregister(struct at91_adc_state * st)1146 static void at91_ts_unregister(struct at91_adc_state *st)
1147 {
1148 input_unregister_device(st->ts_input);
1149 }
1150
at91_adc_probe(struct platform_device * pdev)1151 static int at91_adc_probe(struct platform_device *pdev)
1152 {
1153 unsigned int prsc, mstrclk, ticks, adc_clk, adc_clk_khz, shtim;
1154 int ret;
1155 struct iio_dev *idev;
1156 struct at91_adc_state *st;
1157 struct resource *res;
1158 u32 reg;
1159
1160 idev = devm_iio_device_alloc(&pdev->dev, sizeof(struct at91_adc_state));
1161 if (!idev)
1162 return -ENOMEM;
1163
1164 st = iio_priv(idev);
1165
1166 if (pdev->dev.of_node)
1167 ret = at91_adc_probe_dt(st, pdev);
1168 else
1169 ret = at91_adc_probe_pdata(st, pdev);
1170
1171 if (ret) {
1172 dev_err(&pdev->dev, "No platform data available.\n");
1173 return -EINVAL;
1174 }
1175
1176 platform_set_drvdata(pdev, idev);
1177
1178 idev->dev.parent = &pdev->dev;
1179 idev->name = dev_name(&pdev->dev);
1180 idev->modes = INDIO_DIRECT_MODE;
1181 idev->info = &at91_adc_info;
1182
1183 st->irq = platform_get_irq(pdev, 0);
1184 if (st->irq < 0) {
1185 dev_err(&pdev->dev, "No IRQ ID is designated\n");
1186 return -ENODEV;
1187 }
1188
1189 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1190
1191 st->reg_base = devm_ioremap_resource(&pdev->dev, res);
1192 if (IS_ERR(st->reg_base)) {
1193 return PTR_ERR(st->reg_base);
1194 }
1195
1196 /*
1197 * Disable all IRQs before setting up the handler
1198 */
1199 at91_adc_writel(st, AT91_ADC_CR, AT91_ADC_SWRST);
1200 at91_adc_writel(st, AT91_ADC_IDR, 0xFFFFFFFF);
1201
1202 if (st->caps->has_tsmr)
1203 ret = request_irq(st->irq, at91_adc_9x5_interrupt, 0,
1204 pdev->dev.driver->name, idev);
1205 else
1206 ret = request_irq(st->irq, at91_adc_rl_interrupt, 0,
1207 pdev->dev.driver->name, idev);
1208 if (ret) {
1209 dev_err(&pdev->dev, "Failed to allocate IRQ.\n");
1210 return ret;
1211 }
1212
1213 st->clk = devm_clk_get(&pdev->dev, "adc_clk");
1214 if (IS_ERR(st->clk)) {
1215 dev_err(&pdev->dev, "Failed to get the clock.\n");
1216 ret = PTR_ERR(st->clk);
1217 goto error_free_irq;
1218 }
1219
1220 ret = clk_prepare_enable(st->clk);
1221 if (ret) {
1222 dev_err(&pdev->dev,
1223 "Could not prepare or enable the clock.\n");
1224 goto error_free_irq;
1225 }
1226
1227 st->adc_clk = devm_clk_get(&pdev->dev, "adc_op_clk");
1228 if (IS_ERR(st->adc_clk)) {
1229 dev_err(&pdev->dev, "Failed to get the ADC clock.\n");
1230 ret = PTR_ERR(st->adc_clk);
1231 goto error_disable_clk;
1232 }
1233
1234 ret = clk_prepare_enable(st->adc_clk);
1235 if (ret) {
1236 dev_err(&pdev->dev,
1237 "Could not prepare or enable the ADC clock.\n");
1238 goto error_disable_clk;
1239 }
1240
1241 /*
1242 * Prescaler rate computation using the formula from the Atmel's
1243 * datasheet : ADC Clock = MCK / ((Prescaler + 1) * 2), ADC Clock being
1244 * specified by the electrical characteristics of the board.
1245 */
1246 mstrclk = clk_get_rate(st->clk);
1247 adc_clk = clk_get_rate(st->adc_clk);
1248 adc_clk_khz = adc_clk / 1000;
1249
1250 dev_dbg(&pdev->dev, "Master clock is set as: %d Hz, adc_clk should set as: %d Hz\n",
1251 mstrclk, adc_clk);
1252
1253 prsc = (mstrclk / (2 * adc_clk)) - 1;
1254
1255 if (!st->startup_time) {
1256 dev_err(&pdev->dev, "No startup time available.\n");
1257 ret = -EINVAL;
1258 goto error_disable_adc_clk;
1259 }
1260 ticks = (*st->caps->calc_startup_ticks)(st->startup_time, adc_clk_khz);
1261
1262 /*
1263 * a minimal Sample and Hold Time is necessary for the ADC to guarantee
1264 * the best converted final value between two channels selection
1265 * The formula thus is : Sample and Hold Time = (shtim + 1) / ADCClock
1266 */
1267 if (st->sample_hold_time > 0)
1268 shtim = round_up((st->sample_hold_time * adc_clk_khz / 1000)
1269 - 1, 1);
1270 else
1271 shtim = 0;
1272
1273 reg = AT91_ADC_PRESCAL_(prsc) & st->registers->mr_prescal_mask;
1274 reg |= AT91_ADC_STARTUP_(ticks) & st->registers->mr_startup_mask;
1275 if (st->low_res)
1276 reg |= AT91_ADC_LOWRES;
1277 if (st->sleep_mode)
1278 reg |= AT91_ADC_SLEEP;
1279 reg |= AT91_ADC_SHTIM_(shtim) & AT91_ADC_SHTIM;
1280 at91_adc_writel(st, AT91_ADC_MR, reg);
1281
1282 /* Setup the ADC channels available on the board */
1283 ret = at91_adc_channel_init(idev);
1284 if (ret < 0) {
1285 dev_err(&pdev->dev, "Couldn't initialize the channels.\n");
1286 goto error_disable_adc_clk;
1287 }
1288
1289 init_waitqueue_head(&st->wq_data_avail);
1290 mutex_init(&st->lock);
1291
1292 /*
1293 * Since touch screen will set trigger register as period trigger. So
1294 * when touch screen is enabled, then we have to disable hardware
1295 * trigger for classic adc.
1296 */
1297 if (!st->touchscreen_type) {
1298 ret = at91_adc_buffer_init(idev);
1299 if (ret < 0) {
1300 dev_err(&pdev->dev, "Couldn't initialize the buffer.\n");
1301 goto error_disable_adc_clk;
1302 }
1303
1304 ret = at91_adc_trigger_init(idev);
1305 if (ret < 0) {
1306 dev_err(&pdev->dev, "Couldn't setup the triggers.\n");
1307 at91_adc_buffer_remove(idev);
1308 goto error_disable_adc_clk;
1309 }
1310 } else {
1311 ret = at91_ts_register(st, pdev);
1312 if (ret)
1313 goto error_disable_adc_clk;
1314
1315 at91_ts_hw_init(st, adc_clk_khz);
1316 }
1317
1318 ret = iio_device_register(idev);
1319 if (ret < 0) {
1320 dev_err(&pdev->dev, "Couldn't register the device.\n");
1321 goto error_iio_device_register;
1322 }
1323
1324 return 0;
1325
1326 error_iio_device_register:
1327 if (!st->touchscreen_type) {
1328 at91_adc_trigger_remove(idev);
1329 at91_adc_buffer_remove(idev);
1330 } else {
1331 at91_ts_unregister(st);
1332 }
1333 error_disable_adc_clk:
1334 clk_disable_unprepare(st->adc_clk);
1335 error_disable_clk:
1336 clk_disable_unprepare(st->clk);
1337 error_free_irq:
1338 free_irq(st->irq, idev);
1339 return ret;
1340 }
1341
at91_adc_remove(struct platform_device * pdev)1342 static int at91_adc_remove(struct platform_device *pdev)
1343 {
1344 struct iio_dev *idev = platform_get_drvdata(pdev);
1345 struct at91_adc_state *st = iio_priv(idev);
1346
1347 iio_device_unregister(idev);
1348 if (!st->touchscreen_type) {
1349 at91_adc_trigger_remove(idev);
1350 at91_adc_buffer_remove(idev);
1351 } else {
1352 at91_ts_unregister(st);
1353 }
1354 clk_disable_unprepare(st->adc_clk);
1355 clk_disable_unprepare(st->clk);
1356 free_irq(st->irq, idev);
1357
1358 return 0;
1359 }
1360
1361 #ifdef CONFIG_PM_SLEEP
at91_adc_suspend(struct device * dev)1362 static int at91_adc_suspend(struct device *dev)
1363 {
1364 struct iio_dev *idev = platform_get_drvdata(to_platform_device(dev));
1365 struct at91_adc_state *st = iio_priv(idev);
1366
1367 pinctrl_pm_select_sleep_state(dev);
1368 clk_disable_unprepare(st->clk);
1369
1370 return 0;
1371 }
1372
at91_adc_resume(struct device * dev)1373 static int at91_adc_resume(struct device *dev)
1374 {
1375 struct iio_dev *idev = platform_get_drvdata(to_platform_device(dev));
1376 struct at91_adc_state *st = iio_priv(idev);
1377
1378 clk_prepare_enable(st->clk);
1379 pinctrl_pm_select_default_state(dev);
1380
1381 return 0;
1382 }
1383 #endif
1384
1385 static SIMPLE_DEV_PM_OPS(at91_adc_pm_ops, at91_adc_suspend, at91_adc_resume);
1386
1387 static struct at91_adc_caps at91sam9260_caps = {
1388 .calc_startup_ticks = calc_startup_ticks_9260,
1389 .num_channels = 4,
1390 .registers = {
1391 .channel_base = AT91_ADC_CHR(0),
1392 .drdy_mask = AT91_ADC_DRDY,
1393 .status_register = AT91_ADC_SR,
1394 .trigger_register = AT91_ADC_TRGR_9260,
1395 .mr_prescal_mask = AT91_ADC_PRESCAL_9260,
1396 .mr_startup_mask = AT91_ADC_STARTUP_9260,
1397 },
1398 };
1399
1400 static struct at91_adc_caps at91sam9rl_caps = {
1401 .has_ts = true,
1402 .calc_startup_ticks = calc_startup_ticks_9260, /* same as 9260 */
1403 .num_channels = 6,
1404 .registers = {
1405 .channel_base = AT91_ADC_CHR(0),
1406 .drdy_mask = AT91_ADC_DRDY,
1407 .status_register = AT91_ADC_SR,
1408 .trigger_register = AT91_ADC_TRGR_9G45,
1409 .mr_prescal_mask = AT91_ADC_PRESCAL_9260,
1410 .mr_startup_mask = AT91_ADC_STARTUP_9G45,
1411 },
1412 };
1413
1414 static struct at91_adc_caps at91sam9g45_caps = {
1415 .has_ts = true,
1416 .calc_startup_ticks = calc_startup_ticks_9260, /* same as 9260 */
1417 .num_channels = 8,
1418 .registers = {
1419 .channel_base = AT91_ADC_CHR(0),
1420 .drdy_mask = AT91_ADC_DRDY,
1421 .status_register = AT91_ADC_SR,
1422 .trigger_register = AT91_ADC_TRGR_9G45,
1423 .mr_prescal_mask = AT91_ADC_PRESCAL_9G45,
1424 .mr_startup_mask = AT91_ADC_STARTUP_9G45,
1425 },
1426 };
1427
1428 static struct at91_adc_caps at91sam9x5_caps = {
1429 .has_ts = true,
1430 .has_tsmr = true,
1431 .ts_filter_average = 3,
1432 .ts_pen_detect_sensitivity = 2,
1433 .calc_startup_ticks = calc_startup_ticks_9x5,
1434 .num_channels = 12,
1435 .registers = {
1436 .channel_base = AT91_ADC_CDR0_9X5,
1437 .drdy_mask = AT91_ADC_SR_DRDY_9X5,
1438 .status_register = AT91_ADC_SR_9X5,
1439 .trigger_register = AT91_ADC_TRGR_9X5,
1440 /* prescal mask is same as 9G45 */
1441 .mr_prescal_mask = AT91_ADC_PRESCAL_9G45,
1442 .mr_startup_mask = AT91_ADC_STARTUP_9X5,
1443 },
1444 };
1445
1446 static const struct of_device_id at91_adc_dt_ids[] = {
1447 { .compatible = "atmel,at91sam9260-adc", .data = &at91sam9260_caps },
1448 { .compatible = "atmel,at91sam9rl-adc", .data = &at91sam9rl_caps },
1449 { .compatible = "atmel,at91sam9g45-adc", .data = &at91sam9g45_caps },
1450 { .compatible = "atmel,at91sam9x5-adc", .data = &at91sam9x5_caps },
1451 {},
1452 };
1453 MODULE_DEVICE_TABLE(of, at91_adc_dt_ids);
1454
1455 static const struct platform_device_id at91_adc_ids[] = {
1456 {
1457 .name = "at91sam9260-adc",
1458 .driver_data = (unsigned long)&at91sam9260_caps,
1459 }, {
1460 .name = "at91sam9rl-adc",
1461 .driver_data = (unsigned long)&at91sam9rl_caps,
1462 }, {
1463 .name = "at91sam9g45-adc",
1464 .driver_data = (unsigned long)&at91sam9g45_caps,
1465 }, {
1466 .name = "at91sam9x5-adc",
1467 .driver_data = (unsigned long)&at91sam9x5_caps,
1468 }, {
1469 /* terminator */
1470 }
1471 };
1472 MODULE_DEVICE_TABLE(platform, at91_adc_ids);
1473
1474 static struct platform_driver at91_adc_driver = {
1475 .probe = at91_adc_probe,
1476 .remove = at91_adc_remove,
1477 .id_table = at91_adc_ids,
1478 .driver = {
1479 .name = DRIVER_NAME,
1480 .of_match_table = of_match_ptr(at91_adc_dt_ids),
1481 .pm = &at91_adc_pm_ops,
1482 },
1483 };
1484
1485 module_platform_driver(at91_adc_driver);
1486
1487 MODULE_LICENSE("GPL");
1488 MODULE_DESCRIPTION("Atmel AT91 ADC Driver");
1489 MODULE_AUTHOR("Maxime Ripard <maxime.ripard@free-electrons.com>");
1490