1 /* 2 * This file is part of STM32 ADC driver 3 * 4 * Copyright (C) 2016, STMicroelectronics - All Rights Reserved 5 * Author: Fabrice Gasnier <fabrice.gasnier@st.com>. 6 * 7 * License type: GPLv2 8 * 9 * This program is free software; you can redistribute it and/or modify it 10 * under the terms of the GNU General Public License version 2 as published by 11 * the Free Software Foundation. 12 * 13 * This program is distributed in the hope that it will be useful, but 14 * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY 15 * or FITNESS FOR A PARTICULAR PURPOSE. 16 * See the GNU General Public License for more details. 17 * 18 * You should have received a copy of the GNU General Public License along with 19 * this program. If not, see <http://www.gnu.org/licenses/>. 20 */ 21 22 #ifndef __STM32_ADC_H 23 #define __STM32_ADC_H 24 25 /* 26 * STM32 - ADC global register map 27 * ________________________________________________________ 28 * | Offset | Register | 29 * -------------------------------------------------------- 30 * | 0x000 | Master ADC1 | 31 * -------------------------------------------------------- 32 * | 0x100 | Slave ADC2 | 33 * -------------------------------------------------------- 34 * | 0x200 | Slave ADC3 | 35 * -------------------------------------------------------- 36 * | 0x300 | Master & Slave common regs | 37 * -------------------------------------------------------- 38 */ 39 #define STM32_ADC_MAX_ADCS 3 40 #define STM32_ADC_OFFSET 0x100 41 #define STM32_ADCX_COMN_OFFSET 0x300 42 43 /* STM32F4 - Registers for each ADC instance */ 44 #define STM32F4_ADC_SR 0x00 45 #define STM32F4_ADC_CR1 0x04 46 #define STM32F4_ADC_CR2 0x08 47 #define STM32F4_ADC_SMPR1 0x0C 48 #define STM32F4_ADC_SMPR2 0x10 49 #define STM32F4_ADC_HTR 0x24 50 #define STM32F4_ADC_LTR 0x28 51 #define STM32F4_ADC_SQR1 0x2C 52 #define STM32F4_ADC_SQR2 0x30 53 #define STM32F4_ADC_SQR3 0x34 54 #define STM32F4_ADC_JSQR 0x38 55 #define STM32F4_ADC_JDR1 0x3C 56 #define STM32F4_ADC_JDR2 0x40 57 #define STM32F4_ADC_JDR3 0x44 58 #define STM32F4_ADC_JDR4 0x48 59 #define STM32F4_ADC_DR 0x4C 60 61 /* STM32F4 - common registers for all ADC instances: 1, 2 & 3 */ 62 #define STM32F4_ADC_CSR (STM32_ADCX_COMN_OFFSET + 0x00) 63 #define STM32F4_ADC_CCR (STM32_ADCX_COMN_OFFSET + 0x04) 64 65 /* STM32F4_ADC_SR - bit fields */ 66 #define STM32F4_STRT BIT(4) 67 #define STM32F4_EOC BIT(1) 68 69 /* STM32F4_ADC_CR1 - bit fields */ 70 #define STM32F4_RES_SHIFT 24 71 #define STM32F4_RES_MASK GENMASK(25, 24) 72 #define STM32F4_SCAN BIT(8) 73 #define STM32F4_EOCIE BIT(5) 74 75 /* STM32F4_ADC_CR2 - bit fields */ 76 #define STM32F4_SWSTART BIT(30) 77 #define STM32F4_EXTEN_SHIFT 28 78 #define STM32F4_EXTEN_MASK GENMASK(29, 28) 79 #define STM32F4_EXTSEL_SHIFT 24 80 #define STM32F4_EXTSEL_MASK GENMASK(27, 24) 81 #define STM32F4_EOCS BIT(10) 82 #define STM32F4_DDS BIT(9) 83 #define STM32F4_DMA BIT(8) 84 #define STM32F4_ADON BIT(0) 85 86 /* STM32F4_ADC_CSR - bit fields */ 87 #define STM32F4_EOC3 BIT(17) 88 #define STM32F4_EOC2 BIT(9) 89 #define STM32F4_EOC1 BIT(1) 90 91 /* STM32F4_ADC_CCR - bit fields */ 92 #define STM32F4_ADC_ADCPRE_SHIFT 16 93 #define STM32F4_ADC_ADCPRE_MASK GENMASK(17, 16) 94 95 /* STM32H7 - Registers for each ADC instance */ 96 #define STM32H7_ADC_ISR 0x00 97 #define STM32H7_ADC_IER 0x04 98 #define STM32H7_ADC_CR 0x08 99 #define STM32H7_ADC_CFGR 0x0C 100 #define STM32H7_ADC_SMPR1 0x14 101 #define STM32H7_ADC_SMPR2 0x18 102 #define STM32H7_ADC_PCSEL 0x1C 103 #define STM32H7_ADC_SQR1 0x30 104 #define STM32H7_ADC_SQR2 0x34 105 #define STM32H7_ADC_SQR3 0x38 106 #define STM32H7_ADC_SQR4 0x3C 107 #define STM32H7_ADC_DR 0x40 108 #define STM32H7_ADC_CALFACT 0xC4 109 #define STM32H7_ADC_CALFACT2 0xC8 110 111 /* STM32H7 - common registers for all ADC instances */ 112 #define STM32H7_ADC_CSR (STM32_ADCX_COMN_OFFSET + 0x00) 113 #define STM32H7_ADC_CCR (STM32_ADCX_COMN_OFFSET + 0x08) 114 115 /* STM32H7_ADC_ISR - bit fields */ 116 #define STM32H7_EOC BIT(2) 117 #define STM32H7_ADRDY BIT(0) 118 119 /* STM32H7_ADC_IER - bit fields */ 120 #define STM32H7_EOCIE STM32H7_EOC 121 122 /* STM32H7_ADC_CR - bit fields */ 123 #define STM32H7_ADCAL BIT(31) 124 #define STM32H7_ADCALDIF BIT(30) 125 #define STM32H7_DEEPPWD BIT(29) 126 #define STM32H7_ADVREGEN BIT(28) 127 #define STM32H7_LINCALRDYW6 BIT(27) 128 #define STM32H7_LINCALRDYW5 BIT(26) 129 #define STM32H7_LINCALRDYW4 BIT(25) 130 #define STM32H7_LINCALRDYW3 BIT(24) 131 #define STM32H7_LINCALRDYW2 BIT(23) 132 #define STM32H7_LINCALRDYW1 BIT(22) 133 #define STM32H7_ADCALLIN BIT(16) 134 #define STM32H7_BOOST BIT(8) 135 #define STM32H7_ADSTP BIT(4) 136 #define STM32H7_ADSTART BIT(2) 137 #define STM32H7_ADDIS BIT(1) 138 #define STM32H7_ADEN BIT(0) 139 140 /* STM32H7_ADC_CFGR bit fields */ 141 #define STM32H7_EXTEN_SHIFT 10 142 #define STM32H7_EXTEN_MASK GENMASK(11, 10) 143 #define STM32H7_EXTSEL_SHIFT 5 144 #define STM32H7_EXTSEL_MASK GENMASK(9, 5) 145 #define STM32H7_RES_SHIFT 2 146 #define STM32H7_RES_MASK GENMASK(4, 2) 147 #define STM32H7_DMNGT_SHIFT 0 148 #define STM32H7_DMNGT_MASK GENMASK(1, 0) 149 150 enum stm32h7_adc_dmngt { 151 STM32H7_DMNGT_DR_ONLY, /* Regular data in DR only */ 152 STM32H7_DMNGT_DMA_ONESHOT, /* DMA one shot mode */ 153 STM32H7_DMNGT_DFSDM, /* DFSDM mode */ 154 STM32H7_DMNGT_DMA_CIRC, /* DMA circular mode */ 155 }; 156 157 /* STM32H7_ADC_CALFACT - bit fields */ 158 #define STM32H7_CALFACT_D_SHIFT 16 159 #define STM32H7_CALFACT_D_MASK GENMASK(26, 16) 160 #define STM32H7_CALFACT_S_SHIFT 0 161 #define STM32H7_CALFACT_S_MASK GENMASK(10, 0) 162 163 /* STM32H7_ADC_CALFACT2 - bit fields */ 164 #define STM32H7_LINCALFACT_SHIFT 0 165 #define STM32H7_LINCALFACT_MASK GENMASK(29, 0) 166 167 /* STM32H7_ADC_CSR - bit fields */ 168 #define STM32H7_EOC_SLV BIT(18) 169 #define STM32H7_EOC_MST BIT(2) 170 171 /* STM32H7_ADC_CCR - bit fields */ 172 #define STM32H7_PRESC_SHIFT 18 173 #define STM32H7_PRESC_MASK GENMASK(21, 18) 174 #define STM32H7_CKMODE_SHIFT 16 175 #define STM32H7_CKMODE_MASK GENMASK(17, 16) 176 177 /** 178 * struct stm32_adc_common - stm32 ADC driver common data (for all instances) 179 * @base: control registers base cpu addr 180 * @phys_base: control registers base physical addr 181 * @rate: clock rate used for analog circuitry 182 * @vref_mv: vref voltage (mv) 183 */ 184 struct stm32_adc_common { 185 void __iomem *base; 186 phys_addr_t phys_base; 187 unsigned long rate; 188 int vref_mv; 189 }; 190 191 #endif 192