1 /*
2 * This file is part of STM32 ADC driver
3 *
4 * Copyright (C) 2016, STMicroelectronics - All Rights Reserved
5 * Author: Fabrice Gasnier <fabrice.gasnier@st.com>.
6 *
7 * License type: GPLv2
8 *
9 * This program is free software; you can redistribute it and/or modify it
10 * under the terms of the GNU General Public License version 2 as published by
11 * the Free Software Foundation.
12 *
13 * This program is distributed in the hope that it will be useful, but
14 * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
15 * or FITNESS FOR A PARTICULAR PURPOSE.
16 * See the GNU General Public License for more details.
17 *
18 * You should have received a copy of the GNU General Public License along with
19 * this program. If not, see <http://www.gnu.org/licenses/>.
20 */
21
22 #include <linux/clk.h>
23 #include <linux/delay.h>
24 #include <linux/dma-mapping.h>
25 #include <linux/dmaengine.h>
26 #include <linux/iio/iio.h>
27 #include <linux/iio/buffer.h>
28 #include <linux/iio/timer/stm32-lptim-trigger.h>
29 #include <linux/iio/timer/stm32-timer-trigger.h>
30 #include <linux/iio/trigger.h>
31 #include <linux/iio/trigger_consumer.h>
32 #include <linux/iio/triggered_buffer.h>
33 #include <linux/interrupt.h>
34 #include <linux/io.h>
35 #include <linux/iopoll.h>
36 #include <linux/module.h>
37 #include <linux/platform_device.h>
38 #include <linux/of.h>
39 #include <linux/of_device.h>
40
41 #include "stm32-adc-core.h"
42
43 /* Number of linear calibration shadow registers / LINCALRDYW control bits */
44 #define STM32H7_LINCALFACT_NUM 6
45
46 /* BOOST bit must be set on STM32H7 when ADC clock is above 20MHz */
47 #define STM32H7_BOOST_CLKRATE 20000000UL
48
49 #define STM32_ADC_MAX_SQ 16 /* SQ1..SQ16 */
50 #define STM32_ADC_MAX_SMP 7 /* SMPx range is [0..7] */
51 #define STM32_ADC_TIMEOUT_US 100000
52 #define STM32_ADC_TIMEOUT (msecs_to_jiffies(STM32_ADC_TIMEOUT_US / 1000))
53
54 #define STM32_DMA_BUFFER_SIZE PAGE_SIZE
55
56 /* External trigger enable */
57 enum stm32_adc_exten {
58 STM32_EXTEN_SWTRIG,
59 STM32_EXTEN_HWTRIG_RISING_EDGE,
60 STM32_EXTEN_HWTRIG_FALLING_EDGE,
61 STM32_EXTEN_HWTRIG_BOTH_EDGES,
62 };
63
64 /* extsel - trigger mux selection value */
65 enum stm32_adc_extsel {
66 STM32_EXT0,
67 STM32_EXT1,
68 STM32_EXT2,
69 STM32_EXT3,
70 STM32_EXT4,
71 STM32_EXT5,
72 STM32_EXT6,
73 STM32_EXT7,
74 STM32_EXT8,
75 STM32_EXT9,
76 STM32_EXT10,
77 STM32_EXT11,
78 STM32_EXT12,
79 STM32_EXT13,
80 STM32_EXT14,
81 STM32_EXT15,
82 STM32_EXT16,
83 STM32_EXT17,
84 STM32_EXT18,
85 STM32_EXT19,
86 STM32_EXT20,
87 };
88
89 /**
90 * struct stm32_adc_trig_info - ADC trigger info
91 * @name: name of the trigger, corresponding to its source
92 * @extsel: trigger selection
93 */
94 struct stm32_adc_trig_info {
95 const char *name;
96 enum stm32_adc_extsel extsel;
97 };
98
99 /**
100 * struct stm32_adc_calib - optional adc calibration data
101 * @calfact_s: Calibration offset for single ended channels
102 * @calfact_d: Calibration offset in differential
103 * @lincalfact: Linearity calibration factor
104 */
105 struct stm32_adc_calib {
106 u32 calfact_s;
107 u32 calfact_d;
108 u32 lincalfact[STM32H7_LINCALFACT_NUM];
109 };
110
111 /**
112 * stm32_adc_regs - stm32 ADC misc registers & bitfield desc
113 * @reg: register offset
114 * @mask: bitfield mask
115 * @shift: left shift
116 */
117 struct stm32_adc_regs {
118 int reg;
119 int mask;
120 int shift;
121 };
122
123 /**
124 * stm32_adc_regspec - stm32 registers definition, compatible dependent data
125 * @dr: data register offset
126 * @ier_eoc: interrupt enable register & eocie bitfield
127 * @isr_eoc: interrupt status register & eoc bitfield
128 * @sqr: reference to sequence registers array
129 * @exten: trigger control register & bitfield
130 * @extsel: trigger selection register & bitfield
131 * @res: resolution selection register & bitfield
132 * @smpr: smpr1 & smpr2 registers offset array
133 * @smp_bits: smpr1 & smpr2 index and bitfields
134 */
135 struct stm32_adc_regspec {
136 const u32 dr;
137 const struct stm32_adc_regs ier_eoc;
138 const struct stm32_adc_regs isr_eoc;
139 const struct stm32_adc_regs *sqr;
140 const struct stm32_adc_regs exten;
141 const struct stm32_adc_regs extsel;
142 const struct stm32_adc_regs res;
143 const u32 smpr[2];
144 const struct stm32_adc_regs *smp_bits;
145 };
146
147 struct stm32_adc;
148
149 /**
150 * stm32_adc_cfg - stm32 compatible configuration data
151 * @regs: registers descriptions
152 * @adc_info: per instance input channels definitions
153 * @trigs: external trigger sources
154 * @clk_required: clock is required
155 * @selfcalib: optional routine for self-calibration
156 * @prepare: optional prepare routine (power-up, enable)
157 * @start_conv: routine to start conversions
158 * @stop_conv: routine to stop conversions
159 * @unprepare: optional unprepare routine (disable, power-down)
160 * @smp_cycles: programmable sampling time (ADC clock cycles)
161 */
162 struct stm32_adc_cfg {
163 const struct stm32_adc_regspec *regs;
164 const struct stm32_adc_info *adc_info;
165 struct stm32_adc_trig_info *trigs;
166 bool clk_required;
167 int (*selfcalib)(struct stm32_adc *);
168 int (*prepare)(struct stm32_adc *);
169 void (*start_conv)(struct stm32_adc *, bool dma);
170 void (*stop_conv)(struct stm32_adc *);
171 void (*unprepare)(struct stm32_adc *);
172 const unsigned int *smp_cycles;
173 };
174
175 /**
176 * struct stm32_adc - private data of each ADC IIO instance
177 * @common: reference to ADC block common data
178 * @offset: ADC instance register offset in ADC block
179 * @cfg: compatible configuration data
180 * @completion: end of single conversion completion
181 * @buffer: data buffer
182 * @clk: clock for this adc instance
183 * @irq: interrupt for this adc instance
184 * @lock: spinlock
185 * @bufi: data buffer index
186 * @num_conv: expected number of scan conversions
187 * @res: data resolution (e.g. RES bitfield value)
188 * @trigger_polarity: external trigger polarity (e.g. exten)
189 * @dma_chan: dma channel
190 * @rx_buf: dma rx buffer cpu address
191 * @rx_dma_buf: dma rx buffer bus address
192 * @rx_buf_sz: dma rx buffer size
193 * @pcsel bitmask to preselect channels on some devices
194 * @smpr_val: sampling time settings (e.g. smpr1 / smpr2)
195 * @cal: optional calibration data on some devices
196 */
197 struct stm32_adc {
198 struct stm32_adc_common *common;
199 u32 offset;
200 const struct stm32_adc_cfg *cfg;
201 struct completion completion;
202 u16 buffer[STM32_ADC_MAX_SQ];
203 struct clk *clk;
204 int irq;
205 spinlock_t lock; /* interrupt lock */
206 unsigned int bufi;
207 unsigned int num_conv;
208 u32 res;
209 u32 trigger_polarity;
210 struct dma_chan *dma_chan;
211 u8 *rx_buf;
212 dma_addr_t rx_dma_buf;
213 unsigned int rx_buf_sz;
214 u32 pcsel;
215 u32 smpr_val[2];
216 struct stm32_adc_calib cal;
217 };
218
219 /**
220 * struct stm32_adc_chan_spec - specification of stm32 adc channel
221 * @type: IIO channel type
222 * @channel: channel number (single ended)
223 * @name: channel name (single ended)
224 */
225 struct stm32_adc_chan_spec {
226 enum iio_chan_type type;
227 int channel;
228 const char *name;
229 };
230
231 /**
232 * struct stm32_adc_info - stm32 ADC, per instance config data
233 * @channels: Reference to stm32 channels spec
234 * @max_channels: Number of channels
235 * @resolutions: available resolutions
236 * @num_res: number of available resolutions
237 */
238 struct stm32_adc_info {
239 const struct stm32_adc_chan_spec *channels;
240 int max_channels;
241 const unsigned int *resolutions;
242 const unsigned int num_res;
243 };
244
245 /*
246 * Input definitions common for all instances:
247 * stm32f4 can have up to 16 channels
248 * stm32h7 can have up to 20 channels
249 */
250 static const struct stm32_adc_chan_spec stm32_adc_channels[] = {
251 { IIO_VOLTAGE, 0, "in0" },
252 { IIO_VOLTAGE, 1, "in1" },
253 { IIO_VOLTAGE, 2, "in2" },
254 { IIO_VOLTAGE, 3, "in3" },
255 { IIO_VOLTAGE, 4, "in4" },
256 { IIO_VOLTAGE, 5, "in5" },
257 { IIO_VOLTAGE, 6, "in6" },
258 { IIO_VOLTAGE, 7, "in7" },
259 { IIO_VOLTAGE, 8, "in8" },
260 { IIO_VOLTAGE, 9, "in9" },
261 { IIO_VOLTAGE, 10, "in10" },
262 { IIO_VOLTAGE, 11, "in11" },
263 { IIO_VOLTAGE, 12, "in12" },
264 { IIO_VOLTAGE, 13, "in13" },
265 { IIO_VOLTAGE, 14, "in14" },
266 { IIO_VOLTAGE, 15, "in15" },
267 { IIO_VOLTAGE, 16, "in16" },
268 { IIO_VOLTAGE, 17, "in17" },
269 { IIO_VOLTAGE, 18, "in18" },
270 { IIO_VOLTAGE, 19, "in19" },
271 };
272
273 static const unsigned int stm32f4_adc_resolutions[] = {
274 /* sorted values so the index matches RES[1:0] in STM32F4_ADC_CR1 */
275 12, 10, 8, 6,
276 };
277
278 static const struct stm32_adc_info stm32f4_adc_info = {
279 .channels = stm32_adc_channels,
280 .max_channels = 16,
281 .resolutions = stm32f4_adc_resolutions,
282 .num_res = ARRAY_SIZE(stm32f4_adc_resolutions),
283 };
284
285 static const unsigned int stm32h7_adc_resolutions[] = {
286 /* sorted values so the index matches RES[2:0] in STM32H7_ADC_CFGR */
287 16, 14, 12, 10, 8,
288 };
289
290 static const struct stm32_adc_info stm32h7_adc_info = {
291 .channels = stm32_adc_channels,
292 .max_channels = 20,
293 .resolutions = stm32h7_adc_resolutions,
294 .num_res = ARRAY_SIZE(stm32h7_adc_resolutions),
295 };
296
297 /**
298 * stm32f4_sq - describe regular sequence registers
299 * - L: sequence len (register & bit field)
300 * - SQ1..SQ16: sequence entries (register & bit field)
301 */
302 static const struct stm32_adc_regs stm32f4_sq[STM32_ADC_MAX_SQ + 1] = {
303 /* L: len bit field description to be kept as first element */
304 { STM32F4_ADC_SQR1, GENMASK(23, 20), 20 },
305 /* SQ1..SQ16 registers & bit fields (reg, mask, shift) */
306 { STM32F4_ADC_SQR3, GENMASK(4, 0), 0 },
307 { STM32F4_ADC_SQR3, GENMASK(9, 5), 5 },
308 { STM32F4_ADC_SQR3, GENMASK(14, 10), 10 },
309 { STM32F4_ADC_SQR3, GENMASK(19, 15), 15 },
310 { STM32F4_ADC_SQR3, GENMASK(24, 20), 20 },
311 { STM32F4_ADC_SQR3, GENMASK(29, 25), 25 },
312 { STM32F4_ADC_SQR2, GENMASK(4, 0), 0 },
313 { STM32F4_ADC_SQR2, GENMASK(9, 5), 5 },
314 { STM32F4_ADC_SQR2, GENMASK(14, 10), 10 },
315 { STM32F4_ADC_SQR2, GENMASK(19, 15), 15 },
316 { STM32F4_ADC_SQR2, GENMASK(24, 20), 20 },
317 { STM32F4_ADC_SQR2, GENMASK(29, 25), 25 },
318 { STM32F4_ADC_SQR1, GENMASK(4, 0), 0 },
319 { STM32F4_ADC_SQR1, GENMASK(9, 5), 5 },
320 { STM32F4_ADC_SQR1, GENMASK(14, 10), 10 },
321 { STM32F4_ADC_SQR1, GENMASK(19, 15), 15 },
322 };
323
324 /* STM32F4 external trigger sources for all instances */
325 static struct stm32_adc_trig_info stm32f4_adc_trigs[] = {
326 { TIM1_CH1, STM32_EXT0 },
327 { TIM1_CH2, STM32_EXT1 },
328 { TIM1_CH3, STM32_EXT2 },
329 { TIM2_CH2, STM32_EXT3 },
330 { TIM2_CH3, STM32_EXT4 },
331 { TIM2_CH4, STM32_EXT5 },
332 { TIM2_TRGO, STM32_EXT6 },
333 { TIM3_CH1, STM32_EXT7 },
334 { TIM3_TRGO, STM32_EXT8 },
335 { TIM4_CH4, STM32_EXT9 },
336 { TIM5_CH1, STM32_EXT10 },
337 { TIM5_CH2, STM32_EXT11 },
338 { TIM5_CH3, STM32_EXT12 },
339 { TIM8_CH1, STM32_EXT13 },
340 { TIM8_TRGO, STM32_EXT14 },
341 {}, /* sentinel */
342 };
343
344 /**
345 * stm32f4_smp_bits[] - describe sampling time register index & bit fields
346 * Sorted so it can be indexed by channel number.
347 */
348 static const struct stm32_adc_regs stm32f4_smp_bits[] = {
349 /* STM32F4_ADC_SMPR2: smpr[] index, mask, shift for SMP0 to SMP9 */
350 { 1, GENMASK(2, 0), 0 },
351 { 1, GENMASK(5, 3), 3 },
352 { 1, GENMASK(8, 6), 6 },
353 { 1, GENMASK(11, 9), 9 },
354 { 1, GENMASK(14, 12), 12 },
355 { 1, GENMASK(17, 15), 15 },
356 { 1, GENMASK(20, 18), 18 },
357 { 1, GENMASK(23, 21), 21 },
358 { 1, GENMASK(26, 24), 24 },
359 { 1, GENMASK(29, 27), 27 },
360 /* STM32F4_ADC_SMPR1, smpr[] index, mask, shift for SMP10 to SMP18 */
361 { 0, GENMASK(2, 0), 0 },
362 { 0, GENMASK(5, 3), 3 },
363 { 0, GENMASK(8, 6), 6 },
364 { 0, GENMASK(11, 9), 9 },
365 { 0, GENMASK(14, 12), 12 },
366 { 0, GENMASK(17, 15), 15 },
367 { 0, GENMASK(20, 18), 18 },
368 { 0, GENMASK(23, 21), 21 },
369 { 0, GENMASK(26, 24), 24 },
370 };
371
372 /* STM32F4 programmable sampling time (ADC clock cycles) */
373 static const unsigned int stm32f4_adc_smp_cycles[STM32_ADC_MAX_SMP + 1] = {
374 3, 15, 28, 56, 84, 112, 144, 480,
375 };
376
377 static const struct stm32_adc_regspec stm32f4_adc_regspec = {
378 .dr = STM32F4_ADC_DR,
379 .ier_eoc = { STM32F4_ADC_CR1, STM32F4_EOCIE },
380 .isr_eoc = { STM32F4_ADC_SR, STM32F4_EOC },
381 .sqr = stm32f4_sq,
382 .exten = { STM32F4_ADC_CR2, STM32F4_EXTEN_MASK, STM32F4_EXTEN_SHIFT },
383 .extsel = { STM32F4_ADC_CR2, STM32F4_EXTSEL_MASK,
384 STM32F4_EXTSEL_SHIFT },
385 .res = { STM32F4_ADC_CR1, STM32F4_RES_MASK, STM32F4_RES_SHIFT },
386 .smpr = { STM32F4_ADC_SMPR1, STM32F4_ADC_SMPR2 },
387 .smp_bits = stm32f4_smp_bits,
388 };
389
390 static const struct stm32_adc_regs stm32h7_sq[STM32_ADC_MAX_SQ + 1] = {
391 /* L: len bit field description to be kept as first element */
392 { STM32H7_ADC_SQR1, GENMASK(3, 0), 0 },
393 /* SQ1..SQ16 registers & bit fields (reg, mask, shift) */
394 { STM32H7_ADC_SQR1, GENMASK(10, 6), 6 },
395 { STM32H7_ADC_SQR1, GENMASK(16, 12), 12 },
396 { STM32H7_ADC_SQR1, GENMASK(22, 18), 18 },
397 { STM32H7_ADC_SQR1, GENMASK(28, 24), 24 },
398 { STM32H7_ADC_SQR2, GENMASK(4, 0), 0 },
399 { STM32H7_ADC_SQR2, GENMASK(10, 6), 6 },
400 { STM32H7_ADC_SQR2, GENMASK(16, 12), 12 },
401 { STM32H7_ADC_SQR2, GENMASK(22, 18), 18 },
402 { STM32H7_ADC_SQR2, GENMASK(28, 24), 24 },
403 { STM32H7_ADC_SQR3, GENMASK(4, 0), 0 },
404 { STM32H7_ADC_SQR3, GENMASK(10, 6), 6 },
405 { STM32H7_ADC_SQR3, GENMASK(16, 12), 12 },
406 { STM32H7_ADC_SQR3, GENMASK(22, 18), 18 },
407 { STM32H7_ADC_SQR3, GENMASK(28, 24), 24 },
408 { STM32H7_ADC_SQR4, GENMASK(4, 0), 0 },
409 { STM32H7_ADC_SQR4, GENMASK(10, 6), 6 },
410 };
411
412 /* STM32H7 external trigger sources for all instances */
413 static struct stm32_adc_trig_info stm32h7_adc_trigs[] = {
414 { TIM1_CH1, STM32_EXT0 },
415 { TIM1_CH2, STM32_EXT1 },
416 { TIM1_CH3, STM32_EXT2 },
417 { TIM2_CH2, STM32_EXT3 },
418 { TIM3_TRGO, STM32_EXT4 },
419 { TIM4_CH4, STM32_EXT5 },
420 { TIM8_TRGO, STM32_EXT7 },
421 { TIM8_TRGO2, STM32_EXT8 },
422 { TIM1_TRGO, STM32_EXT9 },
423 { TIM1_TRGO2, STM32_EXT10 },
424 { TIM2_TRGO, STM32_EXT11 },
425 { TIM4_TRGO, STM32_EXT12 },
426 { TIM6_TRGO, STM32_EXT13 },
427 { TIM3_CH4, STM32_EXT15 },
428 { LPTIM1_OUT, STM32_EXT18 },
429 { LPTIM2_OUT, STM32_EXT19 },
430 { LPTIM3_OUT, STM32_EXT20 },
431 {},
432 };
433
434 /**
435 * stm32h7_smp_bits - describe sampling time register index & bit fields
436 * Sorted so it can be indexed by channel number.
437 */
438 static const struct stm32_adc_regs stm32h7_smp_bits[] = {
439 /* STM32H7_ADC_SMPR1, smpr[] index, mask, shift for SMP0 to SMP9 */
440 { 0, GENMASK(2, 0), 0 },
441 { 0, GENMASK(5, 3), 3 },
442 { 0, GENMASK(8, 6), 6 },
443 { 0, GENMASK(11, 9), 9 },
444 { 0, GENMASK(14, 12), 12 },
445 { 0, GENMASK(17, 15), 15 },
446 { 0, GENMASK(20, 18), 18 },
447 { 0, GENMASK(23, 21), 21 },
448 { 0, GENMASK(26, 24), 24 },
449 { 0, GENMASK(29, 27), 27 },
450 /* STM32H7_ADC_SMPR2, smpr[] index, mask, shift for SMP10 to SMP19 */
451 { 1, GENMASK(2, 0), 0 },
452 { 1, GENMASK(5, 3), 3 },
453 { 1, GENMASK(8, 6), 6 },
454 { 1, GENMASK(11, 9), 9 },
455 { 1, GENMASK(14, 12), 12 },
456 { 1, GENMASK(17, 15), 15 },
457 { 1, GENMASK(20, 18), 18 },
458 { 1, GENMASK(23, 21), 21 },
459 { 1, GENMASK(26, 24), 24 },
460 { 1, GENMASK(29, 27), 27 },
461 };
462
463 /* STM32H7 programmable sampling time (ADC clock cycles, rounded down) */
464 static const unsigned int stm32h7_adc_smp_cycles[STM32_ADC_MAX_SMP + 1] = {
465 1, 2, 8, 16, 32, 64, 387, 810,
466 };
467
468 static const struct stm32_adc_regspec stm32h7_adc_regspec = {
469 .dr = STM32H7_ADC_DR,
470 .ier_eoc = { STM32H7_ADC_IER, STM32H7_EOCIE },
471 .isr_eoc = { STM32H7_ADC_ISR, STM32H7_EOC },
472 .sqr = stm32h7_sq,
473 .exten = { STM32H7_ADC_CFGR, STM32H7_EXTEN_MASK, STM32H7_EXTEN_SHIFT },
474 .extsel = { STM32H7_ADC_CFGR, STM32H7_EXTSEL_MASK,
475 STM32H7_EXTSEL_SHIFT },
476 .res = { STM32H7_ADC_CFGR, STM32H7_RES_MASK, STM32H7_RES_SHIFT },
477 .smpr = { STM32H7_ADC_SMPR1, STM32H7_ADC_SMPR2 },
478 .smp_bits = stm32h7_smp_bits,
479 };
480
481 /**
482 * STM32 ADC registers access routines
483 * @adc: stm32 adc instance
484 * @reg: reg offset in adc instance
485 *
486 * Note: All instances share same base, with 0x0, 0x100 or 0x200 offset resp.
487 * for adc1, adc2 and adc3.
488 */
stm32_adc_readl(struct stm32_adc * adc,u32 reg)489 static u32 stm32_adc_readl(struct stm32_adc *adc, u32 reg)
490 {
491 return readl_relaxed(adc->common->base + adc->offset + reg);
492 }
493
494 #define stm32_adc_readl_addr(addr) stm32_adc_readl(adc, addr)
495
496 #define stm32_adc_readl_poll_timeout(reg, val, cond, sleep_us, timeout_us) \
497 readx_poll_timeout(stm32_adc_readl_addr, reg, val, \
498 cond, sleep_us, timeout_us)
499
stm32_adc_readw(struct stm32_adc * adc,u32 reg)500 static u16 stm32_adc_readw(struct stm32_adc *adc, u32 reg)
501 {
502 return readw_relaxed(adc->common->base + adc->offset + reg);
503 }
504
stm32_adc_writel(struct stm32_adc * adc,u32 reg,u32 val)505 static void stm32_adc_writel(struct stm32_adc *adc, u32 reg, u32 val)
506 {
507 writel_relaxed(val, adc->common->base + adc->offset + reg);
508 }
509
stm32_adc_set_bits(struct stm32_adc * adc,u32 reg,u32 bits)510 static void stm32_adc_set_bits(struct stm32_adc *adc, u32 reg, u32 bits)
511 {
512 unsigned long flags;
513
514 spin_lock_irqsave(&adc->lock, flags);
515 stm32_adc_writel(adc, reg, stm32_adc_readl(adc, reg) | bits);
516 spin_unlock_irqrestore(&adc->lock, flags);
517 }
518
stm32_adc_clr_bits(struct stm32_adc * adc,u32 reg,u32 bits)519 static void stm32_adc_clr_bits(struct stm32_adc *adc, u32 reg, u32 bits)
520 {
521 unsigned long flags;
522
523 spin_lock_irqsave(&adc->lock, flags);
524 stm32_adc_writel(adc, reg, stm32_adc_readl(adc, reg) & ~bits);
525 spin_unlock_irqrestore(&adc->lock, flags);
526 }
527
528 /**
529 * stm32_adc_conv_irq_enable() - Enable end of conversion interrupt
530 * @adc: stm32 adc instance
531 */
stm32_adc_conv_irq_enable(struct stm32_adc * adc)532 static void stm32_adc_conv_irq_enable(struct stm32_adc *adc)
533 {
534 stm32_adc_set_bits(adc, adc->cfg->regs->ier_eoc.reg,
535 adc->cfg->regs->ier_eoc.mask);
536 };
537
538 /**
539 * stm32_adc_conv_irq_disable() - Disable end of conversion interrupt
540 * @adc: stm32 adc instance
541 */
stm32_adc_conv_irq_disable(struct stm32_adc * adc)542 static void stm32_adc_conv_irq_disable(struct stm32_adc *adc)
543 {
544 stm32_adc_clr_bits(adc, adc->cfg->regs->ier_eoc.reg,
545 adc->cfg->regs->ier_eoc.mask);
546 }
547
stm32_adc_set_res(struct stm32_adc * adc)548 static void stm32_adc_set_res(struct stm32_adc *adc)
549 {
550 const struct stm32_adc_regs *res = &adc->cfg->regs->res;
551 u32 val;
552
553 val = stm32_adc_readl(adc, res->reg);
554 val = (val & ~res->mask) | (adc->res << res->shift);
555 stm32_adc_writel(adc, res->reg, val);
556 }
557
558 /**
559 * stm32f4_adc_start_conv() - Start conversions for regular channels.
560 * @adc: stm32 adc instance
561 * @dma: use dma to transfer conversion result
562 *
563 * Start conversions for regular channels.
564 * Also take care of normal or DMA mode. Circular DMA may be used for regular
565 * conversions, in IIO buffer modes. Otherwise, use ADC interrupt with direct
566 * DR read instead (e.g. read_raw, or triggered buffer mode without DMA).
567 */
stm32f4_adc_start_conv(struct stm32_adc * adc,bool dma)568 static void stm32f4_adc_start_conv(struct stm32_adc *adc, bool dma)
569 {
570 stm32_adc_set_bits(adc, STM32F4_ADC_CR1, STM32F4_SCAN);
571
572 if (dma)
573 stm32_adc_set_bits(adc, STM32F4_ADC_CR2,
574 STM32F4_DMA | STM32F4_DDS);
575
576 stm32_adc_set_bits(adc, STM32F4_ADC_CR2, STM32F4_EOCS | STM32F4_ADON);
577
578 /* Wait for Power-up time (tSTAB from datasheet) */
579 usleep_range(2, 3);
580
581 /* Software start ? (e.g. trigger detection disabled ?) */
582 if (!(stm32_adc_readl(adc, STM32F4_ADC_CR2) & STM32F4_EXTEN_MASK))
583 stm32_adc_set_bits(adc, STM32F4_ADC_CR2, STM32F4_SWSTART);
584 }
585
stm32f4_adc_stop_conv(struct stm32_adc * adc)586 static void stm32f4_adc_stop_conv(struct stm32_adc *adc)
587 {
588 stm32_adc_clr_bits(adc, STM32F4_ADC_CR2, STM32F4_EXTEN_MASK);
589 stm32_adc_clr_bits(adc, STM32F4_ADC_SR, STM32F4_STRT);
590
591 stm32_adc_clr_bits(adc, STM32F4_ADC_CR1, STM32F4_SCAN);
592 stm32_adc_clr_bits(adc, STM32F4_ADC_CR2,
593 STM32F4_ADON | STM32F4_DMA | STM32F4_DDS);
594 }
595
stm32h7_adc_start_conv(struct stm32_adc * adc,bool dma)596 static void stm32h7_adc_start_conv(struct stm32_adc *adc, bool dma)
597 {
598 enum stm32h7_adc_dmngt dmngt;
599 unsigned long flags;
600 u32 val;
601
602 if (dma)
603 dmngt = STM32H7_DMNGT_DMA_CIRC;
604 else
605 dmngt = STM32H7_DMNGT_DR_ONLY;
606
607 spin_lock_irqsave(&adc->lock, flags);
608 val = stm32_adc_readl(adc, STM32H7_ADC_CFGR);
609 val = (val & ~STM32H7_DMNGT_MASK) | (dmngt << STM32H7_DMNGT_SHIFT);
610 stm32_adc_writel(adc, STM32H7_ADC_CFGR, val);
611 spin_unlock_irqrestore(&adc->lock, flags);
612
613 stm32_adc_set_bits(adc, STM32H7_ADC_CR, STM32H7_ADSTART);
614 }
615
stm32h7_adc_stop_conv(struct stm32_adc * adc)616 static void stm32h7_adc_stop_conv(struct stm32_adc *adc)
617 {
618 struct iio_dev *indio_dev = iio_priv_to_dev(adc);
619 int ret;
620 u32 val;
621
622 stm32_adc_set_bits(adc, STM32H7_ADC_CR, STM32H7_ADSTP);
623
624 ret = stm32_adc_readl_poll_timeout(STM32H7_ADC_CR, val,
625 !(val & (STM32H7_ADSTART)),
626 100, STM32_ADC_TIMEOUT_US);
627 if (ret)
628 dev_warn(&indio_dev->dev, "stop failed\n");
629
630 stm32_adc_clr_bits(adc, STM32H7_ADC_CFGR, STM32H7_DMNGT_MASK);
631 }
632
stm32h7_adc_exit_pwr_down(struct stm32_adc * adc)633 static void stm32h7_adc_exit_pwr_down(struct stm32_adc *adc)
634 {
635 /* Exit deep power down, then enable ADC voltage regulator */
636 stm32_adc_clr_bits(adc, STM32H7_ADC_CR, STM32H7_DEEPPWD);
637 stm32_adc_set_bits(adc, STM32H7_ADC_CR, STM32H7_ADVREGEN);
638
639 if (adc->common->rate > STM32H7_BOOST_CLKRATE)
640 stm32_adc_set_bits(adc, STM32H7_ADC_CR, STM32H7_BOOST);
641
642 /* Wait for startup time */
643 usleep_range(10, 20);
644 }
645
stm32h7_adc_enter_pwr_down(struct stm32_adc * adc)646 static void stm32h7_adc_enter_pwr_down(struct stm32_adc *adc)
647 {
648 stm32_adc_clr_bits(adc, STM32H7_ADC_CR, STM32H7_BOOST);
649
650 /* Setting DEEPPWD disables ADC vreg and clears ADVREGEN */
651 stm32_adc_set_bits(adc, STM32H7_ADC_CR, STM32H7_DEEPPWD);
652 }
653
stm32h7_adc_enable(struct stm32_adc * adc)654 static int stm32h7_adc_enable(struct stm32_adc *adc)
655 {
656 struct iio_dev *indio_dev = iio_priv_to_dev(adc);
657 int ret;
658 u32 val;
659
660 stm32_adc_set_bits(adc, STM32H7_ADC_CR, STM32H7_ADEN);
661
662 /* Poll for ADRDY to be set (after adc startup time) */
663 ret = stm32_adc_readl_poll_timeout(STM32H7_ADC_ISR, val,
664 val & STM32H7_ADRDY,
665 100, STM32_ADC_TIMEOUT_US);
666 if (ret) {
667 stm32_adc_set_bits(adc, STM32H7_ADC_CR, STM32H7_ADDIS);
668 dev_err(&indio_dev->dev, "Failed to enable ADC\n");
669 } else {
670 /* Clear ADRDY by writing one */
671 stm32_adc_set_bits(adc, STM32H7_ADC_ISR, STM32H7_ADRDY);
672 }
673
674 return ret;
675 }
676
stm32h7_adc_disable(struct stm32_adc * adc)677 static void stm32h7_adc_disable(struct stm32_adc *adc)
678 {
679 struct iio_dev *indio_dev = iio_priv_to_dev(adc);
680 int ret;
681 u32 val;
682
683 /* Disable ADC and wait until it's effectively disabled */
684 stm32_adc_set_bits(adc, STM32H7_ADC_CR, STM32H7_ADDIS);
685 ret = stm32_adc_readl_poll_timeout(STM32H7_ADC_CR, val,
686 !(val & STM32H7_ADEN), 100,
687 STM32_ADC_TIMEOUT_US);
688 if (ret)
689 dev_warn(&indio_dev->dev, "Failed to disable\n");
690 }
691
692 /**
693 * stm32h7_adc_read_selfcalib() - read calibration shadow regs, save result
694 * @adc: stm32 adc instance
695 */
stm32h7_adc_read_selfcalib(struct stm32_adc * adc)696 static int stm32h7_adc_read_selfcalib(struct stm32_adc *adc)
697 {
698 struct iio_dev *indio_dev = iio_priv_to_dev(adc);
699 int i, ret;
700 u32 lincalrdyw_mask, val;
701
702 /* Enable adc so LINCALRDYW1..6 bits are writable */
703 ret = stm32h7_adc_enable(adc);
704 if (ret)
705 return ret;
706
707 /* Read linearity calibration */
708 lincalrdyw_mask = STM32H7_LINCALRDYW6;
709 for (i = STM32H7_LINCALFACT_NUM - 1; i >= 0; i--) {
710 /* Clear STM32H7_LINCALRDYW[6..1]: transfer calib to CALFACT2 */
711 stm32_adc_clr_bits(adc, STM32H7_ADC_CR, lincalrdyw_mask);
712
713 /* Poll: wait calib data to be ready in CALFACT2 register */
714 ret = stm32_adc_readl_poll_timeout(STM32H7_ADC_CR, val,
715 !(val & lincalrdyw_mask),
716 100, STM32_ADC_TIMEOUT_US);
717 if (ret) {
718 dev_err(&indio_dev->dev, "Failed to read calfact\n");
719 goto disable;
720 }
721
722 val = stm32_adc_readl(adc, STM32H7_ADC_CALFACT2);
723 adc->cal.lincalfact[i] = (val & STM32H7_LINCALFACT_MASK);
724 adc->cal.lincalfact[i] >>= STM32H7_LINCALFACT_SHIFT;
725
726 lincalrdyw_mask >>= 1;
727 }
728
729 /* Read offset calibration */
730 val = stm32_adc_readl(adc, STM32H7_ADC_CALFACT);
731 adc->cal.calfact_s = (val & STM32H7_CALFACT_S_MASK);
732 adc->cal.calfact_s >>= STM32H7_CALFACT_S_SHIFT;
733 adc->cal.calfact_d = (val & STM32H7_CALFACT_D_MASK);
734 adc->cal.calfact_d >>= STM32H7_CALFACT_D_SHIFT;
735
736 disable:
737 stm32h7_adc_disable(adc);
738
739 return ret;
740 }
741
742 /**
743 * stm32h7_adc_restore_selfcalib() - Restore saved self-calibration result
744 * @adc: stm32 adc instance
745 * Note: ADC must be enabled, with no on-going conversions.
746 */
stm32h7_adc_restore_selfcalib(struct stm32_adc * adc)747 static int stm32h7_adc_restore_selfcalib(struct stm32_adc *adc)
748 {
749 struct iio_dev *indio_dev = iio_priv_to_dev(adc);
750 int i, ret;
751 u32 lincalrdyw_mask, val;
752
753 val = (adc->cal.calfact_s << STM32H7_CALFACT_S_SHIFT) |
754 (adc->cal.calfact_d << STM32H7_CALFACT_D_SHIFT);
755 stm32_adc_writel(adc, STM32H7_ADC_CALFACT, val);
756
757 lincalrdyw_mask = STM32H7_LINCALRDYW6;
758 for (i = STM32H7_LINCALFACT_NUM - 1; i >= 0; i--) {
759 /*
760 * Write saved calibration data to shadow registers:
761 * Write CALFACT2, and set LINCALRDYW[6..1] bit to trigger
762 * data write. Then poll to wait for complete transfer.
763 */
764 val = adc->cal.lincalfact[i] << STM32H7_LINCALFACT_SHIFT;
765 stm32_adc_writel(adc, STM32H7_ADC_CALFACT2, val);
766 stm32_adc_set_bits(adc, STM32H7_ADC_CR, lincalrdyw_mask);
767 ret = stm32_adc_readl_poll_timeout(STM32H7_ADC_CR, val,
768 val & lincalrdyw_mask,
769 100, STM32_ADC_TIMEOUT_US);
770 if (ret) {
771 dev_err(&indio_dev->dev, "Failed to write calfact\n");
772 return ret;
773 }
774
775 /*
776 * Read back calibration data, has two effects:
777 * - It ensures bits LINCALRDYW[6..1] are kept cleared
778 * for next time calibration needs to be restored.
779 * - BTW, bit clear triggers a read, then check data has been
780 * correctly written.
781 */
782 stm32_adc_clr_bits(adc, STM32H7_ADC_CR, lincalrdyw_mask);
783 ret = stm32_adc_readl_poll_timeout(STM32H7_ADC_CR, val,
784 !(val & lincalrdyw_mask),
785 100, STM32_ADC_TIMEOUT_US);
786 if (ret) {
787 dev_err(&indio_dev->dev, "Failed to read calfact\n");
788 return ret;
789 }
790 val = stm32_adc_readl(adc, STM32H7_ADC_CALFACT2);
791 if (val != adc->cal.lincalfact[i] << STM32H7_LINCALFACT_SHIFT) {
792 dev_err(&indio_dev->dev, "calfact not consistent\n");
793 return -EIO;
794 }
795
796 lincalrdyw_mask >>= 1;
797 }
798
799 return 0;
800 }
801
802 /**
803 * Fixed timeout value for ADC calibration.
804 * worst cases:
805 * - low clock frequency
806 * - maximum prescalers
807 * Calibration requires:
808 * - 131,072 ADC clock cycle for the linear calibration
809 * - 20 ADC clock cycle for the offset calibration
810 *
811 * Set to 100ms for now
812 */
813 #define STM32H7_ADC_CALIB_TIMEOUT_US 100000
814
815 /**
816 * stm32h7_adc_selfcalib() - Procedure to calibrate ADC (from power down)
817 * @adc: stm32 adc instance
818 * Exit from power down, calibrate ADC, then return to power down.
819 */
stm32h7_adc_selfcalib(struct stm32_adc * adc)820 static int stm32h7_adc_selfcalib(struct stm32_adc *adc)
821 {
822 struct iio_dev *indio_dev = iio_priv_to_dev(adc);
823 int ret;
824 u32 val;
825
826 stm32h7_adc_exit_pwr_down(adc);
827
828 /*
829 * Select calibration mode:
830 * - Offset calibration for single ended inputs
831 * - No linearity calibration (do it later, before reading it)
832 */
833 stm32_adc_clr_bits(adc, STM32H7_ADC_CR, STM32H7_ADCALDIF);
834 stm32_adc_clr_bits(adc, STM32H7_ADC_CR, STM32H7_ADCALLIN);
835
836 /* Start calibration, then wait for completion */
837 stm32_adc_set_bits(adc, STM32H7_ADC_CR, STM32H7_ADCAL);
838 ret = stm32_adc_readl_poll_timeout(STM32H7_ADC_CR, val,
839 !(val & STM32H7_ADCAL), 100,
840 STM32H7_ADC_CALIB_TIMEOUT_US);
841 if (ret) {
842 dev_err(&indio_dev->dev, "calibration failed\n");
843 goto pwr_dwn;
844 }
845
846 /*
847 * Select calibration mode, then start calibration:
848 * - Offset calibration for differential input
849 * - Linearity calibration (needs to be done only once for single/diff)
850 * will run simultaneously with offset calibration.
851 */
852 stm32_adc_set_bits(adc, STM32H7_ADC_CR,
853 STM32H7_ADCALDIF | STM32H7_ADCALLIN);
854 stm32_adc_set_bits(adc, STM32H7_ADC_CR, STM32H7_ADCAL);
855 ret = stm32_adc_readl_poll_timeout(STM32H7_ADC_CR, val,
856 !(val & STM32H7_ADCAL), 100,
857 STM32H7_ADC_CALIB_TIMEOUT_US);
858 if (ret) {
859 dev_err(&indio_dev->dev, "calibration failed\n");
860 goto pwr_dwn;
861 }
862
863 stm32_adc_clr_bits(adc, STM32H7_ADC_CR,
864 STM32H7_ADCALDIF | STM32H7_ADCALLIN);
865
866 /* Read calibration result for future reference */
867 ret = stm32h7_adc_read_selfcalib(adc);
868
869 pwr_dwn:
870 stm32h7_adc_enter_pwr_down(adc);
871
872 return ret;
873 }
874
875 /**
876 * stm32h7_adc_prepare() - Leave power down mode to enable ADC.
877 * @adc: stm32 adc instance
878 * Leave power down mode.
879 * Enable ADC.
880 * Restore calibration data.
881 * Pre-select channels that may be used in PCSEL (required by input MUX / IO).
882 */
stm32h7_adc_prepare(struct stm32_adc * adc)883 static int stm32h7_adc_prepare(struct stm32_adc *adc)
884 {
885 int ret;
886
887 stm32h7_adc_exit_pwr_down(adc);
888
889 ret = stm32h7_adc_enable(adc);
890 if (ret)
891 goto pwr_dwn;
892
893 ret = stm32h7_adc_restore_selfcalib(adc);
894 if (ret)
895 goto disable;
896
897 stm32_adc_writel(adc, STM32H7_ADC_PCSEL, adc->pcsel);
898
899 return 0;
900
901 disable:
902 stm32h7_adc_disable(adc);
903 pwr_dwn:
904 stm32h7_adc_enter_pwr_down(adc);
905
906 return ret;
907 }
908
stm32h7_adc_unprepare(struct stm32_adc * adc)909 static void stm32h7_adc_unprepare(struct stm32_adc *adc)
910 {
911 stm32h7_adc_disable(adc);
912 stm32h7_adc_enter_pwr_down(adc);
913 }
914
915 /**
916 * stm32_adc_conf_scan_seq() - Build regular channels scan sequence
917 * @indio_dev: IIO device
918 * @scan_mask: channels to be converted
919 *
920 * Conversion sequence :
921 * Apply sampling time settings for all channels.
922 * Configure ADC scan sequence based on selected channels in scan_mask.
923 * Add channels to SQR registers, from scan_mask LSB to MSB, then
924 * program sequence len.
925 */
stm32_adc_conf_scan_seq(struct iio_dev * indio_dev,const unsigned long * scan_mask)926 static int stm32_adc_conf_scan_seq(struct iio_dev *indio_dev,
927 const unsigned long *scan_mask)
928 {
929 struct stm32_adc *adc = iio_priv(indio_dev);
930 const struct stm32_adc_regs *sqr = adc->cfg->regs->sqr;
931 const struct iio_chan_spec *chan;
932 u32 val, bit;
933 int i = 0;
934
935 /* Apply sampling time settings */
936 stm32_adc_writel(adc, adc->cfg->regs->smpr[0], adc->smpr_val[0]);
937 stm32_adc_writel(adc, adc->cfg->regs->smpr[1], adc->smpr_val[1]);
938
939 for_each_set_bit(bit, scan_mask, indio_dev->masklength) {
940 chan = indio_dev->channels + bit;
941 /*
942 * Assign one channel per SQ entry in regular
943 * sequence, starting with SQ1.
944 */
945 i++;
946 if (i > STM32_ADC_MAX_SQ)
947 return -EINVAL;
948
949 dev_dbg(&indio_dev->dev, "%s chan %d to SQ%d\n",
950 __func__, chan->channel, i);
951
952 val = stm32_adc_readl(adc, sqr[i].reg);
953 val &= ~sqr[i].mask;
954 val |= chan->channel << sqr[i].shift;
955 stm32_adc_writel(adc, sqr[i].reg, val);
956 }
957
958 if (!i)
959 return -EINVAL;
960
961 /* Sequence len */
962 val = stm32_adc_readl(adc, sqr[0].reg);
963 val &= ~sqr[0].mask;
964 val |= ((i - 1) << sqr[0].shift);
965 stm32_adc_writel(adc, sqr[0].reg, val);
966
967 return 0;
968 }
969
970 /**
971 * stm32_adc_get_trig_extsel() - Get external trigger selection
972 * @trig: trigger
973 *
974 * Returns trigger extsel value, if trig matches, -EINVAL otherwise.
975 */
stm32_adc_get_trig_extsel(struct iio_dev * indio_dev,struct iio_trigger * trig)976 static int stm32_adc_get_trig_extsel(struct iio_dev *indio_dev,
977 struct iio_trigger *trig)
978 {
979 struct stm32_adc *adc = iio_priv(indio_dev);
980 int i;
981
982 /* lookup triggers registered by stm32 timer trigger driver */
983 for (i = 0; adc->cfg->trigs[i].name; i++) {
984 /**
985 * Checking both stm32 timer trigger type and trig name
986 * should be safe against arbitrary trigger names.
987 */
988 if ((is_stm32_timer_trigger(trig) ||
989 is_stm32_lptim_trigger(trig)) &&
990 !strcmp(adc->cfg->trigs[i].name, trig->name)) {
991 return adc->cfg->trigs[i].extsel;
992 }
993 }
994
995 return -EINVAL;
996 }
997
998 /**
999 * stm32_adc_set_trig() - Set a regular trigger
1000 * @indio_dev: IIO device
1001 * @trig: IIO trigger
1002 *
1003 * Set trigger source/polarity (e.g. SW, or HW with polarity) :
1004 * - if HW trigger disabled (e.g. trig == NULL, conversion launched by sw)
1005 * - if HW trigger enabled, set source & polarity
1006 */
stm32_adc_set_trig(struct iio_dev * indio_dev,struct iio_trigger * trig)1007 static int stm32_adc_set_trig(struct iio_dev *indio_dev,
1008 struct iio_trigger *trig)
1009 {
1010 struct stm32_adc *adc = iio_priv(indio_dev);
1011 u32 val, extsel = 0, exten = STM32_EXTEN_SWTRIG;
1012 unsigned long flags;
1013 int ret;
1014
1015 if (trig) {
1016 ret = stm32_adc_get_trig_extsel(indio_dev, trig);
1017 if (ret < 0)
1018 return ret;
1019
1020 /* set trigger source and polarity (default to rising edge) */
1021 extsel = ret;
1022 exten = adc->trigger_polarity + STM32_EXTEN_HWTRIG_RISING_EDGE;
1023 }
1024
1025 spin_lock_irqsave(&adc->lock, flags);
1026 val = stm32_adc_readl(adc, adc->cfg->regs->exten.reg);
1027 val &= ~(adc->cfg->regs->exten.mask | adc->cfg->regs->extsel.mask);
1028 val |= exten << adc->cfg->regs->exten.shift;
1029 val |= extsel << adc->cfg->regs->extsel.shift;
1030 stm32_adc_writel(adc, adc->cfg->regs->exten.reg, val);
1031 spin_unlock_irqrestore(&adc->lock, flags);
1032
1033 return 0;
1034 }
1035
stm32_adc_set_trig_pol(struct iio_dev * indio_dev,const struct iio_chan_spec * chan,unsigned int type)1036 static int stm32_adc_set_trig_pol(struct iio_dev *indio_dev,
1037 const struct iio_chan_spec *chan,
1038 unsigned int type)
1039 {
1040 struct stm32_adc *adc = iio_priv(indio_dev);
1041
1042 adc->trigger_polarity = type;
1043
1044 return 0;
1045 }
1046
stm32_adc_get_trig_pol(struct iio_dev * indio_dev,const struct iio_chan_spec * chan)1047 static int stm32_adc_get_trig_pol(struct iio_dev *indio_dev,
1048 const struct iio_chan_spec *chan)
1049 {
1050 struct stm32_adc *adc = iio_priv(indio_dev);
1051
1052 return adc->trigger_polarity;
1053 }
1054
1055 static const char * const stm32_trig_pol_items[] = {
1056 "rising-edge", "falling-edge", "both-edges",
1057 };
1058
1059 static const struct iio_enum stm32_adc_trig_pol = {
1060 .items = stm32_trig_pol_items,
1061 .num_items = ARRAY_SIZE(stm32_trig_pol_items),
1062 .get = stm32_adc_get_trig_pol,
1063 .set = stm32_adc_set_trig_pol,
1064 };
1065
1066 /**
1067 * stm32_adc_single_conv() - Performs a single conversion
1068 * @indio_dev: IIO device
1069 * @chan: IIO channel
1070 * @res: conversion result
1071 *
1072 * The function performs a single conversion on a given channel:
1073 * - Apply sampling time settings
1074 * - Program sequencer with one channel (e.g. in SQ1 with len = 1)
1075 * - Use SW trigger
1076 * - Start conversion, then wait for interrupt completion.
1077 */
stm32_adc_single_conv(struct iio_dev * indio_dev,const struct iio_chan_spec * chan,int * res)1078 static int stm32_adc_single_conv(struct iio_dev *indio_dev,
1079 const struct iio_chan_spec *chan,
1080 int *res)
1081 {
1082 struct stm32_adc *adc = iio_priv(indio_dev);
1083 const struct stm32_adc_regspec *regs = adc->cfg->regs;
1084 long timeout;
1085 u32 val;
1086 int ret;
1087
1088 reinit_completion(&adc->completion);
1089
1090 adc->bufi = 0;
1091
1092 if (adc->cfg->prepare) {
1093 ret = adc->cfg->prepare(adc);
1094 if (ret)
1095 return ret;
1096 }
1097
1098 /* Apply sampling time settings */
1099 stm32_adc_writel(adc, regs->smpr[0], adc->smpr_val[0]);
1100 stm32_adc_writel(adc, regs->smpr[1], adc->smpr_val[1]);
1101
1102 /* Program chan number in regular sequence (SQ1) */
1103 val = stm32_adc_readl(adc, regs->sqr[1].reg);
1104 val &= ~regs->sqr[1].mask;
1105 val |= chan->channel << regs->sqr[1].shift;
1106 stm32_adc_writel(adc, regs->sqr[1].reg, val);
1107
1108 /* Set regular sequence len (0 for 1 conversion) */
1109 stm32_adc_clr_bits(adc, regs->sqr[0].reg, regs->sqr[0].mask);
1110
1111 /* Trigger detection disabled (conversion can be launched in SW) */
1112 stm32_adc_clr_bits(adc, regs->exten.reg, regs->exten.mask);
1113
1114 stm32_adc_conv_irq_enable(adc);
1115
1116 adc->cfg->start_conv(adc, false);
1117
1118 timeout = wait_for_completion_interruptible_timeout(
1119 &adc->completion, STM32_ADC_TIMEOUT);
1120 if (timeout == 0) {
1121 ret = -ETIMEDOUT;
1122 } else if (timeout < 0) {
1123 ret = timeout;
1124 } else {
1125 *res = adc->buffer[0];
1126 ret = IIO_VAL_INT;
1127 }
1128
1129 adc->cfg->stop_conv(adc);
1130
1131 stm32_adc_conv_irq_disable(adc);
1132
1133 if (adc->cfg->unprepare)
1134 adc->cfg->unprepare(adc);
1135
1136 return ret;
1137 }
1138
stm32_adc_read_raw(struct iio_dev * indio_dev,struct iio_chan_spec const * chan,int * val,int * val2,long mask)1139 static int stm32_adc_read_raw(struct iio_dev *indio_dev,
1140 struct iio_chan_spec const *chan,
1141 int *val, int *val2, long mask)
1142 {
1143 struct stm32_adc *adc = iio_priv(indio_dev);
1144 int ret;
1145
1146 switch (mask) {
1147 case IIO_CHAN_INFO_RAW:
1148 ret = iio_device_claim_direct_mode(indio_dev);
1149 if (ret)
1150 return ret;
1151 if (chan->type == IIO_VOLTAGE)
1152 ret = stm32_adc_single_conv(indio_dev, chan, val);
1153 else
1154 ret = -EINVAL;
1155 iio_device_release_direct_mode(indio_dev);
1156 return ret;
1157
1158 case IIO_CHAN_INFO_SCALE:
1159 *val = adc->common->vref_mv;
1160 *val2 = chan->scan_type.realbits;
1161 return IIO_VAL_FRACTIONAL_LOG2;
1162
1163 default:
1164 return -EINVAL;
1165 }
1166 }
1167
stm32_adc_isr(int irq,void * data)1168 static irqreturn_t stm32_adc_isr(int irq, void *data)
1169 {
1170 struct stm32_adc *adc = data;
1171 struct iio_dev *indio_dev = iio_priv_to_dev(adc);
1172 const struct stm32_adc_regspec *regs = adc->cfg->regs;
1173 u32 status = stm32_adc_readl(adc, regs->isr_eoc.reg);
1174
1175 if (status & regs->isr_eoc.mask) {
1176 /* Reading DR also clears EOC status flag */
1177 adc->buffer[adc->bufi] = stm32_adc_readw(adc, regs->dr);
1178 if (iio_buffer_enabled(indio_dev)) {
1179 adc->bufi++;
1180 if (adc->bufi >= adc->num_conv) {
1181 stm32_adc_conv_irq_disable(adc);
1182 iio_trigger_poll(indio_dev->trig);
1183 }
1184 } else {
1185 complete(&adc->completion);
1186 }
1187 return IRQ_HANDLED;
1188 }
1189
1190 return IRQ_NONE;
1191 }
1192
1193 /**
1194 * stm32_adc_validate_trigger() - validate trigger for stm32 adc
1195 * @indio_dev: IIO device
1196 * @trig: new trigger
1197 *
1198 * Returns: 0 if trig matches one of the triggers registered by stm32 adc
1199 * driver, -EINVAL otherwise.
1200 */
stm32_adc_validate_trigger(struct iio_dev * indio_dev,struct iio_trigger * trig)1201 static int stm32_adc_validate_trigger(struct iio_dev *indio_dev,
1202 struct iio_trigger *trig)
1203 {
1204 return stm32_adc_get_trig_extsel(indio_dev, trig) < 0 ? -EINVAL : 0;
1205 }
1206
stm32_adc_set_watermark(struct iio_dev * indio_dev,unsigned int val)1207 static int stm32_adc_set_watermark(struct iio_dev *indio_dev, unsigned int val)
1208 {
1209 struct stm32_adc *adc = iio_priv(indio_dev);
1210 unsigned int watermark = STM32_DMA_BUFFER_SIZE / 2;
1211 unsigned int rx_buf_sz = STM32_DMA_BUFFER_SIZE;
1212
1213 /*
1214 * dma cyclic transfers are used, buffer is split into two periods.
1215 * There should be :
1216 * - always one buffer (period) dma is working on
1217 * - one buffer (period) driver can push with iio_trigger_poll().
1218 */
1219 watermark = min(watermark, val * (unsigned)(sizeof(u16)));
1220 adc->rx_buf_sz = min(rx_buf_sz, watermark * 2 * adc->num_conv);
1221
1222 return 0;
1223 }
1224
stm32_adc_update_scan_mode(struct iio_dev * indio_dev,const unsigned long * scan_mask)1225 static int stm32_adc_update_scan_mode(struct iio_dev *indio_dev,
1226 const unsigned long *scan_mask)
1227 {
1228 struct stm32_adc *adc = iio_priv(indio_dev);
1229 int ret;
1230
1231 adc->num_conv = bitmap_weight(scan_mask, indio_dev->masklength);
1232
1233 ret = stm32_adc_conf_scan_seq(indio_dev, scan_mask);
1234 if (ret)
1235 return ret;
1236
1237 return 0;
1238 }
1239
stm32_adc_of_xlate(struct iio_dev * indio_dev,const struct of_phandle_args * iiospec)1240 static int stm32_adc_of_xlate(struct iio_dev *indio_dev,
1241 const struct of_phandle_args *iiospec)
1242 {
1243 int i;
1244
1245 for (i = 0; i < indio_dev->num_channels; i++)
1246 if (indio_dev->channels[i].channel == iiospec->args[0])
1247 return i;
1248
1249 return -EINVAL;
1250 }
1251
1252 /**
1253 * stm32_adc_debugfs_reg_access - read or write register value
1254 *
1255 * To read a value from an ADC register:
1256 * echo [ADC reg offset] > direct_reg_access
1257 * cat direct_reg_access
1258 *
1259 * To write a value in a ADC register:
1260 * echo [ADC_reg_offset] [value] > direct_reg_access
1261 */
stm32_adc_debugfs_reg_access(struct iio_dev * indio_dev,unsigned reg,unsigned writeval,unsigned * readval)1262 static int stm32_adc_debugfs_reg_access(struct iio_dev *indio_dev,
1263 unsigned reg, unsigned writeval,
1264 unsigned *readval)
1265 {
1266 struct stm32_adc *adc = iio_priv(indio_dev);
1267
1268 if (!readval)
1269 stm32_adc_writel(adc, reg, writeval);
1270 else
1271 *readval = stm32_adc_readl(adc, reg);
1272
1273 return 0;
1274 }
1275
1276 static const struct iio_info stm32_adc_iio_info = {
1277 .read_raw = stm32_adc_read_raw,
1278 .validate_trigger = stm32_adc_validate_trigger,
1279 .hwfifo_set_watermark = stm32_adc_set_watermark,
1280 .update_scan_mode = stm32_adc_update_scan_mode,
1281 .debugfs_reg_access = stm32_adc_debugfs_reg_access,
1282 .of_xlate = stm32_adc_of_xlate,
1283 .driver_module = THIS_MODULE,
1284 };
1285
stm32_adc_dma_residue(struct stm32_adc * adc)1286 static unsigned int stm32_adc_dma_residue(struct stm32_adc *adc)
1287 {
1288 struct dma_tx_state state;
1289 enum dma_status status;
1290
1291 status = dmaengine_tx_status(adc->dma_chan,
1292 adc->dma_chan->cookie,
1293 &state);
1294 if (status == DMA_IN_PROGRESS) {
1295 /* Residue is size in bytes from end of buffer */
1296 unsigned int i = adc->rx_buf_sz - state.residue;
1297 unsigned int size;
1298
1299 /* Return available bytes */
1300 if (i >= adc->bufi)
1301 size = i - adc->bufi;
1302 else
1303 size = adc->rx_buf_sz + i - adc->bufi;
1304
1305 return size;
1306 }
1307
1308 return 0;
1309 }
1310
stm32_adc_dma_buffer_done(void * data)1311 static void stm32_adc_dma_buffer_done(void *data)
1312 {
1313 struct iio_dev *indio_dev = data;
1314
1315 iio_trigger_poll_chained(indio_dev->trig);
1316 }
1317
stm32_adc_dma_start(struct iio_dev * indio_dev)1318 static int stm32_adc_dma_start(struct iio_dev *indio_dev)
1319 {
1320 struct stm32_adc *adc = iio_priv(indio_dev);
1321 struct dma_async_tx_descriptor *desc;
1322 dma_cookie_t cookie;
1323 int ret;
1324
1325 if (!adc->dma_chan)
1326 return 0;
1327
1328 dev_dbg(&indio_dev->dev, "%s size=%d watermark=%d\n", __func__,
1329 adc->rx_buf_sz, adc->rx_buf_sz / 2);
1330
1331 /* Prepare a DMA cyclic transaction */
1332 desc = dmaengine_prep_dma_cyclic(adc->dma_chan,
1333 adc->rx_dma_buf,
1334 adc->rx_buf_sz, adc->rx_buf_sz / 2,
1335 DMA_DEV_TO_MEM,
1336 DMA_PREP_INTERRUPT);
1337 if (!desc)
1338 return -EBUSY;
1339
1340 desc->callback = stm32_adc_dma_buffer_done;
1341 desc->callback_param = indio_dev;
1342
1343 cookie = dmaengine_submit(desc);
1344 ret = dma_submit_error(cookie);
1345 if (ret) {
1346 dmaengine_terminate_sync(adc->dma_chan);
1347 return ret;
1348 }
1349
1350 /* Issue pending DMA requests */
1351 dma_async_issue_pending(adc->dma_chan);
1352
1353 return 0;
1354 }
1355
stm32_adc_buffer_postenable(struct iio_dev * indio_dev)1356 static int stm32_adc_buffer_postenable(struct iio_dev *indio_dev)
1357 {
1358 struct stm32_adc *adc = iio_priv(indio_dev);
1359 int ret;
1360
1361 if (adc->cfg->prepare) {
1362 ret = adc->cfg->prepare(adc);
1363 if (ret)
1364 return ret;
1365 }
1366
1367 ret = stm32_adc_set_trig(indio_dev, indio_dev->trig);
1368 if (ret) {
1369 dev_err(&indio_dev->dev, "Can't set trigger\n");
1370 goto err_unprepare;
1371 }
1372
1373 ret = stm32_adc_dma_start(indio_dev);
1374 if (ret) {
1375 dev_err(&indio_dev->dev, "Can't start dma\n");
1376 goto err_clr_trig;
1377 }
1378
1379 ret = iio_triggered_buffer_postenable(indio_dev);
1380 if (ret < 0)
1381 goto err_stop_dma;
1382
1383 /* Reset adc buffer index */
1384 adc->bufi = 0;
1385
1386 if (!adc->dma_chan)
1387 stm32_adc_conv_irq_enable(adc);
1388
1389 adc->cfg->start_conv(adc, !!adc->dma_chan);
1390
1391 return 0;
1392
1393 err_stop_dma:
1394 if (adc->dma_chan)
1395 dmaengine_terminate_all(adc->dma_chan);
1396 err_clr_trig:
1397 stm32_adc_set_trig(indio_dev, NULL);
1398 err_unprepare:
1399 if (adc->cfg->unprepare)
1400 adc->cfg->unprepare(adc);
1401
1402 return ret;
1403 }
1404
stm32_adc_buffer_predisable(struct iio_dev * indio_dev)1405 static int stm32_adc_buffer_predisable(struct iio_dev *indio_dev)
1406 {
1407 struct stm32_adc *adc = iio_priv(indio_dev);
1408 int ret;
1409
1410 adc->cfg->stop_conv(adc);
1411 if (!adc->dma_chan)
1412 stm32_adc_conv_irq_disable(adc);
1413
1414 ret = iio_triggered_buffer_predisable(indio_dev);
1415 if (ret < 0)
1416 dev_err(&indio_dev->dev, "predisable failed\n");
1417
1418 if (adc->dma_chan)
1419 dmaengine_terminate_sync(adc->dma_chan);
1420
1421 if (stm32_adc_set_trig(indio_dev, NULL))
1422 dev_err(&indio_dev->dev, "Can't clear trigger\n");
1423
1424 if (adc->cfg->unprepare)
1425 adc->cfg->unprepare(adc);
1426
1427 return ret;
1428 }
1429
1430 static const struct iio_buffer_setup_ops stm32_adc_buffer_setup_ops = {
1431 .postenable = &stm32_adc_buffer_postenable,
1432 .predisable = &stm32_adc_buffer_predisable,
1433 };
1434
stm32_adc_trigger_handler(int irq,void * p)1435 static irqreturn_t stm32_adc_trigger_handler(int irq, void *p)
1436 {
1437 struct iio_poll_func *pf = p;
1438 struct iio_dev *indio_dev = pf->indio_dev;
1439 struct stm32_adc *adc = iio_priv(indio_dev);
1440
1441 dev_dbg(&indio_dev->dev, "%s bufi=%d\n", __func__, adc->bufi);
1442
1443 if (!adc->dma_chan) {
1444 /* reset buffer index */
1445 adc->bufi = 0;
1446 iio_push_to_buffers_with_timestamp(indio_dev, adc->buffer,
1447 pf->timestamp);
1448 } else {
1449 int residue = stm32_adc_dma_residue(adc);
1450
1451 while (residue >= indio_dev->scan_bytes) {
1452 u16 *buffer = (u16 *)&adc->rx_buf[adc->bufi];
1453
1454 iio_push_to_buffers_with_timestamp(indio_dev, buffer,
1455 pf->timestamp);
1456 residue -= indio_dev->scan_bytes;
1457 adc->bufi += indio_dev->scan_bytes;
1458 if (adc->bufi >= adc->rx_buf_sz)
1459 adc->bufi = 0;
1460 }
1461 }
1462
1463 iio_trigger_notify_done(indio_dev->trig);
1464
1465 /* re-enable eoc irq */
1466 if (!adc->dma_chan)
1467 stm32_adc_conv_irq_enable(adc);
1468
1469 return IRQ_HANDLED;
1470 }
1471
1472 static const struct iio_chan_spec_ext_info stm32_adc_ext_info[] = {
1473 IIO_ENUM("trigger_polarity", IIO_SHARED_BY_ALL, &stm32_adc_trig_pol),
1474 {
1475 .name = "trigger_polarity_available",
1476 .shared = IIO_SHARED_BY_ALL,
1477 .read = iio_enum_available_read,
1478 .private = (uintptr_t)&stm32_adc_trig_pol,
1479 },
1480 {},
1481 };
1482
stm32_adc_of_get_resolution(struct iio_dev * indio_dev)1483 static int stm32_adc_of_get_resolution(struct iio_dev *indio_dev)
1484 {
1485 struct device_node *node = indio_dev->dev.of_node;
1486 struct stm32_adc *adc = iio_priv(indio_dev);
1487 unsigned int i;
1488 u32 res;
1489
1490 if (of_property_read_u32(node, "assigned-resolution-bits", &res))
1491 res = adc->cfg->adc_info->resolutions[0];
1492
1493 for (i = 0; i < adc->cfg->adc_info->num_res; i++)
1494 if (res == adc->cfg->adc_info->resolutions[i])
1495 break;
1496 if (i >= adc->cfg->adc_info->num_res) {
1497 dev_err(&indio_dev->dev, "Bad resolution: %u bits\n", res);
1498 return -EINVAL;
1499 }
1500
1501 dev_dbg(&indio_dev->dev, "Using %u bits resolution\n", res);
1502 adc->res = i;
1503
1504 return 0;
1505 }
1506
stm32_adc_smpr_init(struct stm32_adc * adc,int channel,u32 smp_ns)1507 static void stm32_adc_smpr_init(struct stm32_adc *adc, int channel, u32 smp_ns)
1508 {
1509 const struct stm32_adc_regs *smpr = &adc->cfg->regs->smp_bits[channel];
1510 u32 period_ns, shift = smpr->shift, mask = smpr->mask;
1511 unsigned int smp, r = smpr->reg;
1512
1513 /* Determine sampling time (ADC clock cycles) */
1514 period_ns = NSEC_PER_SEC / adc->common->rate;
1515 for (smp = 0; smp <= STM32_ADC_MAX_SMP; smp++)
1516 if ((period_ns * adc->cfg->smp_cycles[smp]) >= smp_ns)
1517 break;
1518 if (smp > STM32_ADC_MAX_SMP)
1519 smp = STM32_ADC_MAX_SMP;
1520
1521 /* pre-build sampling time registers (e.g. smpr1, smpr2) */
1522 adc->smpr_val[r] = (adc->smpr_val[r] & ~mask) | (smp << shift);
1523 }
1524
stm32_adc_chan_init_one(struct iio_dev * indio_dev,struct iio_chan_spec * chan,const struct stm32_adc_chan_spec * channel,int scan_index,u32 smp)1525 static void stm32_adc_chan_init_one(struct iio_dev *indio_dev,
1526 struct iio_chan_spec *chan,
1527 const struct stm32_adc_chan_spec *channel,
1528 int scan_index, u32 smp)
1529 {
1530 struct stm32_adc *adc = iio_priv(indio_dev);
1531
1532 chan->type = channel->type;
1533 chan->channel = channel->channel;
1534 chan->datasheet_name = channel->name;
1535 chan->scan_index = scan_index;
1536 chan->indexed = 1;
1537 chan->info_mask_separate = BIT(IIO_CHAN_INFO_RAW);
1538 chan->info_mask_shared_by_type = BIT(IIO_CHAN_INFO_SCALE);
1539 chan->scan_type.sign = 'u';
1540 chan->scan_type.realbits = adc->cfg->adc_info->resolutions[adc->res];
1541 chan->scan_type.storagebits = 16;
1542 chan->ext_info = stm32_adc_ext_info;
1543
1544 /* Prepare sampling time settings */
1545 stm32_adc_smpr_init(adc, chan->channel, smp);
1546
1547 /* pre-build selected channels mask */
1548 adc->pcsel |= BIT(chan->channel);
1549 }
1550
stm32_adc_chan_of_init(struct iio_dev * indio_dev)1551 static int stm32_adc_chan_of_init(struct iio_dev *indio_dev)
1552 {
1553 struct device_node *node = indio_dev->dev.of_node;
1554 struct stm32_adc *adc = iio_priv(indio_dev);
1555 const struct stm32_adc_info *adc_info = adc->cfg->adc_info;
1556 struct property *prop;
1557 const __be32 *cur;
1558 struct iio_chan_spec *channels;
1559 int scan_index = 0, num_channels, ret;
1560 u32 val, smp = 0;
1561
1562 num_channels = of_property_count_u32_elems(node, "st,adc-channels");
1563 if (num_channels < 0 ||
1564 num_channels > adc_info->max_channels) {
1565 dev_err(&indio_dev->dev, "Bad st,adc-channels?\n");
1566 return num_channels < 0 ? num_channels : -EINVAL;
1567 }
1568
1569 /* Optional sample time is provided either for each, or all channels */
1570 ret = of_property_count_u32_elems(node, "st,min-sample-time-nsecs");
1571 if (ret > 1 && ret != num_channels) {
1572 dev_err(&indio_dev->dev, "Invalid st,min-sample-time-nsecs\n");
1573 return -EINVAL;
1574 }
1575
1576 channels = devm_kcalloc(&indio_dev->dev, num_channels,
1577 sizeof(struct iio_chan_spec), GFP_KERNEL);
1578 if (!channels)
1579 return -ENOMEM;
1580
1581 of_property_for_each_u32(node, "st,adc-channels", prop, cur, val) {
1582 if (val >= adc_info->max_channels) {
1583 dev_err(&indio_dev->dev, "Invalid channel %d\n", val);
1584 return -EINVAL;
1585 }
1586
1587 /*
1588 * Using of_property_read_u32_index(), smp value will only be
1589 * modified if valid u32 value can be decoded. This allows to
1590 * get either no value, 1 shared value for all indexes, or one
1591 * value per channel.
1592 */
1593 of_property_read_u32_index(node, "st,min-sample-time-nsecs",
1594 scan_index, &smp);
1595
1596 stm32_adc_chan_init_one(indio_dev, &channels[scan_index],
1597 &adc_info->channels[val],
1598 scan_index, smp);
1599 scan_index++;
1600 }
1601
1602 indio_dev->num_channels = scan_index;
1603 indio_dev->channels = channels;
1604
1605 return 0;
1606 }
1607
stm32_adc_dma_request(struct iio_dev * indio_dev)1608 static int stm32_adc_dma_request(struct iio_dev *indio_dev)
1609 {
1610 struct stm32_adc *adc = iio_priv(indio_dev);
1611 struct dma_slave_config config;
1612 int ret;
1613
1614 adc->dma_chan = dma_request_slave_channel(&indio_dev->dev, "rx");
1615 if (!adc->dma_chan)
1616 return 0;
1617
1618 adc->rx_buf = dma_alloc_coherent(adc->dma_chan->device->dev,
1619 STM32_DMA_BUFFER_SIZE,
1620 &adc->rx_dma_buf, GFP_KERNEL);
1621 if (!adc->rx_buf) {
1622 ret = -ENOMEM;
1623 goto err_release;
1624 }
1625
1626 /* Configure DMA channel to read data register */
1627 memset(&config, 0, sizeof(config));
1628 config.src_addr = (dma_addr_t)adc->common->phys_base;
1629 config.src_addr += adc->offset + adc->cfg->regs->dr;
1630 config.src_addr_width = DMA_SLAVE_BUSWIDTH_2_BYTES;
1631
1632 ret = dmaengine_slave_config(adc->dma_chan, &config);
1633 if (ret)
1634 goto err_free;
1635
1636 return 0;
1637
1638 err_free:
1639 dma_free_coherent(adc->dma_chan->device->dev, STM32_DMA_BUFFER_SIZE,
1640 adc->rx_buf, adc->rx_dma_buf);
1641 err_release:
1642 dma_release_channel(adc->dma_chan);
1643
1644 return ret;
1645 }
1646
stm32_adc_probe(struct platform_device * pdev)1647 static int stm32_adc_probe(struct platform_device *pdev)
1648 {
1649 struct iio_dev *indio_dev;
1650 struct device *dev = &pdev->dev;
1651 struct stm32_adc *adc;
1652 int ret;
1653
1654 if (!pdev->dev.of_node)
1655 return -ENODEV;
1656
1657 indio_dev = devm_iio_device_alloc(&pdev->dev, sizeof(*adc));
1658 if (!indio_dev)
1659 return -ENOMEM;
1660
1661 adc = iio_priv(indio_dev);
1662 adc->common = dev_get_drvdata(pdev->dev.parent);
1663 spin_lock_init(&adc->lock);
1664 init_completion(&adc->completion);
1665 adc->cfg = (const struct stm32_adc_cfg *)
1666 of_match_device(dev->driver->of_match_table, dev)->data;
1667
1668 indio_dev->name = dev_name(&pdev->dev);
1669 indio_dev->dev.parent = &pdev->dev;
1670 indio_dev->dev.of_node = pdev->dev.of_node;
1671 indio_dev->info = &stm32_adc_iio_info;
1672 indio_dev->modes = INDIO_DIRECT_MODE | INDIO_HARDWARE_TRIGGERED;
1673
1674 platform_set_drvdata(pdev, adc);
1675
1676 ret = of_property_read_u32(pdev->dev.of_node, "reg", &adc->offset);
1677 if (ret != 0) {
1678 dev_err(&pdev->dev, "missing reg property\n");
1679 return -EINVAL;
1680 }
1681
1682 adc->irq = platform_get_irq(pdev, 0);
1683 if (adc->irq < 0) {
1684 dev_err(&pdev->dev, "failed to get irq\n");
1685 return adc->irq;
1686 }
1687
1688 ret = devm_request_irq(&pdev->dev, adc->irq, stm32_adc_isr,
1689 0, pdev->name, adc);
1690 if (ret) {
1691 dev_err(&pdev->dev, "failed to request IRQ\n");
1692 return ret;
1693 }
1694
1695 adc->clk = devm_clk_get(&pdev->dev, NULL);
1696 if (IS_ERR(adc->clk)) {
1697 ret = PTR_ERR(adc->clk);
1698 if (ret == -ENOENT && !adc->cfg->clk_required) {
1699 adc->clk = NULL;
1700 } else {
1701 dev_err(&pdev->dev, "Can't get clock\n");
1702 return ret;
1703 }
1704 }
1705
1706 if (adc->clk) {
1707 ret = clk_prepare_enable(adc->clk);
1708 if (ret < 0) {
1709 dev_err(&pdev->dev, "clk enable failed\n");
1710 return ret;
1711 }
1712 }
1713
1714 ret = stm32_adc_of_get_resolution(indio_dev);
1715 if (ret < 0)
1716 goto err_clk_disable;
1717 stm32_adc_set_res(adc);
1718
1719 if (adc->cfg->selfcalib) {
1720 ret = adc->cfg->selfcalib(adc);
1721 if (ret)
1722 goto err_clk_disable;
1723 }
1724
1725 ret = stm32_adc_chan_of_init(indio_dev);
1726 if (ret < 0)
1727 goto err_clk_disable;
1728
1729 ret = stm32_adc_dma_request(indio_dev);
1730 if (ret < 0)
1731 goto err_clk_disable;
1732
1733 ret = iio_triggered_buffer_setup(indio_dev,
1734 &iio_pollfunc_store_time,
1735 &stm32_adc_trigger_handler,
1736 &stm32_adc_buffer_setup_ops);
1737 if (ret) {
1738 dev_err(&pdev->dev, "buffer setup failed\n");
1739 goto err_dma_disable;
1740 }
1741
1742 ret = iio_device_register(indio_dev);
1743 if (ret) {
1744 dev_err(&pdev->dev, "iio dev register failed\n");
1745 goto err_buffer_cleanup;
1746 }
1747
1748 return 0;
1749
1750 err_buffer_cleanup:
1751 iio_triggered_buffer_cleanup(indio_dev);
1752
1753 err_dma_disable:
1754 if (adc->dma_chan) {
1755 dma_free_coherent(adc->dma_chan->device->dev,
1756 STM32_DMA_BUFFER_SIZE,
1757 adc->rx_buf, adc->rx_dma_buf);
1758 dma_release_channel(adc->dma_chan);
1759 }
1760 err_clk_disable:
1761 if (adc->clk)
1762 clk_disable_unprepare(adc->clk);
1763
1764 return ret;
1765 }
1766
stm32_adc_remove(struct platform_device * pdev)1767 static int stm32_adc_remove(struct platform_device *pdev)
1768 {
1769 struct stm32_adc *adc = platform_get_drvdata(pdev);
1770 struct iio_dev *indio_dev = iio_priv_to_dev(adc);
1771
1772 iio_device_unregister(indio_dev);
1773 iio_triggered_buffer_cleanup(indio_dev);
1774 if (adc->dma_chan) {
1775 dma_free_coherent(adc->dma_chan->device->dev,
1776 STM32_DMA_BUFFER_SIZE,
1777 adc->rx_buf, adc->rx_dma_buf);
1778 dma_release_channel(adc->dma_chan);
1779 }
1780 if (adc->clk)
1781 clk_disable_unprepare(adc->clk);
1782
1783 return 0;
1784 }
1785
1786 static const struct stm32_adc_cfg stm32f4_adc_cfg = {
1787 .regs = &stm32f4_adc_regspec,
1788 .adc_info = &stm32f4_adc_info,
1789 .trigs = stm32f4_adc_trigs,
1790 .clk_required = true,
1791 .start_conv = stm32f4_adc_start_conv,
1792 .stop_conv = stm32f4_adc_stop_conv,
1793 .smp_cycles = stm32f4_adc_smp_cycles,
1794 };
1795
1796 static const struct stm32_adc_cfg stm32h7_adc_cfg = {
1797 .regs = &stm32h7_adc_regspec,
1798 .adc_info = &stm32h7_adc_info,
1799 .trigs = stm32h7_adc_trigs,
1800 .selfcalib = stm32h7_adc_selfcalib,
1801 .start_conv = stm32h7_adc_start_conv,
1802 .stop_conv = stm32h7_adc_stop_conv,
1803 .prepare = stm32h7_adc_prepare,
1804 .unprepare = stm32h7_adc_unprepare,
1805 .smp_cycles = stm32h7_adc_smp_cycles,
1806 };
1807
1808 static const struct of_device_id stm32_adc_of_match[] = {
1809 { .compatible = "st,stm32f4-adc", .data = (void *)&stm32f4_adc_cfg },
1810 { .compatible = "st,stm32h7-adc", .data = (void *)&stm32h7_adc_cfg },
1811 {},
1812 };
1813 MODULE_DEVICE_TABLE(of, stm32_adc_of_match);
1814
1815 static struct platform_driver stm32_adc_driver = {
1816 .probe = stm32_adc_probe,
1817 .remove = stm32_adc_remove,
1818 .driver = {
1819 .name = "stm32-adc",
1820 .of_match_table = stm32_adc_of_match,
1821 },
1822 };
1823 module_platform_driver(stm32_adc_driver);
1824
1825 MODULE_AUTHOR("Fabrice Gasnier <fabrice.gasnier@st.com>");
1826 MODULE_DESCRIPTION("STMicroelectronics STM32 ADC IIO driver");
1827 MODULE_LICENSE("GPL v2");
1828 MODULE_ALIAS("platform:stm32-adc");
1829